Gary Ruggles, Sr Product Manger for PCIe and CXL Controller IP​, provides an provides example use cases for adoption of CXL​, an introduction to Synopsys CXL IP Solutions​, interop and proof points​.

1. Building Fast and Secure Chips with CXL IP
Sr Product Manger for PCIe and CXL Controller IP
Memory Fabric Forum 2024
Gary Ruggles

2. © 2023 Synopsys, Inc. 2
Overview
• Example Use Case and Adoption for CXL
• Introduction to Synopsys CXL IP Solutions
• Interop and Proof Points
• Summary
Synopsys Confidential Information

3. © 2023 Synopsys, Inc. 3
CXL Enabled Memory Expansion – An Exciting Use Case
One Interface Can Enable Multiple Types Of Memory
SoC
DDR Controller
DDR DIMM
DDR
DDR Controller
DDR DIMM
DDR
SoC
DDR Controller
DDR DIMM
DDR
DDR Controller
DDR DIMM
DDR
CXL
CXL
CXL
CXL
CXL CXL
CXL CXL
CXL Memory/Storage
CXL Memory/Storage
CXL Memory/Storage
CXL Memory/Storage
CXL
CXL
CXL
CXL
CXL
Memory/
Storage
CXL
Memory/
Storage
CXL
Memory/
Storage
CXL
Memory/
Storage
CXL
CXL
CXL
CXL
Memory controllers move
outside for CXL Links
Parallel DDR Interfaces:
1 or 2 DIMMS per channel
Multi-lane Serial CXL Interfaces
connected to various types of
memory/storage:
• DDR
• LPDDR
• Persistent Memory
CXL enables media independence
with a single interface:
DDR3/4/5, LPDDR 3/4/5,
Persistent Memory/Storage

4. © 2023 Synopsys, Inc. 4
CXL Use and Deployment is Exploding!
Cumulative Licenses Based on Synopsys Fiscal Years
• Growth is accelerating
• Over 130 CXL Controllers
and PHYs (32G/64G)
• Includes > 20 CXL 3.0
• Includes > 20 with IDE for
CXL 2.0 & 3.0
2020 2021 2022 2023
Cumulative CXL Licenses by Year

5. © 2023 Synopsys, Inc. 5
• Complete CXL IP solution is built on Synopsys' silicon-
proven PCI Express 5.0 IP, lowering integration risk for
device and host applications
• 512-bit CXL controller enables a highly efficient x16 link for
maximum bandwidth with extremely low latency
• Silicon-proven 32 GT/s PHY allows for more than 36 dB
channel loss across PVT variations for long reach
applications
• VC Verification IP for CXL verifies I/O, memory access, and
coherency protocol features for all link configurations up to
16 lanes and 32 GT/s data rates
• Supports the CXL 2.0 specification, with full backwards
compatibility to 1.1 and supporting all required CXL
protocols and device types
CXL IP Delivers Low Latency and High Bandwidth for AI, Memory Expansion, & Cloud Applications
Synopsys Delivers Industry's First CXL IP Solution for Breakthrough
Performance in Data-Intensive SoCs
Dr. Debendra Das Sharma
Intel Fellow and director of I/O Technology and Standards at Intel
“CXL is a key enabler for next-generation
heterogeneous computing architectures, where
CPUs and accelerators work together to deliver the
most advanced solutions. With support from
leading IP providers like Synopsys, we're well on
the way to a robust, innovative CXL ecosystem
that will benefit the whole industry."
CXL_014

6. © 2023 Synopsys, Inc. 6
Complete CXL IP 2.0/3.0 Solution
Controller + IDE, PHY, VIP Optimized for Low Latency, Small Area and Low Power
• Compliant with CXL 3.1, 2.0 & CXL 1.1 specifications providing cache coherency
and heterogenous computing for high-bandwidth workloads
• Available now with optional CXL 2.0/3.1 IDE support
• CXL Controllers with support for PCIe 5.0/6.1
– Comprehensive solution w/support for Device Host and Switch Port Modes
– Low risk CXL.io built from Synopsys silicon proven PCIe 5.0/6.1 controller
– High-bandwidth 128b/256b/512b/1024b data paths achieving low-latency performance in
x16, x8, x4 and x2 links @ up to 64 GT/s per lane
– Configurable support for Type 1, 2, 3 devices (CXL.io, CXL.mem, CXL.cache)
– Easily interfaces to on-chip bus using Native or AMBA (including CXS)
– Supports CCIX over CXL, proven in multiple customer designs
• Utilizes Silicon-proven PCIe 5.0/6.0 PHYs in multiple foundries
• Proven CXL and PCIe Interoperability with Major Host CPUs, including Intel
Sapphire Rapids
• Features targeting advanced Arm based designs, including LTI, MSI-GIC and
Arm Confidential Compute Architecture
• Industry’s First 2-party Interop and Public Compliance Demo of CXL 2.0 with
Teledyne LeCroy Excerciser/Analyzer
CXL_017
> 120 CXL Licenses to date
CXL Controller IP
Host
Device
CXL IP Prototyping Kits
IP Subsystems
PCIe 5.0/6.0 PHY IP
CXL Verification IP
DM
Switch Port
CXL IDE
Security
Module

7. © 2023 Synopsys, Inc. 7
Synopsys PCIe & CXL IDE Security Modules Protect HPC Data
Pre-verified Integrity & Data Encryption with Synopsys Controller IP
• High performance, low latency solutions meet cloud computing
demands
• Reduce risk with standards-compliant security modules
– Efficient data encryption/decryption/authentication based on
AES-GCM
– Compliant with latest specifications releases
• Fast time-to-market with plug-and-play solutions
– Seamless integration with Synopsys PCIe & CXL controllers
– Support controllers’ data bus widths and clock configurations
• Proven in 70+ design wins
• Protect against data tampering and physical attacks across
PCIe 5.0, PCIe 6.0 and CXL 2.0, CXL 3.0 interfaces

8. © 2023 Synopsys, Inc. 8
CXL Controller Interface: PCIe 6.0 (CXL.io) + CXL.cache/mem
Synopsys IP Supports Two Options: Synopsys Native CXS Interface and CXS
CXL Controller with Native Interface CXL Controller with CXS Interface
• CXL access via CXS.B
• Direct Plug-in for CMN-700 (Kampos)
and beyond
• CCIX over CXL (CCIX 2.0)
• A configuration option for all
Synopsys CXL AMBA Controllers
• Interface mix and match options:
• Native CXL.io + Native CXL.cm
• Native CXL.io + CXS CXL.cm
• AXI CXL.io + Native CXL.cm
• AXI CXL.io + CXS CXL.cm
Synopsys PCIe Gen5/Gen6 PHY
Logical PHY
Application Logic
PIPE 5.x/6.x
Synopsys
CXL 2.0/3.0
Controller
CXL.io (PCIe)
CXL.cache
ARB MUX
PCIe 5.0/6.0 Controller +
Enhancements = CXL.io
Enhancements
Application layer
Transaction layer
Link layer
CXL.cache/mem
Transaction layer
Link layer
CXL.mem
Synopsys PCIe Gen5/Gen6 PHY
Logical PHY
Arm CMN-700 (Kampos)
Coherent Mesh Network
PIPE 5.x/6.x
Synopsys
CXL 2.0/3.0
Controller
CXL.io (PCIe) AXI
CXS
ARB MUX
PCIe 5.0/6.0 Controller +
Enhancements = CXL.io
Enhancements
Application layer
Transaction layer
Link layer
CXL.cache/mem
CXS Interface
Link layer

9. © 2023 Synopsys, Inc. 9
More Comprehensive Interop Testing
More Entries in PCI-SIG Integrators List
DWC_PCIe_009
DWC_PCIe_009
• Use HAPS-based prototyping kits for testing
• Use Teledyne LeCroy Analyzer & Exerciser for internal testing
• Same platform used for PCI-SIG Compliance testing
• Successfully interoperated with > 56 Endpoints and 22 RCs for PCIe
4.0 in PCI-SIG Pre-FYI and FYI testing
• Additional interop testing with Intel, Mellanox, Teledyne LeCroy,
Marvell and others for both PCIe 4.0 and PCIe 5.0
• PCIe 6.0 Now on the PCIe 5.0 Integrators List
– PCIe 6.0 PHY and Controllers (RC and EP)
• Passed PCIe 5.0 compliance: 4 PHYs, EP and RC Controllers
– The most entries of any IP Vendor for PCIe 5.0, including CXL 2.0
– The first IP Vendor with Host IP on the 5.0 Integrators List!
Synopsys PCIe 5.0 Solution with HAPS-
80 IPKs testing with Teledyne LeCroy
Synopsys PCIe 6.0 End-to-End Solution
with HAPS-100 IPKs

10. © 2023 Synopsys, Inc. 10
CXL 2.0 Interop Demonstrations
x4 Link
Industry’s First 2-party Interop and Public Compliance
Demo of CXL 2.0
Tests Performed with
Synopsys End-to-End System
Gen3x4 and Gen3x8
• Alt protocol negotiation
• CXL.io L0 link up
• CXL.io transaction flits
• CXL.cache compliance test algorithm 1a
Interop Tests performed
with Intel Sapphire Rapids
Gen3x8
• Alt protocol negotiation
• CXL.io L0 link up
• CXL.io transaction flits
• CXL.cache compliance test algorithm 1a
End to End Synopsys Solution and Interop with Intel Sapphire Rapids

11. © 2023 Synopsys, Inc. 11
© 2023 Synopsys, Inc. 11
Synopsys and XConn - 256 Lane CXL 2.0 Switch
• Achieved first-pass silicon
success with silicon-
proven CXL and PCIe IP
• Integrates 256 lanes of
Synopsys PCIe 5 PHY
and CXL 2.0 controller in
a monolithic die
• Low latency CXL
implementation
• Met critical 1GHz timing
closure, low latency,
power and performance
requirements
World’s First CXL 2.0 Switch SoC, Highest Capacity In The Market

12. © 2023 Synopsys, Inc. 12
Industry First 64GT/s Link-up – Synopsys and Keysight
PCIe 6.0 is incorporated into CXL 3.0 as CXL.io
• January 27, 2023
• Hillsboro, Oregon Synopsys lab
• Clean link-up to 64 GT/s L0, no trips to
RCVRY
PCIe_Proof_013

13. © 2023 Synopsys, Inc. 13
NEW
Image or
article goes
here
Synopsys Demonstrates Industry’s First Interoperability of
PCI Express 6.0 IP with Intel’s PCIe 6.0 Test Chip
• Synopsys and Intel achieved end-to-end
64 GT/s interop between Synopsys PCIe 6.0 IP and
Intel PCIe 6.0-enabled test chip
• Validates that PCIe 6.0 solutions from Synopsys or
Intel interoperate with the ecosystem, reducing
design and integration risk
• Demonstrates the robustness of Synopsys IP for
PCIe 6.0, which has >30 design wins
Joint 64 GT/s Demo Reduces Integration Risk for Advanced High-Performance Computing SoCs
Debendra Das Sharma
Senior Fellow and co-GM of Memory and I/O
Technologies at Intel Corporation
Intel’s close collaboration with Synopsys, a
leading PCIe IP provider, has once again
resulted in successful interoperability using
the latest PCIe standard.
PCIe_Proof_012

14. © 2023 Synopsys, Inc. 14
Synopsys PCIe 6.0 Solution on Integrators List
For Both Root Complex & End Point
The only PCIe 6.0 Solution in PCI-SIG RC/EP Integrators List
Compliance ensures first
pass interoperability with
existing Gen 5 systems
Only PCIe 6.0 Solution to
demonstrate End to End
FLIT transfer & rate changes
Only PCIe 6.0 solution to
demonstrate multi vendor
Interoperability

15. © 2023 Synopsys, Inc. 15
Synopsys CXL 3.0/3.1 Feature Support
Synopsys Confidential Information

16. © 2023 Synopsys, Inc. 16
Synopsys CXL 3.0 Feature Support
(includes Full-featured PCIe 6.1 support)
CXL_040
Feature Support for CXL 3.0
1024b/512b/256b/128b PCIe datapath Architectures
Synopsys Native CXL Interface support
AXI (CXL.io) + CXS Interface support
256 Byte Standard Flit support
256 Byte Latency Optimized Flit support
Device/Host/DM Support
L0p support in CXL 3.0 mode
Multiple Logic Devices (MLD)
CXL Back Invalidate
CXL Cache Scaling
Switch Port support: HBR and PBR
PBR support for EP (GFAM)
IDE for CXL 3.0 Native and CXS Interfaces
UIO Direct P2P to HDM

17. © 2023 Synopsys, Inc. 17
Synopsys CXL 3.1 Feature support
New Features Supported for CXL 3.1
Support for Applicable CXL 3.1 Errata
Direct P2P CXL.mem
TSP
Extended Meta-Data Trailers
Header Logging

18. © 2023 Synopsys, Inc. 18
Summary
A comprehensive, proven CXL portfolio with advanced features and performance
• The broadest CXL IP Portfolio
– Controllers covering CXL 2.0 and CXL 3.0/3.1, including broad coverage of PCIe 6.0 features and CNs
– PHYs in many foundries for both CXL 2.0 (32G) and CXL 3.0 (64G)
• The Lowest Risk solution
– Synopsys was invited to be the only “Early Contributor” for CXL resulting in early spec access and the most mature CXL controller
– Synopsys already has over 120 CXL licenses, and more than 350 PCIe 5.0 licenses, with many customers already in silicon
– Over 50 PCIe 6 licenses, including over 20 CXL 3.0/3.1
– Multiple licenses for CXL 3.0 solution, including IDE for both CXL 2.0 and CXL 3.0
• Complete solution for CXL 2.0/3.0 + PHYs + IDE + VIP, including Si-proven 32G and 64G PHYs with broad foundry support
• Support for Device, Host and Dual-Mode configurations, and SW Port for CXL 2.0/CXL 3.0
• Extremely low latency CXL solution
• Customer-Proven 1 GHz timing closure to facilitate 32GT/s using 32b PIPE and 64GT/s using 64b PIPE
• Optimized datapath architectures supporting x2 to x16 lane widths
• Powerful coreConsultant configuration tool to explore architectural tradeoffs at your Desk to create optimized solution; adjust
parameters and see simulation results in minutes
• Leveraging industry’s most advanced RAS-DES with extensions to cover CXL features and simplify debug & software
development
• Flexible interface support for AMBA or optimized low-latency Native interface
• Supporting advanced Arm based SoC features like LTI, MSI-GIC and Arm Confidential Compute Architecture (CCA)
CXL_025

19. © 2023 Synopsys, Inc. 19
How to Find Out More about Synopsys CXL IP Solutions
• For more information about Synopsys CXL Solutions contact to your Synopsys
Sales representative or FAE
• If you are not sure about your Sales Rep or FAE, please contact
Gary Ruggles
ruggles@synopsys.com
Synopsys Confidential Information

20. Thank You
Synopsys Confidential Information