System-on-Chip Design
Introduction to Zynq
Dr Hao Zheng
Computer Sci. & Eng.
U. of South Florida
• Chapter 1: Introduction
• Chapter 2: The Zynq Device (“What is it?)
• Chapter 5: Applications and Opportunities
(“What can I do with it?”)
The ZYNQ Book
Xilinx Educational Video
• Why Zynq?
http://www.xilinx.com/training/zynq/why-zynq.htm
Reading
Source: The Zynq Book
Traditional Architecture
Source: The Zynq Book
FPGA with Soft Processor Core
Source: The Zynq Book
Zynq Architecture
Source: The Zynq Book
Embedded SoC Architecture
Source: The Zynq Book
Implement Embedded SoC on Zynq
Source: Xilinx Video Tutorials
Zynq Highlights
ARM Processor Roadmap
Source: Xilinx White Paper: Extensible Processing Platform
Basic Design Flow for Zynq SoC
Source: The Zynq Book
Zynq SoC Ecosystem
Source: The Zynq Book
Zynq SoC Ecosystem
Xilinx Zynq
Zynq-7000 All Programmable
SoCs with Cortex-A9 MPCore
Altera Arria V & Cyclone V
Hard processor system (HPS)
with Cortex-A9 MPCore
Microsemi Smartfusion2
Cortex M3
Alternative Solutions
Source: The Zynq Book
The Zynq Processing System
Source: The Zynq Book
Application Processing Unit (APU)
APU programming is through Xlinx SDK
Source: The Zynq Book
NEON Co-Processor
SIMD Execution for media and DSP applications
Source: The Zynq Book
PS External Interfaces: MIO
Programmable Logic (PL) CLBs and IOBs
Source: The Zynq Book
Basic Logic Elements (BLEs)
12 2 FPGA Architectures: An Overview
Switch Matrix
16 2 FPGA Architectures: An Overview
Source: The Zynq Book
PL: Special Resources
Source: The Zynq Book
AXI Interconnects and Interfaces
9 AXI interfaces
between PS and
PL.
Basic AXI Signaling – 5 Channels
1. Read Address Channel
2. Read Data Channel
3. Write Address Channel
4. Write Data Channel
5. Write Response Channel
Zynq Architecture 12-33 © Copyright 2012 Xilinx
The AXI Interface—AX4-Lite
No burst
Data width 32 or 64 only
– Xilinx IP only supports 32-bits
Very small footprint
Bridging to AXI4 handled
automatically by
AXI_Interconnect (if needed)
AXI4-Lite Read
AXI4-Lite Write
Zynq Architecture 12-34 © Copyright 2012 Xilinx
The AXI Interface—AXI4
Sometimes called “Full AXI” or “AXI
Memory Mapped”
– Not ARM-sanctioned names
Single address multiple data
– Burst up to 256 data beats
Data Width parameterizable
– 1024 bits
AXI4 Read
AXI4 Write
Zynq Architecture 12-35 © Copyright 2012 Xilinx
The AXI Interface—AXI4-Stream
No address channel, no read and write,
always just master to slave
– Effectively an AXI4 “write data” channel
Unlimited burst length
– AXI4 max 256
– AXI4-Lite does not burst
Virtually same signaling as AXI Data
Channels
– Protocol allows merging, packing, width
conversion
– Supports sparse, continuous, aligned,
unaligned streams
AXI4-Stream Transfer
Zynq Architecture 12-36 © Copyright 2012 Xilinx
Using Extended Multiplexed Input/Output
(EMIO) to Interface Between PS and PL
Source: The Zynq Book
Choice Among Various
Implementation Platforms
Source: Xcell Journal, no. 88, Q3 2014
Advantages of Zynq
Source: Xcell Journal, no. 88, Q3 2014
Academic Subjects to which Zynq is Relevant
Source: The Zynq Book
Zedboard
Zynq device
DDR3 mem
VGA port
Ethernet
SD card
Backup
Source: The Zynq Book
System-on-a-Board
Source: The Zynq Book
System-on-Chip (SoC)
Design Flow for Zynq SoC
Source: Xilinx White Paper: Extensible Processing Platform
Automotive Applications
Automotive Applications
Lane and Road Sign Recognition
Source: The Zynq Book
Computer Vision
Detection of Cars at a Junction
Source: The Zynq Book
Smart
Home
Source: The Zynq Book
Communication Systems
Wireless
Basestation
Satellite
Groundstation
Wired Network
Switches
Source: The Zynq Book
Control and Instrumentation Systems
Industrial
Control
Room
Wind
Turbines
High Energy
Physics
Experiment
Source: The Zynq Book
Medical Applications
MRI Scanning Robot Assisted Surgery
Source: The Zynq Book
ZYBO General Purpose Input Output (GPIO)
Source: ZYBO Reference Manual
Pmod Connector
Source: ZYBO Reference Manual

zynq.ppt