Kunyuan Wang has a Master's degree in Electrical Engineering from USC and dual Bachelor's degrees from Luebeck University of Applied Sciences and East China University of Science and Technology. He has experience in programming languages like C/C++, Verilog, and SystemVerilog. Some of his academic projects include redesigning a UVM verification project using SystemVerilog, debugging an FPGA design, and implementing placement and routing algorithms. He also designed a full custom general purpose pipelined microprocessor using Cadence Virtuoso. Previously, he worked as a junior engineer at Taiping Life Insurance where he provided IT support and conducted statistical analysis.

1. Kunyuan Wang
645 W 23rd
St Apt.4, Los Angeles, CA, 90007 Email: kunyuan.wang@hotmail.com TEL: (323)3141547
Education
Viterbi School of Engineering, University of Southern California Los Angeles, US
Master of Science in Electrical Engineering GPA: 3.73/4.0 Graduated in August 2015
Relevant Coursework: Verification of VLSI Systems, Computer System Organization, VLSI System Design, Computer
Aided Design of Digital Systems, MOS VLSI Circuit Design, Internet and Cloud Computing.
(Dual Bachelor Degrees Program)
Luebeck University of Applied Sciences (Phase Two) Lübeck, Germany
Bachelor of Science in Information and Technology GPA: 3.5/4.0 Graduated in August 2013
East China University of Science and Technology (Phase One) Shanghai, China
Bachelor of Science in Electrical Engineering and Automation GPA: 3.5/4.0 Finished in February 2012
Technical Skills
Programming Languages: C/C++, Verilog, SystemVerilog, Perl.
Software Applications: Cadence Virtuoso, ModelSim, Quartus, PrimeTime, Design Compiler.
Operating System: Mac, Windows, UNIX.
Academic Projects
UVM Verification and Redesign Project (SystemVerilog) Summer, 2015
 Redesigned code to complete UVM structure with new fifo and pipe file.
 Implemented SystemVerilog interface connecting new DUT to UVM testbench.
 Created object-based testbench including sequencer, driver, monitor, scoreboard, coverage class.
FPGA Prototyping and Code Coverage (Quartus II) Summer, 2015
 Debugged the FPGA Design with given constraints and performed Code Coverage simulation.
 Synthesized the design on FPGA board, and optimized the timing parameters.
FPGA placement & routing implementation (Netlist based, SA, Lee’s Algorithm, C++) Spring, 2015
 Handled netlist and FPGA configuration files to implement the FPGA placement and routing task via C++.
 Applied Simulated Annealing Heuristic to resolve placement.
 Implemented routing using Lee's algorithm, dynamic programming and negotiation-based routing.
Full Custom General Purpose Pipelined Microprocessor (Cadence Virtuoso, Perl) Fall, 2014
 Designed schematic and layout of a general purpose CPU supporting basic MIPs instructions using 256bit SRAM,
Dynamic Carry-Lookahead Adder, pipelined CSA-
 Performed Perl script to compile the instructions and automatically generate the input vector files and check the output
results with the golden results.
Professional Experience
Taiping Life Insurance Co., Ltd Shanghai, China Sep.2011 – Dec.2011
Position: Junior engineer at Operation Department
 Installed and tested camera and microphone equipment in conference room, provided computer maintenance service
for colleagues.
 Recorded clarified insurance information, conducted statistics to investigate correlation of income and products.