Neeraj is seeking full-time positions in physical design, SoC design, circuit design, or backend VLSI starting in May 2020. He has a Master of Science degree from the University of Minnesota expected in May 2020 with a GPA of 3.6. His skills include Verilog, C/C++, Python, and CAD tools like Cadence and Synopsys. For his graduate project, he designed a 128Kbit SRAM with a 7nm ASAP PDK and a ring oscillator with automated layout using SKILL. He has work experience in automotive meter model design and supply chain management.

1. NEERAJ
1701 Elm St. SE, Apt No. 204, MN - 55414
Phone - +1 (651) 4422281 | Email – neera003@umn.edu | LinkedIn Profile - http://www.linkedin.com/in/fnu-neeraj-78419250
Objective
I am looking for Full time positions in the field of Physical Design/SoC Design/Circuit Design/Backend VLSI starting May 2020.
Education
Master of Science | Sep 2018 - May 2020 (expected) | University of Minnesota, Twin Cities GPA: 3.6(Expected)
Coursework: VLSI Design 2 (Memories and Low Power Design), VLSI Design Lab (RTL to GDSII flow), VLSI Design 1 (CMOS
devices and circuit design), VLSI Design Automation (Backend CAD algorithms for routing, floor planning, partitioning and placement),
Advanced Verification of VLSI Design (SystemVerilog and UVM), Circuits and Computational Biology(Non-traditional computing
models),Systems Engineering 2.
Bachelor of Engineering | Sep 2012 - Jun 2016 | SJ College of Engineering, India GPA: 9.73/10
Skills & Abilities
Programming Languages - C/C++, Verilog, Python, SKILL.
Design and Simulation Tools - Cadence – Virtuoso,
Synopsys - Cosmoscope, HSPICE,VCS,DVE,IC Compiler, Design Compiler
Mentor Graphics - Calibre (DRC, LVS and PEX),
MATLAB – Scripting,SimuLink, Stateflow.
Others - RTL to GDSII, Static Timing Analysis, 7nm Technology node, FINFETs, OS : Windows, Linux.
Academic Projects
Graduate Academic Project (Fall 2018):
Full Custom Design of Schematic and Layout of a Memory circuit for 128Kbit SRAM with ASAP 7nm PDK
• Designing of 128Kbit SRAM (512x256) with an intention of minimal area coupled with optimal performance at low power. Designing of
the Schematic and Layout of row decoder and pre-decoder in ASAP 7nm Technology node PDK was completed successfully.
• 6T SRAM cell custom design with analog mux,precharge,sense amplifier and write circuit.
• Design of Row Decoder Schematic compromised of address, clock buffers, pre-decoder, pre-decoder buffers and RC distributed network
by extraction of RC values for different metal interconnects. The layout was designed to be fully automated using the SKILL Language.
Custom Layout Design of Ring Oscillator in 7nm FINFET Tech using ASAP 7nm PDK
• Schematic and layout of the oscillator designed in Cadence Virtuoso and simulation using HSPICE.
• Fully automated layout placement using SKILL code to provide N-stage ring oscillator with minimal area, optimal cell placement and
automated metal routing with via placement.
Simulated Annealing Placement for non-slicing floorplan with Area, Wirelength and both optimizations
• C++ STL used to implement an annealing-based non-slicing floorplan placement and later the engine was optimized for 3 options
• The optimization with Area, optimization with Wirelength and optimization with both were the 3 options of optimizations.
Design of Static Timing Analyser Tool using the C++ Standard Template Library
• This STA tool was designed using the C++ STL to perform timing analysis for benchmarks from the ISCAS85 suite.
• The program parses the netlist and obtains capacitance and slew values from the Non-Linear Delay Model (NLDM) library for each gate
and stores the connectivity information in the form of C++ STL vectors.
• The critical path load capacitance, arrival time, slew and slack of every node was computed and tested in C++ using the STL.
Device Characterization in ASAP 7nm Predictive PDK
• Parameters: Body Effect Coefficient, DIBL coefficient, Sub-threshold swing, Channel length Modulation, Delay vs fanout of inverter was
simulated and analysed. Sheet resistance of Metal layers from M1 to M9 was extracted from the layout.
Stochastic Computing based Arithmetic Logic Unit
• Design and Testing of the adder, multiplier and random bit stream generator LFSR.
• The RTL to full GDSII flow for the designed ALU with area and power optimizations.
Work Experience
Assistant System Engineer | Tata Consultancy Services – Nagpur, India Dec 2016 – May 2018
- Designing of Meter models functions using Model Based Design tools like MATLAB/Simulink for -Nissan Account. Special functions
like Wake-Up-and-Sleep functions which complied with AUTOSAR Architecture was designed and tested.
- Developing and testing of the functions with optimized design and SIL, MIL, HIL testing inclusive.
- Meter models verification and validation with AUTOSAR compliance. Training named Initial Learning Program (ILP) for 3 months.
Graduate Engineer Trainee | Larsen and Toubro Construction– Chennai, India Jul 2016 – Nov 2016
- In Smart World and Communication BU(Business Unit) of WET (Water and Effluent Treatment) IC(Independent Company) as a GET in
Supply Chain Management division. Training named PRAVAS program for Graduate Engineer Trainees (Training – 1 month) completed.
Honors and Awards
Rank Certificate: May 2016, LIREL awardee at TCS: Feb 2017, Learning Achievement Award: May 2018
WORK AUTHORIZATION: Eligible to intern in the United States of America with Curricular Practical Training.