Scrambler is generally employed in data communication systems to add redundancy in the transmitted data stream so that at the receiver end, timing information can be retrieved to aid the synchronization between data terminals. Present paper deals with simulation and implementation of the scrambler for 56Kbps voice-band modem. Scrambler for the transmitter of 56kbps modem was chosen as a case study. Simulation has been carried out using Simulink of Matlab. An algorithm for the scrambling function has been developed and implemented on Texas Instrument’s based TMS320C50PQ57 Digital Signal Processor (DSP). Signalogic DSP software has been used to compare the simulated and practical results.
COMPARATIVE ANALYSIS OF ROUTE INFORMATION BASED ENHANCED DIVIDE AND RULE STRA...ijsc
In wireless sensor network, routing data efficiently to the base station is a big issue and for this purpose, a
number of routing algorithms are invented by researchers. Clustering plays a very important role in the
design and as well as development of wireless sensor networks for well distribution of network and also to
route data efficiently. In this paper, we had done the enhancement of divide and rule strategy that is
basically route information protocol based upon static clustering and dynamic cluster head selection.
Simulation results show that our technique outperforms DR, LEACH, and AODV on the basis of packet
loss, delay, and throughput.
ASSURED NEIGHBOR BASED COUNTER PROTOCOL ON MAC-LAYER PROVIDING SECURITY IN MO...cscpconf
In this paper, we have taken out the concern of security on a Medium Access Control layer
implementing Assured Neighbor based Security Protocol to provide the authentication,
confidentiality and taking in consideration High speed transmission by providing security in
parallel manner in both Routing and Link Layer of Mobile Ad hoc Networks. We basically
divide the protocol into two different segments as the first portion concentrates, based on
Routing layer information; we implement the scheme for the detection and isolation of the
malicious nodes. The trust counter for each node is maintained which actively increased and
decreased considering the trust value for the packet forwarding. The threshold level is defined differencing the malicious and non malicious nodes. If the value of the node in trust counter lacks below the threshold value then the node is considered as malicious. The second part focus on providing the security in the link layer, the security is provided using CTR (Counter) approach for authentication and encryption. Hence simulating the results in NS-2, we come to conclude that the proposed protocol can attain high packet delivery over various intruders while attaining low delays and overheads.
Efficient algorithm for rsa text encryption using cuda ccsandit
Modern-day computer security relies heavily on cryptography as a means to protect the data
that we have become increasingly reliant on. The main research in computer security domain
is how to enhance the speed of RSA algorithm. The computing capability of Graphic Processing
Unit as a co-processor of the CPU can leverage massive-parallelism. This paper presents a
novel algorithm for calculating modulo value that can process large power of numbers
which otherwise are not supported by built-in data types. First the traditional algorithm is
studied. Secondly, the parallelized RSA algorithm is designed using CUDA framework. Thirdly,
the designed algorithm is realized for small prime numbers and large prime number . As a
result the main fundamental problem of RSA algorithm such as speed and use of poor or
small prime numbers that has led to significant security holes, despite the RSA algorithm's
mathematical soundness can be alleviated by this algorithm.
Reactive/Proactive Connectivity Management in a Tactical Service-Oriented Inf...Roberto Rigolin F. Lopes
This document summarizes a presentation on reactive and proactive connectivity management in a tactical service-oriented infrastructure. The presentation covers three main topics: 1) introducing a scenario and quality of service requirements for tactical networks, 2) describing a service-oriented model and connectivity management approach, and 3) presenting quantitative analysis results from simulating different mobility patterns and network sizes. The goal of the research is to develop an architecture called Tactical Service Infrastructure (TSI) that can manage connectivity challenges in tactical networks by handling both stable and unstable network conditions through distributed services and core services.
30 9762 extension paper id 0030 (edit i)IAESIJEECS
This paper deals with border distortion effect at starting and ending of finite signal by proposing sliding window technique and basic extension mode implementation. Single phase of transient and voltage sag is chosen to be analyzed in wavelet. The signal which being used for the analysis is simulated in Matlab 2017a. Disturbance signal decomposes into four level and Daubechies 4 (db4) has been chosen for computation. The proposed technique has been compared with conventional method which is finite length power disturbance analysis. Simulation result revealed that the proposed smooth-padding mode can be successfully minimized the border distortion effect compared to the zero-padding and symmetrization
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET- Appraisal of Secure Data Aggregation protocol for Wireless Sensor ...IRJET Journal
This document summarizes research on secure data aggregation protocols for wireless sensor networks. It first introduces wireless sensor networks and discusses how data aggregation can help reduce energy usage by aggregating sensor data as it travels towards a base station. However, data aggregation also presents security risks if sensor data is compromised. The document then reviews different types of attacks against wireless sensor networks, such as denial of service attacks and false data injection attacks. It also discusses security goals like data confidentiality, integrity, and availability. Several existing secure data aggregation protocols are then summarized, including techniques using public/private key cryptography and probabilistic encryption to securely aggregate and transmit sensor data while preventing attacks. The document concludes that security is an important challenge for data aggregation in wireless sensor
IMPROVING SCHEDULING OF DATA TRANSMISSION IN TDMA SYSTEMScsandit
In an era where communication has a most important role in modern societies, designing efficient
algorithms for data transmission is of the outmost importance. TDMA is a technology used in many
communication systems such as satellites and cell phones. In order to transmit data in such systems we
need to cluster them in packages. To achieve a faster transmission we are allowed to preempt the
transmission of any packet in order to resume at a later time. Such preemptions though come with a delay
in order to setup for the next transmission. In this paper we propose an algorithm which yields improved
transmission scheduling. This algorithm we call MGA. We have proven an approximation ratio for MGA
and ran experiments to establish that it works even better in practice. In order to conclude that MGA will
be a very helpful tool in constructing an improved schedule for packet routing using preemtion with a setup
cost, we compare its results to two other efficient algorithms designed by researchers in the past.
COMPARATIVE ANALYSIS OF ROUTE INFORMATION BASED ENHANCED DIVIDE AND RULE STRA...ijsc
In wireless sensor network, routing data efficiently to the base station is a big issue and for this purpose, a
number of routing algorithms are invented by researchers. Clustering plays a very important role in the
design and as well as development of wireless sensor networks for well distribution of network and also to
route data efficiently. In this paper, we had done the enhancement of divide and rule strategy that is
basically route information protocol based upon static clustering and dynamic cluster head selection.
Simulation results show that our technique outperforms DR, LEACH, and AODV on the basis of packet
loss, delay, and throughput.
ASSURED NEIGHBOR BASED COUNTER PROTOCOL ON MAC-LAYER PROVIDING SECURITY IN MO...cscpconf
In this paper, we have taken out the concern of security on a Medium Access Control layer
implementing Assured Neighbor based Security Protocol to provide the authentication,
confidentiality and taking in consideration High speed transmission by providing security in
parallel manner in both Routing and Link Layer of Mobile Ad hoc Networks. We basically
divide the protocol into two different segments as the first portion concentrates, based on
Routing layer information; we implement the scheme for the detection and isolation of the
malicious nodes. The trust counter for each node is maintained which actively increased and
decreased considering the trust value for the packet forwarding. The threshold level is defined differencing the malicious and non malicious nodes. If the value of the node in trust counter lacks below the threshold value then the node is considered as malicious. The second part focus on providing the security in the link layer, the security is provided using CTR (Counter) approach for authentication and encryption. Hence simulating the results in NS-2, we come to conclude that the proposed protocol can attain high packet delivery over various intruders while attaining low delays and overheads.
Efficient algorithm for rsa text encryption using cuda ccsandit
Modern-day computer security relies heavily on cryptography as a means to protect the data
that we have become increasingly reliant on. The main research in computer security domain
is how to enhance the speed of RSA algorithm. The computing capability of Graphic Processing
Unit as a co-processor of the CPU can leverage massive-parallelism. This paper presents a
novel algorithm for calculating modulo value that can process large power of numbers
which otherwise are not supported by built-in data types. First the traditional algorithm is
studied. Secondly, the parallelized RSA algorithm is designed using CUDA framework. Thirdly,
the designed algorithm is realized for small prime numbers and large prime number . As a
result the main fundamental problem of RSA algorithm such as speed and use of poor or
small prime numbers that has led to significant security holes, despite the RSA algorithm's
mathematical soundness can be alleviated by this algorithm.
Reactive/Proactive Connectivity Management in a Tactical Service-Oriented Inf...Roberto Rigolin F. Lopes
This document summarizes a presentation on reactive and proactive connectivity management in a tactical service-oriented infrastructure. The presentation covers three main topics: 1) introducing a scenario and quality of service requirements for tactical networks, 2) describing a service-oriented model and connectivity management approach, and 3) presenting quantitative analysis results from simulating different mobility patterns and network sizes. The goal of the research is to develop an architecture called Tactical Service Infrastructure (TSI) that can manage connectivity challenges in tactical networks by handling both stable and unstable network conditions through distributed services and core services.
30 9762 extension paper id 0030 (edit i)IAESIJEECS
This paper deals with border distortion effect at starting and ending of finite signal by proposing sliding window technique and basic extension mode implementation. Single phase of transient and voltage sag is chosen to be analyzed in wavelet. The signal which being used for the analysis is simulated in Matlab 2017a. Disturbance signal decomposes into four level and Daubechies 4 (db4) has been chosen for computation. The proposed technique has been compared with conventional method which is finite length power disturbance analysis. Simulation result revealed that the proposed smooth-padding mode can be successfully minimized the border distortion effect compared to the zero-padding and symmetrization
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET- Appraisal of Secure Data Aggregation protocol for Wireless Sensor ...IRJET Journal
This document summarizes research on secure data aggregation protocols for wireless sensor networks. It first introduces wireless sensor networks and discusses how data aggregation can help reduce energy usage by aggregating sensor data as it travels towards a base station. However, data aggregation also presents security risks if sensor data is compromised. The document then reviews different types of attacks against wireless sensor networks, such as denial of service attacks and false data injection attacks. It also discusses security goals like data confidentiality, integrity, and availability. Several existing secure data aggregation protocols are then summarized, including techniques using public/private key cryptography and probabilistic encryption to securely aggregate and transmit sensor data while preventing attacks. The document concludes that security is an important challenge for data aggregation in wireless sensor
IMPROVING SCHEDULING OF DATA TRANSMISSION IN TDMA SYSTEMScsandit
In an era where communication has a most important role in modern societies, designing efficient
algorithms for data transmission is of the outmost importance. TDMA is a technology used in many
communication systems such as satellites and cell phones. In order to transmit data in such systems we
need to cluster them in packages. To achieve a faster transmission we are allowed to preempt the
transmission of any packet in order to resume at a later time. Such preemptions though come with a delay
in order to setup for the next transmission. In this paper we propose an algorithm which yields improved
transmission scheduling. This algorithm we call MGA. We have proven an approximation ratio for MGA
and ran experiments to establish that it works even better in practice. In order to conclude that MGA will
be a very helpful tool in constructing an improved schedule for packet routing using preemtion with a setup
cost, we compare its results to two other efficient algorithms designed by researchers in the past.
Lossless Data Compression Using Rice Algorithm Based On Curve Fitting TechniqueIRJET Journal
This document describes a lossless data compression technique called the Rice algorithm and a modification of the Rice algorithm using curve fitting. The Rice algorithm uses a two-stage approach of preprocessing data to decorrelate it followed by entropy coding to assign variable-length codes. The modified Rice algorithm uses curve fitting to generate a function to predict future data points for improved compression performance compared to the original Rice algorithm. Simulation results show the modified algorithm achieves better compression by selecting an encoding option that uses fewer bits than the original Rice algorithm on a sample data set.
Enchancing the Data Collection in Tree based Wireless Sensor Networksijsrd.com
Number of techniques used in Wireless Sensor Network to improve data collection from sensor nodes. It achieve by minimize the schedule length and dynamic channel assignment. Schedule length minimized by BFS algorithm without interfering links. Interfering links can be eliminated by transmission power control and multi frequency. The power can be save by using beacon signal. Collection of data can also be limited by topology of network. So the nodes are arranged in form. The capacitated minimal spanning trees and degree- constrained spanning trees give significant improvement in scheduling. Finally the data collection is enhancing in terms of security by using T-Hash Chain algorithm.
A SECURE DIGITAL SIGNATURE SCHEME WITH FAULT TOLERANCE BASED ON THE IMPROVED ...csandit
Fault tolerance and data security are two important issues in modern communication systems.
In this paper, we propose a secure and efficient digital signature scheme with fault tolerance
based on the improved RSA system. The proposed scheme for the RSA cryptosystem contains
three prime numbers and overcome several attacks possible on RSA. By using the Chinese
Reminder Theorem (CRT) the proposed scheme has a speed improvement on the RSA decryption
side and it provides high security also.
Efficient Broadcast Authentication with Highest Life Span in Wireless Sensor ...IRJET Journal
This document discusses efficient broadcast authentication to maximize the lifetime of wireless sensor networks. It proposes using a greedy heuristics algorithm with the X-TESLA broadcast authentication protocol. X-TESLA uses short key chains to authenticate broadcast messages but has limitations regarding sleep modes, network failures, idle sessions, extended lifetime, and denial-of-service attacks. The proposed approach combines X-TESLA with greedy heuristics to address these issues and significantly improve network lifetime compared to using each approach alone. It aims to find a broadcast tree that maximizes the minimum residual energy of nodes after broadcasting to prolong the ability of the network to complete future broadcasts.
Minimum distance based routing protocol for lifetime improvement in wireless ...eSAT Journals
Abstract Balanced utilization of energy of wireless sensor nodes is a challenge while designing wireless sensor network (WSN). This energy of sensor node is a limited resource and measure for the lifespan of WSN. Communication process consumes most of the energy of sensor node hence; energy of sensor node becomes a major design issue for WSN. Clustering is preferred while designing routing protocols for WSN for its many to one traffic pattern. In our minimum distance based routing protocol for lifetime improvement in WSN (MDBRP) clusters are formed once in a lifetime and their heads are selected rotationally based on minimum communication distance between nodes and their next hop. MDBRP considers minimum energy consumption which aims to increase the overall lifespan of WSN. Keywords— clustering, dynamic clustering, routing protocol, static clustering, wireless sensor network.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Limit energy is a severe bottleneck of wireless sensor networks (WSNs), and limits network lifetime of WSNs. To extend network lifetime, buffer zone has been proposed. Sensors send their data packets to buffer zone. The sensors in buffer zone buffer the data packets. And then the sink visits the buffer zone to collect the data ackets. This leads to that the loads of the sensors in buffer zone are too high and the sensors die quickly. To further extend network lifetime, an algorithm based on dynamic buffer zone has been proposed in this paper. The algorithm divides the whole network area into some areas, and lets all areas act as the buffer zone in turn. And the reasonable times each zone acts as the buffer zone are computed with linear programming. The simulation results have shown that our proposed algorithm notably extends network lifetime.
IRJET- Data Embedding using Image SteganographyIRJET Journal
This document presents a method for secure communication using both steganography and cryptography techniques. It discusses embedding encrypted text into an image using discrete wavelet transform (DWT). Specifically, it first encrypts a text message using the advanced encryption standard (AES) algorithm. It then embeds the encrypted text into an image by applying DWT to decompose the image into sub-bands and hiding the data in the high frequency sub-bands. MATLAB is used to implement a graphical user interface that allows a sender to encrypt a message, embed it into an image, and send the stego-image to a receiver. The receiver interface extracts the encrypted text from the stego-image and decrypts it using AES. The method aims to
The document proposes a Congestion Control Anonymous Gossip (CCAG) protocol to improve reliable packet delivery in multicast routing protocols for mobile ad-hoc networks (MANETs). The CCAG protocol uses a two phase approach, first using an existing multicast protocol like MAODV to disseminate messages unreliably, then using a gossip protocol in the background to reliably recover any lost messages. The gossip protocol implements anonymous gossip, locality of gossip, cached gossip, and pull-based message exchange to provide reliability while minimizing overhead. Simulation results show the CCAG protocol achieves a 22% improvement in packet delivery ratio over MAODV, while also reducing congestion and variation in packets received by nodes.
Multiple Downlink Fair Packet Scheduling Scheme in Wi-MaxEditor IJCATR
IEEE 802.16 is standardization for a broadband wireless access in network metropolitan area network (MAN). IEEE 802.16
standard (Wi-Max) defines the concrete quality of service (QoS) requirement, a scheduling scheme and efficient packet scheduling
scheme which is necessary to achieve the QoS requirement. In this paper, a novel waiting queue based on downlink bandwidth
allocation architecture from a number of rtps schedule has been proposed to improve the performance of nrtPS services without any
impaction to other services. This paper proposes an efficient QoS scheduling scheme that satisfies both throughput and delay guarantee
to various real and non-real applications corresponding to different scheduling schemes for k=1,2,3,4. Simulation results show that
proposed scheduling scheme can provide a tight QoS guarantee in terms of delay for all types of traffic as defined in WiMax standards.
This process results in maintaining the fairness of allocation and helps to eliminate starvation of lower priority class services. The
authors propose a new efficient and generalized scheduling schemes for IEEE 802.16 broadband wireless access system reflecting the
delay requirements.
The MAC architecture is used in real time digital signal processing and multimedia information
processing which requires high throughput. A novel method to estimate the transition activity at
the nodes of a multiplier accumulator architecture based on modified booth algorithm
implementing finite impulse response filter is proposed in this paper. The input signals are
described by a stationary Gaussian process and the transition activity per bit of a signal word is
modeled according to the dual bit type (DBT) model. This estimation is based on the
mathematical formulation by multiplexing mechanism on the breakpoints of the DBT model.
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEcscpconf
In recent years, various chaos based modulation schemes were evolved, of which the CS-DCSK
modulation technique provides better BER performance and bandwidth efficiency, due to its
code domain approach. The QCSK modulation technique provides double benefit: higher data
rate with similar BER performance and same bandwidth occupation as DCSK. By combining
the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos
shift keying (QCSK) scheme, a novel CS-QCSK modulation scheme called code shifted
Quadrature chaos shift keying is proposed. The noise performance of CS-QCSK is better to
most conventional modulation schemes and also provides an increased data transmission rates
with greatly improved robustness. Analytical expressions for the bit-error rates are derived for
both AWGN channel and Rayleigh multipath fading channel. The simulation result shows that
the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
REDUCING THE MONITORING REGISTER FOR THE DETECTION OF ANOMALIES IN SOFTWARE D...csandit
Reducing the number of processed data, when the information flow is high, is essential in processes that require short response times, such as the detection of anomalies in data networks. This work applied the wavelet transform in the reduction of the size of the monitoring register of a software defined network. Its main contribution lies in obtaining a record that, although reduced, retains detailed information required by the detectors of anomalies.
This document summarizes a research paper that analyzes end-to-end delay distribution in wireless sensor networks. It first introduces the importance of average delay and end-to-end delay distribution for real-time quality of service in wireless sensor networks. It then discusses previous work that analyzed average delay but failed to consider single hop delay distribution or bursty traffic. The document proposes a comprehensive cross-layer analysis framework to model average delay and end-to-end delay distribution considering both deterministic and random node deployments. It also compares the performance of CSMA/CA and a cross-layer MAC protocol in terms of throughput, packet loss, and delay.
Ballpark Figure Algorithms for Data Broadcast in Wireless NetworksEditor IJCATR
In wireless system allocation is a necessary purpose and show industry expensive dependability in message protocol design. In multihop wireless networks, equally, imposition by a node by reason of immediate transmissions as its neighbors makes it nontrivial to graph a minimum-latency transmit algorithm, which is known to be NP-complete. A simple ballpark figure algorithm for the one-to-all transmit problem that improves all previously documented guarantees for this problem. In All-to-all transmit problem where every node sends its own consequence to all complementary nodes. In the all-to-all transmit problem, we current two algorithms with ballpark figure ratios of 20 and 34, civilizing the greatest result. A communication wants to be transmitted establishment its resource to all the previous nodes in the network. There may be different messages to be broadcasted from several sources. Two or more nodes broadcast a communication to an ordinary neighbor at the same time; the frequent node will not collect any of this communication. We say that collide has occurred at the ordinary node. So any message protocol for wireless networks must dispute with the distress of difficulty in the wireless intermediate.
A continuous time adc and digital signal processing system for smart dust and...eSAT Journals
This document discusses a continuous-time (CT) analog-to-digital converter (ADC) and digital signal processing system suitable for applications like smart dust and wireless sensor networks. The key benefits of the CT system are lower noise, no need for a clock generator or anti-aliasing filter.
The paper proposes a clockless, event-driven CTADC based on delta modulation. An unbuffered, area-efficient segmented resistor string digital-to-analog converter is used. This architecture achieves an 87.5% reduction in resistors, switches and flip-flops for an 8-bit converter compared to prior designs.
The CTADC uses a level-crossing sampling technique where samples are generated when
A continuous time adc and digital signal processing system for smart dust and...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A continuous time adc and digital signal processing system for smart dust and...eSAT Journals
This document discusses a continuous-time (CT) analog-to-digital converter (ADC) and digital signal processing system suitable for smart dust and wireless sensor applications. The system uses a clockless event-driven ADC based on CT delta modulation. The ADC output is digital data continuous in time known as "data tokens". The system achieves lower power consumption and area than conventional clocked systems by operating without a clock generator or anti-aliasing filter. The 8-bit ADC system achieves a signal-to-noise ratio of 55.73 dB and effective number of bits of over 9 within an input band of 220 kHz, demonstrating its suitability for smart dust applications.
The Quality of the New Generator Sequence Improvent to Spread the Color Syste...TELKOMNIKA JOURNAL
This paper shows a new technic applicable for the digital devices that are the result of the finite’s
effect precision in the chaotic dynamics used in the coupled technic and the chaotic map’s perturbation
technics used for the generation of a Pseudo-Random Number Generator (PRNGs).The use of the
pseudo- chaotic sequences coupled to the orbit perturbation method in the chaotic logistic map and the
NewPiece-Wise Linear Chaotic Map (NPWLCM). The pseudo random number generator’s originality
proposed from the perturbation of the chaotic recurrence. Furthermore the outputs of the binary sequences
with NPWLCM are reconstructed conventionally with the Bernoulli’s sequences shifts map to change the
shapes with the bitwise permetation then the results in simulation are shown in progress.After being
perturbed, the chaotic system can generate the chaotic binary sequences in uniform distribution and the
statistical properties invulnerable analysis. This generator also has many advantages in the possible useful
applications of spread spectrum digitalimages, such as sensitive secret keys, random uniform distribution
of pixels in Crypto system in secure and synchronize communication.
IRJET- A Novel Hybrid Security System for OFDM-PON using Highly Improved RC6 ...IRJET Journal
This document proposes a novel hybrid security system for OFDM-PON using a highly improved RC6 algorithm and scrambling technique. The data is first scrambled using Morlet wavelet transform for spatial domain scrambling without data loss. It is then encrypted using a highly improved RC6 algorithm for enhanced security. By combining scrambling and encryption, a two-tier security approach is implemented with low complexity. Simulation results show low bit and symbol error rates, demonstrating improved system performance. The proposed scheme provides enhanced security for OFDM-PON networks with potential applications in secure optical communications.
IRJET- Performance Analysis of a Synchronized Receiver over Noiseless and Fad...IRJET Journal
This document summarizes the performance analysis of a synchronized receiver over noiseless and fading channels. It presents a baseband communications system that implements data phase transmission using a single-tone waveform. The behavior of the received signal when transmitted over a noiseless channel and a fading frequency selective channel with additive white Gaussian noise is analyzed. Key plots analyzed include the channel output power spectrum, cross-spectral phase between the equalizer input and output, control signal for the equalizer, and scatter plots of the equalizer input, output, and descrambler output. The analysis shows distortion of the signal due to noise in the fading channel.
Lossless Data Compression Using Rice Algorithm Based On Curve Fitting TechniqueIRJET Journal
This document describes a lossless data compression technique called the Rice algorithm and a modification of the Rice algorithm using curve fitting. The Rice algorithm uses a two-stage approach of preprocessing data to decorrelate it followed by entropy coding to assign variable-length codes. The modified Rice algorithm uses curve fitting to generate a function to predict future data points for improved compression performance compared to the original Rice algorithm. Simulation results show the modified algorithm achieves better compression by selecting an encoding option that uses fewer bits than the original Rice algorithm on a sample data set.
Enchancing the Data Collection in Tree based Wireless Sensor Networksijsrd.com
Number of techniques used in Wireless Sensor Network to improve data collection from sensor nodes. It achieve by minimize the schedule length and dynamic channel assignment. Schedule length minimized by BFS algorithm without interfering links. Interfering links can be eliminated by transmission power control and multi frequency. The power can be save by using beacon signal. Collection of data can also be limited by topology of network. So the nodes are arranged in form. The capacitated minimal spanning trees and degree- constrained spanning trees give significant improvement in scheduling. Finally the data collection is enhancing in terms of security by using T-Hash Chain algorithm.
A SECURE DIGITAL SIGNATURE SCHEME WITH FAULT TOLERANCE BASED ON THE IMPROVED ...csandit
Fault tolerance and data security are two important issues in modern communication systems.
In this paper, we propose a secure and efficient digital signature scheme with fault tolerance
based on the improved RSA system. The proposed scheme for the RSA cryptosystem contains
three prime numbers and overcome several attacks possible on RSA. By using the Chinese
Reminder Theorem (CRT) the proposed scheme has a speed improvement on the RSA decryption
side and it provides high security also.
Efficient Broadcast Authentication with Highest Life Span in Wireless Sensor ...IRJET Journal
This document discusses efficient broadcast authentication to maximize the lifetime of wireless sensor networks. It proposes using a greedy heuristics algorithm with the X-TESLA broadcast authentication protocol. X-TESLA uses short key chains to authenticate broadcast messages but has limitations regarding sleep modes, network failures, idle sessions, extended lifetime, and denial-of-service attacks. The proposed approach combines X-TESLA with greedy heuristics to address these issues and significantly improve network lifetime compared to using each approach alone. It aims to find a broadcast tree that maximizes the minimum residual energy of nodes after broadcasting to prolong the ability of the network to complete future broadcasts.
Minimum distance based routing protocol for lifetime improvement in wireless ...eSAT Journals
Abstract Balanced utilization of energy of wireless sensor nodes is a challenge while designing wireless sensor network (WSN). This energy of sensor node is a limited resource and measure for the lifespan of WSN. Communication process consumes most of the energy of sensor node hence; energy of sensor node becomes a major design issue for WSN. Clustering is preferred while designing routing protocols for WSN for its many to one traffic pattern. In our minimum distance based routing protocol for lifetime improvement in WSN (MDBRP) clusters are formed once in a lifetime and their heads are selected rotationally based on minimum communication distance between nodes and their next hop. MDBRP considers minimum energy consumption which aims to increase the overall lifespan of WSN. Keywords— clustering, dynamic clustering, routing protocol, static clustering, wireless sensor network.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Limit energy is a severe bottleneck of wireless sensor networks (WSNs), and limits network lifetime of WSNs. To extend network lifetime, buffer zone has been proposed. Sensors send their data packets to buffer zone. The sensors in buffer zone buffer the data packets. And then the sink visits the buffer zone to collect the data ackets. This leads to that the loads of the sensors in buffer zone are too high and the sensors die quickly. To further extend network lifetime, an algorithm based on dynamic buffer zone has been proposed in this paper. The algorithm divides the whole network area into some areas, and lets all areas act as the buffer zone in turn. And the reasonable times each zone acts as the buffer zone are computed with linear programming. The simulation results have shown that our proposed algorithm notably extends network lifetime.
IRJET- Data Embedding using Image SteganographyIRJET Journal
This document presents a method for secure communication using both steganography and cryptography techniques. It discusses embedding encrypted text into an image using discrete wavelet transform (DWT). Specifically, it first encrypts a text message using the advanced encryption standard (AES) algorithm. It then embeds the encrypted text into an image by applying DWT to decompose the image into sub-bands and hiding the data in the high frequency sub-bands. MATLAB is used to implement a graphical user interface that allows a sender to encrypt a message, embed it into an image, and send the stego-image to a receiver. The receiver interface extracts the encrypted text from the stego-image and decrypts it using AES. The method aims to
The document proposes a Congestion Control Anonymous Gossip (CCAG) protocol to improve reliable packet delivery in multicast routing protocols for mobile ad-hoc networks (MANETs). The CCAG protocol uses a two phase approach, first using an existing multicast protocol like MAODV to disseminate messages unreliably, then using a gossip protocol in the background to reliably recover any lost messages. The gossip protocol implements anonymous gossip, locality of gossip, cached gossip, and pull-based message exchange to provide reliability while minimizing overhead. Simulation results show the CCAG protocol achieves a 22% improvement in packet delivery ratio over MAODV, while also reducing congestion and variation in packets received by nodes.
Multiple Downlink Fair Packet Scheduling Scheme in Wi-MaxEditor IJCATR
IEEE 802.16 is standardization for a broadband wireless access in network metropolitan area network (MAN). IEEE 802.16
standard (Wi-Max) defines the concrete quality of service (QoS) requirement, a scheduling scheme and efficient packet scheduling
scheme which is necessary to achieve the QoS requirement. In this paper, a novel waiting queue based on downlink bandwidth
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DSP Based Implementation of Scrambler for 56kbps Modem
1. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 85
DSP Based Implementation of Scrambler for 56Kbps Modem
Davinder Pal Sharma davinder.sharma@sta.uwi.edu
Department of Physics
University of the West Indies
St. Augustine, Tinidad & Tobago
Jasvir Singh j_singh00@rediffmail.com
Department of Electronics Technology
Guru Nanak Dev University
Amritsar -143105, India
_____________________________________________________________________________
Abstract
Scrambler is generally employed in data communication systems to add
redundancy in the transmitted data stream so that at the receiver end, timing
information can be retrieved to aid the synchronization between data terminals.
Present paper deals with simulation and implementation of the scrambler for
56Kbps voice-band modem. Scrambler for the transmitter of 56Kbps modem was
chosen as a case study. Simulation has been carried out using Simulink of
Matlab. An algorithm for the scrambling function has been developed and
implemented on Texas Instrument’s based TMS320C50PQ57 Digital Signal
Processor (DSP). Signalogic DSP software has been used to compare the
simulated and practical results.
Keywords: Scrambler, 56Kbps Modem, Matlab, Signalogic, Digital Signal Processor.
_____________________________________________________________________________
1. INTRODUCTION
Often, it is required by the user to ensure that the transmitted signal should has sufficient
randomness or activity so that timing recovery, adaptive equalization and echo cancellation can
be reliably performed. Mostly users type characters on PC relatively slow due to which computer
terminal transmits null characters most of the time. A long sequence of null characters results in a
highly correlated line signal. Such signals can foil timing recovery and other functions, all of which
assume that the transmitted symbols are uncorrelated. Scrambling is intended to minimize strong
correlations among the information bits so as to make them appear more random. It is a method
of achieving dc balance (dc null) and eliminating long sequences of zeros to ensure timing
recovery without redundant line coding. Scrambler does not add anything in signal, as it is not
based on redundancy. Scrambler performs one-to-one mapping between input data bits and
coded data bits. The objective is to map the bit sequences, which are problematic and likely to
occur, into a coded sequence that looks more random and less problematic.
Scrambler is a digital device, which maps a data sequence into a channel sequence. If the data
sequence is periodic, it converts it into a periodic channel sequence with period, which is many
times the data period. A simple scrambler adds a Maximum-Length Shift-Registers (MLSR)
sequence to the input bit stream to randomize or whiten the statistics of the data, making it more
random. Scrambler consists of linear sequential filters with feedback paths, counters, storage
2. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 86
elements and peripheral logic in their discrete form. The counters, storage elements and
peripheral logic, monitor the channel sequence but react infrequently so that the scrambler
behaves principally as linear sequential filter [1].
There are many applications of scrambler. This is used for encryption of data in security systems,
to remove non-linearity of common carrier systems which causes inter-channel interference and
to remove systematic jitter caused by self-retiming circuits in base-band Pulse Code Modulation
(PCM) systems. In data communication systems, main purpose of the scrambler is to add
redundancy in the transmitted data stream so that at the receiver, timing information can be
retrieved from received data i.e. to aid the synchronization between two modems. The present
study deals with the implementation of the scrambler used for synchronization purpose.
2. THEORETICAL BACKGROUND
In the beginning, scrambler was used to reduce the effect of jitter in the PCM systems. Jitter is a
very serious problem as it reduces the Signal-to-Noise Ratio (SNR) and causes more errors to be
introduced at the receiver. In addition, jitter also effects the functioning of the repeaters, which
has a commutative effect. The proceeding timing circuits generates systematic jitter, which
degrades the transmission quality because the r.m.s. value of the jitter increases in proportion to
the square root of the number of repeaters. A self-retiming circuit is used in conventional base-
band PCM systems to minimize the jitter in which a timing waveform is extracted from an
equalized pulse train [2]-[3].
There are certain impairments that vary with the statistics of the digital source in digital
transmission systems and these statistics of the data source is related to the problem of timing
recovery, equalization and cross talk. One of the methods to isolate the system performance from
the source statistics is to use redundant transmission codes. These codes could not provide
complete isolation however they generate additional problems by increasing the symbol rate.
Alternative method to cope up with this problem is scrambling, which whitens the statistics of
digital source. Any source is said to white if it generates statistically independent and
equiviprobable symbols using which system impairment can be easily analyzed. All the first order
and second order statistics of any binary source can be whiten to any degree at the cost of an
arbitrarily small controllable rate [4].
3. BASIC SCRAMBLING ACTION
Data transmission through any communication system will be errorless if the timing of each
device attached to the system is accurate enough. But it is difficult to ensure the accuracy of the
timing in a larger system having many devices or having very large data packets. The solution to
this problem of highly accurate clocks can be found by using synchronous communication
techniques. In synchronous systems, it is necessary to extract timing information from the
received data, which in turn reduces the burden of internal clock circuitry. There are many
methods using which timing information from the received data can be retrieved. Line coding
techniques like Return to Zero coding and Manchester coding are the few familiar techniques that
may be used for this purpose [1]. The problem with the usage of these line-coding techniques is
that the timing benefits come at the expense of bandwidth, so these techniques are not used in
Public Switched Telephone Network (PSTN), which is severely band-limited network, so one has
to choose other options. Scrambling is a technique that can be used in conjunction with simpler
line coding algorithms such as simple binary and RS232C protocol to achieve above-mentioned
goal without sacrificing the bandwidth requirement.
3. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 87
In digital system, it is common practice to encounter long strings of 1’s and 0’s within the
transmitted data that results in constant output levels. Timing information cannot be retrieved
from such outputs because there will be no state-transition during these sequences which may
result in transmission errors at the receiver. Scrambler can eliminate this problem by detecting
undesirable sequences of bits and inserting state transitions in a pseudo random manner. If
there is a long sequence of 1’s, 0’s will be pseudo randomly inserted in to the stream. It ensures
that the probability of receiving a ‘1’ is equal to the probability of receiving ‘0’ and minimizes the
probability of periodic or repetitive data transmission, which in turn make clock recovery easier
[5]. Simple scrambling action of a scrambler is shown in Fig. (1). While it may not be possible to
prevent the occurrence of all undesirable sequences with absolute certainty, at least most of the
common replications in the input data stream can be removed by the use of a scrambler. It has
been found that the transmission of short repetitive patterns could play havoc with both the
equalizer and timing recovery systems [2].
4. SYSTEM DESIGN
There are many ways to implement scrambler but all rely on the same basic building blocks of
linear feedback shift registers and modulo-2-addition functions. Many researchers have
discussed the general theory of implementation of scramblers [2-4], [6-7]. In general, the serial
data enters in linear feedback shift register, where each stage in the register delays the signal by
one time unit as shown in Fig. (2). The delayed version of the output signal is then fed back and
modulo-2-addition is performed with the input signal. The scrambler's input and output relation, in
general, is given by [1]-[2] :
(1)
D D D
hm
y (n-2) y (n-m)
h2
h1 hm-1
y (n-1)
y (n)
x (n)
FIGURE 2: Basic Structure of a Scrambler
1 0 1 0 1 0 1 0 0 0 0 0 1 1
SCRAMBLER
FIGURE 1: Scrambling Action
Unscrambled data
stream having
long string of 0s
Scrambled output in
which long string of
0s has been
removed
1 0 1 1 1 0 0 0 1 1 0 1 0 0
∑
=
−+=
m
k
knyhnxny k
1
)()()(
4. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 88
Where y(n) is current output, y (n-k) is the output delayed by k times, x(n) is current input and hk
is system transform function. All the constants and variable in eqn. (1) can only have the values
‘0’ or ‘1’ and all additions performed are modulo-2-additions (exclusive-OR operations).
Corresponding state vector s(n) to this eqn. can be written as
(2)
In general scrambler is of two types; Frame synchronized scrambler and self-synchronized
scrambler. Frame-synchronized scrambler is used for cryptography purposes whereas self-
synchronized scrambler is used for clock or carrier recovery purpose and it is this scrambler,
which is used in modem design.
Both scramblers are based upon maximum-length shift-register sequence or M-sequences, which
are periodic bit sequences with properties that make them appear to be random. These
sequences can be generated using a feedback shift register, which is basically a linear sequential
filter with feedback paths. Binary m-stage linear feedback shift register is shown in Fig. (3) [8].
Binary sequence of this maximum length is known as M-sequence or pseudo-random binary
sequence because it satisfies several statistical tests for randomness. The auto-correlation
function of such sequences resembles with the white noise. While implementing such device, the
design problem is to select the shift register taps, which generate a M-sequence. The theory
behind it is based on finite fields so it involves algebraic polynomials and finite field arithmetic
(modulo-2-addition). Polynomials, which generate ‘M’ sequences, should be primitive. A
polynomial y(x) of degree ‘m’ is primitive if it is irreducible i.e. has no factors except 1 and itself
and if it divides x
k
+1 for k = 2
m
-1 and does not divide x
k
+1 for k< 2
m
-1. Sequence period of such
primitive polynomials is 2
m
-1. Characteristic polynomial for M sequence generator is given by
[2, 9]:
(3)
Let x(n) be the binary sequence at the input of scrambler. Taking D-transform (Huffman
transform; like z-transform with D = z
-1
) of the incoming sequence as
(4)
)](),...,2(),1([)( mnynynyns −−−=
)](),...,(),([ 21 nmsnsns=
∑
∞
=
=
0
)()(
n
nDnxDX
∑
=
+=
m
k
xhy kk
1
1
xk-1 xk-2 xk-3 xk-m+1 xk-m
h1 h2 h3 hm-1 hm
FIGURE 3: Binary m-stage Feedback Shift Register
5. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 89
Then the connecting polynomial for the scrambler given in Fig. (2) can be written as
(5)
Output transform with zero initial state is given by
(6)
Taking D-transform on both sides of the above equation, we have:
(7)
The output of the scrambler is therefore given by
(8)
So mathematical operation performed by the scrambler is basically equivalent to dividing the
input information sequence by a Generating Polynomial (GP). The polynomial resulting in the
fewest feedback connection is often the most attractive for scrambling purpose. Scrambling
action of a simple five-tap scrambler specified by the generating polynomial
(9)
is shown in Fig. (4).
There are many types of characteristic polynomials that can be used in modems. Some of the
popular generating polynomials are those which have been used in the CCITT V.22 and CCITT
V.27 protocols. The V.22 polynomial is the one in which seventeen-stage operation is
recommended [6]. The CCITT V.27 protocol suggests a seven-stage register. Finally, the CCITT
V.29 recommends the 23-stage register to implement generating polynomial. Everyone has his
own preference regarding which polynomial to use but all rely on the same basic cells; shift
registers and modulo-2-adders.
∑
=
+=
m
k
kDkhDh
1
1)(
)(/)()( DhDXDY =
)()()( DXDhDY =
)(
1
)()( . nx
m
k
knyhny k =∑
=
−+
531)( −+−+= xxxy
FIGURE 4: Input and Output Waveforms of a Five-tap Scrambler
Input
Output
1 0 1 0 1 0 1 0 0 0 0 0 1 1
1 0 1 1 1 0 0 0 1 1 0 1 0 0
6. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 90
5. SCRAMBLER IN 56KBPS MODEM
56Kbps modem uses PCM in the downstream (server to client). Clock recovery circuit of the
modem generally uses high-Q resonant tank circuit, which averages the clock phase over several
bit periods. Clock phase resulting from sampling a constant signal level will attain a static value
and if this bit pattern changes to another pattern, the implementation of clock recovery circuit will
force the clock phase to change and attain a new value. The serial PCM bit stream reflects the
deterministic parts of the signal and this leads to clock phase jitter in the repeater. Its r.m.s. value
increases linearly as square root of the number of cascaded repeaters. Since a clock phase
change is equivalent to timing jitter, the data eye will not always be sampled at the optimum time
and so there will be an increase in bit error probability. Scrambling is one of the effective methods
for the suppression of this jitter [10-11].
The data scrambler specified for the transmitter of 56Kbps digital modem is designed using the
following generating polynomial [12]:
(10)
This is a self-synchronizing scrambler, which means that it will not only provide clocking
information throughout the transmission but also will be used to create the signals for the initial
handshaking between the modems on the receiving and transmitting end. If there is an error free
transmission then one can use the same generating polynomial with the feed-forward shift-
register device for de-scrambling but if there is any error then one have to use different
polynomial. Block diagram of 56Kbps digital modem’s scrambler is given in Fig. (5).
6. SIMULATION OF SCRAMBLER USING MATLAB
Matlab has been used to study the scrambling action in the transmitter of 56Kbps digital modem
which uses generating polynomial given by eqn. (10). Using Simulink toolbox of Matlab, a model
of scrambler as shown in Fig. (6), corresponding to the eqn. (10) has been developed and its
performance against input binary sequences with different probabilities of occurrence of 0’s (P)
has been evaluated. Model contains a Bernoulli Random Binary Generator (BRBG) block, which
generates random number using Bernoulli distribution [13].
The Bernoulli distribution produces zeros with the probability P and ones with the probability 1-P.
The Bernoulli distribution has mean value 1-P and variance P (1-P) [14]. The scrambler block
scrambles the input signal (the output of BRBG) using scramble polynomial parameter ρ, which
23181)( −+−+= xxxy
FIGURE 5: Scrambler for 56Kbps Digital Modem
Output
Input
D1 D2 D18 D19 D23
7. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 91
defines the feedback connections in the scrambler i.e. feedback connection from 1
st
, 3
rd
and 5
th
delay elements can be represented as ρ = [0,-3,-5] or as ρ = [1 0 0 1 0 1].
Simulation results corresponding to different values of P in time domain were obtained and from
these results, the number of transitions in input data (Ti/p) and in output data (To/p) have been
calculated. The ratio of To/p to the Ti/p gives the Randomization Parameter R which can be
considered as a measure of performance of the scrambler, R therefore describes how effectively
scrambler randomizes the incoming binary signal. Fig. (7) gives the graphical representation of
the results obtained and hence it can be concluded that scrambling action of the scrambler is
more effective for the input data sequences having high value of probability of occurrence of
zeros or ones i.e. the signal having long sequences of 0s or 1s. Scrambler is less effective for the
input data sequences having frequent transitions and more over no scrambling is needed for such
inputs because these sequences have sufficient number of transitions in it, using which clock
information can easily be retrieved.
7. IMPLEMENTATION OF SCRAMBLER ON DSP CHIP
Scrambler for 56Kbps server (digital) modem has been implemented on TMS320C50PQ57 DSP
chip using MICRO-50EB evaluation module. Experimental setup used for the present
implementation is shown in Fig. (8). Evaluation module contains a 16 bit fixed point processor
TMS320C50PQ57 along with 48-Kiloword (KW) of monitor EPROM, 16KW of program RAM, 32
KW of data RAM & 32KW of I/O RAM. The highly paralleled architecture and efficient instruction
set provide speed and flexibility which make the TMS320C50PQ57 DSP to capable of executing
about 57 Million Instructions Per Second (MIPS). TMS320C50PQ57 DSP optimizes speed by
FIGURE 7: Variation of Randomization Parameter (R) With the Probability of Occurrence of
(P) For Scrambler With GP Given in Eqn. (10).
0
0.5
1
1.5
2
2.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
RendomizationParameter(R)
Probability of occurrence of Zeros (P)
Bernoulli Random
Binary Generator Scrambler
Scope
FIGURE 6: Matlab Model to Study the Relation between P and R in a Scrambler
8. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 92
implementing functions in hardware that other processors implement through micro-code or
software. This hardware intensive approach provides high processing power previously
unavailable on single chip. Its powerful instruction set, inherent flexibility, high-speed number-
crunching capabilities, and innovative architecture have made this high-performance, cost
effective processor; the ideal solution to many telecommunications, commercial, industrial and
military applications [15].
7.1. Algorithm for Soft Implementation of the Scrambler
Scrambler has been implemented using the circular buffers of the TMS320C50PQ57 DSP chip.
The chip has special memory mapped registers and associated circuitry for two circular buffers.
One of the eight auxiliary registers can be used as a pointer into the circular buffer. Circular buffer
was implemented on the DSP on-chip memory block. Two memory-mapped registers are
associated with each circular buffer that needs to be initialized with the start and end address.
Block diagram of I/P sample circular buffer is given in Fig. (9), where x(n) is the input data at a
time n, x(n-1) is input data delayed by single time unit and N is length of linear feedback or feed
forward shift register. Initialized circular buffer can be used for producing delay and data can be
read from any position pointed by the auxiliary register AR-1. Then XOR operation can be
performed on delayed samples to achieve scrambling action. Before the initialization of circular
buffer we have to initialize the DSP chip and I/O devices [9].
MICRO50EB
DSP
Module
Personal
Computer
FIGURE 8: Experimental Setup for Soft Implementation of Scrambler of 56Kbps Digital
Modem on DSP
Matlab
Signalogic
DSP
Software
FIGURE 9: Structure of Circular Buffer
x (n-1)
x (n)
x (n-N+1)
9. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 93
In present implementation TLC32044 AIC (Analog Interface Circuit) has been used as I/O device.
The supporting algorithm for the initialization of DSP module and algorithm for implementation of
scrambler of digital modem is given in Appendix (A) along with the algorithm of main scrambling
routine using circular buffer.
Assembly level program (source code) for the scrambler of 56Kbps digital modem has been
written using algorithm given in Appendix (A). Source code were loaded into the DSP and output
data obtained was stored at appropriate data memory location with the slight modification in the
program i.e. one more step of data storage in addition with the data transmission has been
included in the main program. Stored data was loaded into the Signalogic DSP Software for time
and frequency domain analysis of practically obtained results. In the similar fashion output data
obtained from the simulation was loaded in to the software package and simulated and practical
results were compared in time as well as frequency domain.
Time domain comparison of scrambler's simulated and practical result is shown in Fig. (10). It can
easily be concluded from this figure that the present practical result differs very slightly from the
simulated results. The transition which was occurring at 3.375ms in the simulation study has been
get shifted to 3.875 in actual practice but this shift does not disturb the scrambling action because
total number of transitions are same. Similar study in frequency domain has been carried out for
simulated and practical results. Spectral analysis i.e. variation of magnitude with frequency of
simulated and practical results is presented in Fig. (11). It is clear from this figure that the
practical and simulated results are almost same, which confirms the successful implementation of
scrambler on DSP.
Present implementation is more efficient than the earlier implementation reported by Steven
A.Ttretter, C.J.Buechler and H. Sampath [16]. In the present implementation circular buffer is
being used to produce delay and on chip memory of the DSP chip is being used due to which
memory requirement as well as execution time have been reduced by using efficient algorithm
discussed earlier. Comparison of various implementation parameters like program execution
time, program and data memory used for the current and previous study is given in the Table (1).
TABLE 1: Various Implementation Parameters
8. CONCLUSION
Scrambler for 56Kbps digital modem has been simulated using Matlab and implemented using
TMS320C50PQ57 DSP chip during the present study. From the simulation it has been found that
scrambling action of proposed scrambler is more effective for the input data sequences having
high value of probability of occurrence of zeros or ones i.e. the signal having long sequences of
0s or 1s. Scrambler is less effective for the input data sequences having frequent transitions and
more over no scrambling is needed for such inputs because it has sufficient number of transitions
in it, from which, clock information can easily be retrieved. In present implementation circular
buffer is being used to produce delay and on-chip memory of the DSP chip is used due to which
program memory requirement as well as execution time has been get reduced using the efficient
algorithm as compared to previous study. Simulated and practical results have been compared
Implementation
Program
Execution Time
(µsec)
Program Memory Used
(W)
Data Memory Used
(W)
Present 3.2 64 23
Previous 5 100 15
10. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 94
FIGURE 11: Comparison of Simulated and Practical Results of Scrambler in Frequency Domain
FIGURE 10: Comparison of Simulated and Practical Results of Scrambler in Time Domain
11. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 95
using Signalogic DSP Software in time as well as frequency domain and have been found same
which confirms the successful implementation of scrambler on DSP.
ACKNOWLEDGEMENTS
One of the authors Davinder Pal Sharma is thankful to Guru Nanak Dev University, Amritsar, for
providing DSP Research facilities at Department of Electronics Technology for present research
work.
9. REFERENCES
1. J. G. Proakis, M. Salehi. “Digital Communications”, McGraw Hill, (2007).
2. R. D. Gitlin, J. F. Hayes. “Timing recovery and scramblers in data transmission”, Bell System
Technical Journal 54(3): 569 – 593, 1975.
3. H. Kasai, S. Senmoto and M. Matsushita, “PCM jitter suppression by scrambling”, IEEE
Trans. on Communications, 22(8): 1114-1122, 1974.
4. A. Huzii, S. Kondo. “On the timing information disappearance of digital transmission
systems”, IEEE Trans. on Communications, 21(4):1072-1074, 1973.
5. R.L. Freeman. “Practical Data Communications”, John Wiley and Sons Inc., (1995).
6. C. H. Lin et.al. “Parallel scrambler for high speed applications”, IEEE Trans. on Circuit &
Systems-II, 53(7): 558-562, 2006.
7. M. Cluzeau. “Reconstruction of a linear scrambler”, IEEE Trans. on Computers, 56(9):
1283-1291, 2007.
8. “Data Scrambler / Descrambler with Look Ahead”, IBM Technical Disclosure Bulletin, 28:
1063-1064, 1985.
9. S. A. Tretter. “Communication System Design Using DSP Algorithms: With Laboratory
Experiments for the TMS320C6713 DSK”, Springer, 163-171 (2008).
10. ITU-T Recommendation V.92. “Enhancement to Recommendation V.90”, International Tele
communication Union, 2000.
11. D. Y. Kim et. al. “V.92: The last dial-up modem”, IEEE Trans. On Communications, 52(1):
54-61, 2004.
12. ITU-T Recommendation V.90. “A digital and analog modem pair for use on the PSTN at data
signaling rates of up to 56000 bits/s downstream and 33600 bits/s upstream”, International
Tele communication Union, 1998.
13. “Simulink User Guide”, The Mathworks Inc. (2009), http://www.mathworks.com.
12. Davinder Pal Sharma & Jasvir Singh
Signal Processing – An International Journal (SPIJ), Volume (4) : Issue (2) 96
14. G. Zimmermann. “Probabilities of long sequences of identical bits after data scrambling”. In
Proceeding of IEEE International Conference on Communications, 1990, 1521-1525.
15. "Micro-50 EB user manual", DSP Series, Vi Microsystems Pvt. Ltd., (2000).
16. S. A. Tretter et. al. " V.34 Transmitter and receiver implementation on the TMS320C50
DSP", Digital Signal Processing Solutions, Texas Instruments, USA, 1997.
APPENDIX (A)
Start
Select I/O device by
setting appropriate bits
Initialize I/O device
Enable RINT interrupt
IDLE
Initialize the RINT & XINT
vectors
B
RINT ISR
Algorithm for
initialization of DSP
Module
Get data from I/O and
store it at 100H
Load the address of last
data in the window
100H + (N-1)H
Clear Acc. and
P-register
Do Scrambling (C)
Transmit the resultant
data to AIC
IDLE
B
Algorithm for initialization
of scrambling function of
56Kbps digital modem.
Initialize the Circular Buffer
Move the data using
RPT/DMOV
Repeat (N-1) time
Set ARP for digital modem
scrambler
1st
=100H, 2nd
= 112H. 3rd
= 117H
Load data from DRR to start
address of Circular Buffer
Scrambled data
XOR the ACC. with the data
pointed by ARP
Main scrambling routine
C