Vinoth Raj R teaches a course on digital logic design using Verilog HDL at Velammal Institute of Technology. The course covers various topics related to Verilog including data types, operators, levels of abstraction for modeling circuits, gate-level modeling using primitives, user-defined primitives, data flow modeling, behavioral modeling, and file handling. The emphasis is on modeling, verifying, and synthesizing digital circuits specified in Verilog.

1. Vinoth Raj R
Assistant Professor
Electronics & Communication Engineering
Velammal Institute of Technology
Digital Logic Design using
Verilog HDL

2. Course Outline
• Introduction
• Types of HDL
• Verilog data types
• Operators
• Levels of abstraction
• Gate level or Structural modeling
• User Defined Primitives
• Data flow modeling
• Behavioral modeling
• File Handling
• Discussion
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3. Introduction
• A hardware description language (HDL) is a computer-based language that
describes the hardware of digital systems in a textual form
• Similar to computer programming language, such as C, but is specifically
oriented to describing hardware structures and the behavior of logic circuits
• It can be used to represent logic diagrams, truth tables, Boolean
expressions, and complex abstractions of the behavior of a digital system
• It describes a relationship between signals that are the inputs to a circuit
and the signals that are the outputs of the circuit
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4. Types of HDL
• Verilog
• VHDL (VHSIC)
• System Verilog
• System C
• Bluespec System Verilog
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Widely used

5. Verilog Vs. VHDL
Verilog VHDL
Case sensitive Case insensitive
Not a strongly typed Strongly typed
Similar to C language Similar to ADA language
Up to transistor level simulation is possible Only up to gate level simulation
IEEE 1364 standard (Synopys) IEEE 1164 (Department of Defence)
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6. Contd...
• Our emphasis will be on the modeling, verification, and
synthesis (both manual and automated) of Verilog models of
circuits having specified behavior
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7. Operators
Bitwise
& and
| or
~ not
&~ nand
&| nor
^ ex-or
~^ ex-nor
Arithmetic
+ addition
- subratction
* multiplication
/ division
% modulus
Logical
&& and
|| or
! not
Relational
== Equality
!= Inequality
>= Greater than or
equal
<= Less than or equal
=== Case equality
!== Case inequality
others
{} concatenate
?: conditional
shift
>> shift right
<< shift left
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8. Value set
Value Definition
0 logic zero or false
1 logic one or true
x unknown logic value
z High impedance
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During the initialization /
simulation: All unconnected nets
are set to ‘Z’ & All register
variables are set to ‘X’.
wire x, y, z; // single bit
wire [7:0] sum; // 7 – MSB, 0 - LSB
reg [31:0] MDR; // 31 – MSB, 0 - LSB
reg [1:10] data; // 1 – MSB, 10 - LSB
wire clock; // single bit with sequence
reg [31:0] IR;
reg [5:0] opcode;
reg [4:0] reg1, reg2, reg3;
reg [10:0] offset;
opcode = IR[31:26];
offset = IR[10:0];
reg1 = IR[25:21]; reg2 = IR[20:16];
reg3 = IR[15:11];

9. Data Types
1. Nets
• The variables represent the physical connection between structural entities.
• These variables do not store variables
• Value changes is continuously driving to the circuit
2. Registers
• It is used in procedural blocks which stores values from one assignment to
next
• Assignment statement in a procedure act as a trigger that changes the value
of the data storage element
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10. Nets
1. wire
2. tri
3. wor
4. wand
5. supply0
6. supply1
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11. Register Data Type
• In Verilog - Register is a variable that can holds a value
• unlike a “net” that is continuously driven and cannot hold any value
• Combinational circuit can also use register type variables
• register data types
a) reg :most widely used
b) integer :used for loop counting
c) real :used to store floating point numbers
d) time :keeps track of simulation time(not synthesizable)
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12. Levels of Abstraction
Behavioral Structural
Physical
Programs
Specifications
Truth Table
Gates
Adders
Registers
Transistors/Layout
Cells
Chips/boards
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13. Structural or Gate Level Modeling
• When we design a Verilog code entirely using Primitive Logic Gates, it is
called “Gate Level Modelling“. This is Lowest level abstraction
• Likewise in Structural modelling, we model a circuit by using Primitive
gates, and predefined modules
• Inbuilt primitives
• and, or, not, nand, nor, xor, xnor
• cmos,pmos,nmos,supply0,supply1
Synthesizable
Non synthesizable
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14. Module Instantiation
module
myexor(a,b,s);
input a,b;
output s;
xor (s,a,b);
endmodule
module
myand(a,b,c);
input a,b;
output y;
and (c,a,b);
endmodule
module ha(a,b,s,c);
input a,b;
output y;
myxor g1(s,a,b);
myand g2(c,a,b);
endmodule
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15. User Defined Primitives (UDP)
• The user can create additional primitives by defining them in tabular
form
• One way of specifying a digital circuit in tabular form is by means of
a truth table
• UDP descriptions do not use the keyword pair module . . .
endmodule
• Instead, they are declared with the keyword pair primitive . . .
endprimitive
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16. Examples
primitive udp_or(a,b,c);
input a,b;
output c;
table
//a b :c;
? 1 : 1;
1 ? :1;
0 0 : 0;
endtable
endprimitive
module myor_gate(a,b,c);
input a,b;
output c;
udp_or g1(a,b,c);
endmodule
primitive sum(s,a,b);
input a,b;
output s;
table
//a b :s;
0 0 : 0;
0 1 : 1;
1 0 : 1;
1 1 : 0;
endtable
endprimitive
primitive carry(c,a,b);
input a,b;
output c;
table
//a b :c;
0 0 : 0;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable
endprimitive
module ha_udp(s,c,a,b);
input a,b;
output s,c;
sum t1(s,a,b);
carry t2(c,a,b);
endmodule
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17. Data Flow Modeling
It is completely done by the logical expression of the digital circuit
• We have arithmetic and logical operators in verilog which we can
use to create a logic expressions of the circuit
• This is medium level abstraction this type of modelling along with
structural modelling in highly recommended in ASIC design
continous assignment
• values are continously assigned to nets
• keyword assign
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18. Examples
module myand(a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule
module ha(a,b,s,c);
input a,b;
output s,c;
assign c = a ^ b;
assign s = a & b;
endmodule
module
mux_2_1(y,s,a,b);
input a,b,s;
output y;
assign y=(~s)&(a)|(s&b);
endmodule
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19. Behavioral Modeling
• It completely depends on the truth table or behaviour of the circuit
• In this modelling we can design without even knowing the
components present in it
• If we know the behaviour of the circuit, we can design it
• This is the highest level abstraction
• This modelling is recommended for FPGA prototyping and other
Reconfigurable devices
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20. always block
• always @( )
begin
...elements...
end
always @(posedge clk)
always @(negedge clk)
always @(posedge clk or negedge rst)
always @(*)
Sensitivity list
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21. Procedural Statements
Blocking statements
•It must be executed before the execution of the statements that followed in a sequential block
ex
a=b;
b=c;
Non blocking statements
•It allow you to schedule assignments without blocking the procedural flow
•whenever you want to make several register assignments within the same time step without
regard to order or dependence upon each other
ex
b<=a;
c<=b;
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22. Conditional Statements
• It is used to make a decision on whether the statement within
the if block should be executed or not
• If there is an else statement and expression is false then
statements within else block will be executed
1. if without else
2. if with else
3. if else if
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23. Examples
module
up_counter(clk,rst,count);
input clk,rst;
output reg[31:0]count;
always@(posedge clk or
negedge rst)
begin
if(!rst)
count =32'b0;
else
count=count+1;
end
endmodule
module mux_2_1(a,b,sel,out);
input a,b, sel;
output reg out;
always@(a or b or sel)
begin
if(sel == 1)
out = a;
else
out = b;
end
endmodule
module d_ff(clk,rst,q,d);
input clk,rst,q;
output reg q;
always@(posedge clk or negedge
rst)
begin
if(rst == 0)
q<=1'b0;
else
q<=d;
end
endmodule
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24. Case Statement
The case statement is a decision instruction that chooses one statement for
execution. The statement chosen is one with a value that matches that of the case
statement
Syntax
case (expression)
expression : statement
expression {, expression} : statement
default : statement
endcase
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25. Examples
module
mux_4_1(i0,i1,i2,i3,sel,y);
input i0,i1,i2,i3;
input [1:0]sel;
output reg y;
always@(i0 or i1 or i2 or i3 or
sel)
begin
case(sel)
2'b00 : y=i0;
2'b01 : y=i1;
2'b10 : y=i2;
2'b11 : y=i3;
endcase
end
endmodule
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26. Looping Statement
forever loop
The forever loop executes continually, the loop never ends. Normally we use forever statements in initial blocks
syntax forever < statement >
while loop
The while loop executes as long as an < expression > evaluates as true. This is the same as in any other programming language
syntax : while (< expression >) < statement >
for loop
The for loop is the same as the for loop used in any other programming language
Executes an < initial assignment > once at the start of the loop
Executes the loop as long as an < expression > evaluates as true
Executes a < step assignment > at the end of each pass through the loop
syntax:
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27. module forever_example ();
reg clk;
initial begin
#1 clk = 0;
forever begin
#5 clk = ! clk;
end
end
initial begin
$monitor ("Time = %d clk = %b",$time, clk);
#100 $finish;
end
endmodule
module while_example();
reg [5:0] loc;
reg [7:0] data;
always @ (data or loc)
begin
loc = 0;
// If Data is 0, then loc is 32 (invalid value)
if (data == 0) begin
loc = 32;
end else begin
while (data[0] == 0) begin
loc = loc + 1;
data = data >> 1;
end
end
$display ("DATA = %b LOCATION = %d",data,loc);
end
initial begin
#1 data = 8'b11;
#1 data = 8'b100;
#1 data = 8'b1000;
#1 data = 8'b1000_0000;
#1 data = 8'b0;
#1 $finish;
end
endmodule
module for_example();
integer i;
reg [7:0] ram [0:255];
initial begin
for (i = 0; i < 256; i = i + 1) begin
#1 $display(" Address = %g Data = %h",i,ram[i]);
ram[i] <= 0; // Initialize the RAM with 0
#1 $display(" Address = %g Data = %h",i,ram[i]);
end
#1 $finish;
end
endmodule
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28. File Handling
• $fopen(file_name);
• $fdisplay(arguments);
• $fmonitor(arguments);
• $fclose(file_name);
• $fwrite(arguments);
• $freadmemb(“file”,memory_identifier[,begin_address[,end_address]]);
• $readmemh(“file”,memory_identifier[,begin_address[,end_address]]);
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29. integer file;
reg a,b,c;
initial
begin
file =$fopen(“results.dat”);
a=b&c;
$fdisplay(file,”Result is:%b”,a);
$fclose(file);
end
reg[3:0]memory[15:0];
initial
begin
$readmemb(“data.bin”,memory);
end
reg[3:0]memory[15:0];
initial
begin
$readmemh(“data.hex”,memory,4,2);
end
loading data in hexadecimal format from file
data.hex into memory starting address 4 and
down to 2
loading data in binary format from the file
data.bin into memory
Result of operation a = b & c will be
put into the file result.dat
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30. References
• NPTEL lecture on “Hardware modelling using verilog” by Prof
Indranil sen gupta, professor, department of CSE ,IIT
Kharagpur.
• “Digital design with an introduction to verilog HDL”, fifth
edition M.Morris Mano and Micheal d Ciletti.
• www.asic-world.com
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