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![Chip Debug
Why Functional Correctness is Easier to Assess from the RTL
RTL DEBUG
D[7:0] Gate level debuggers
SEL have limited design
C[7:0] 0 0
Z[7:0]
visibility, making bugs
B[7:0] 1 + 1
harder to find.
A[7:0]
• Enumerated TYPES in your RTL appear as 1’s and
0’s in the netlist
Synthesis • Inferred RAM, DSPs and other synthesis
optimizations cause debug nodes of interest to be
absorbed or transformed - they can no longer be
probed Netlist
now includes
GATE LEVEL DEBUG names and structures
SEL that differ greatly from
D[7:0] 0
A[7:0] Z[7:0] the functional RTL
C[7:0] + 1
B[7:0] description
output no longer gated by SEL signal
© Synopsys 2011 10](https://image.slidesharecdn.com/synopsysjul1411-110719065458-phpapp01/85/Synopsys-jul1411-10-320.jpg)
![Reproducible, Documented Design Process
Custom Reporting and Analysis using Tcl/Find … An Example
1. Define a Tcl / Find script analysis_example.tcl
open_design implementation_a/top.srm
set find_DSP48Es [find -hier –inst {*} -filter @view == {DSP48E*}]
set find_negslack [find -hier –seq –inst {*} -filter @slack < {-0.0}]
c_print $find_DSP48Es -file DSP48Es.txt
c_print -prop slack -prop view $find_negslack -file negslack.txt
2. Run the script from the command line
synplify_pro –batch analysis_example.tcl
DSP48Es.txt negslack.txt
{i:CPU_A_SOC.CPU.MULT.ABH_4[34:0]} Object Name slack view
{i:CPU_A_SOC.CPU.MULT.ABH_7[47:0]} {i:CPU_A_SOC.CPU.DATAPATH.GBR[0]} -3.264 "FDE"
{i:CPU_B_SOC.CPU.MULT.ABH_0[34:0]} {i:CPU_A_SOC.CPU.DATAPATH.GBR[1]} -3.158 "FDE"
{i:CPU_B_SOC.CPU.MULT.ABH_3[47:0]} {i:CPU_A_SOC.CPU.DATAPATH.GBR[2]} -3.091 "FDE"
Inferred DSP48E instances Paths with negative slack
© Synopsys 2011 19](https://image.slidesharecdn.com/synopsysjul1411-110719065458-phpapp01/85/Synopsys-jul1411-19-320.jpg)
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Synopsys jul1411
This document discusses key concerns and methods for designing high-reliability FPGA-based systems. It covers ensuring accurate design specifications, implementing built-in safety features like triple modular redundancy and safe finite state machines, evaluating and debugging designs at the register-transfer level using FPGA prototypes, and following reproducible, documented design processes. The goal is to address safety-critical applications' needs for mitigating radiation effects, requirements tracing, power reduction, and verification.
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Synopsys jul1411
- 1. Faster, Safer Implementationof High-Reliability, High-Availability Designs using FPGAs Angela Sutton Staff Product Marketing Manager Synopsys July 2011 © Synopsys 2011 1
- 2. Top Concerns forHigh-Rel Applications • Safety-critical design – SEU mitigation – Safe FSM Consumer • Requirements tracking Industrial Wireless • Power reduction Medical/ Computing/Storage • Verification & debug Instrumentation Military & Aerospace • Ease of use Wired Comms Wired Comms. Medical/Instruments Mil/Aero Automotive Broadcast Other Source: Channel Media & Market Research, August 2010 © Synopsys 2011 2
- 3. Agenda Design Reliability involves many things including Complete and Accurate Design Specification Constraints and syntax checking Design specification checking Built in Safety Triple Modular Redundancy (TMR) Safe Finite State Machines (Safe FSMs) Power Reduction Evaluate / Debug Correct Chip Operation Implement and preserve debug logic during synthesis Debug chip at the RTL Level in Hardware Debug and Develop Proof of Concept using Prototyping Hardware Reproducible, Documented Design Process Documentation, Archiving and Restoration DO-254 and Process Compliance Verification and Equivalence Checks Disabling optimizations that obstruct requirements tracing RTL debug in operating hardware © Synopsys 2011 3
- 4. Complete and AccurateDesign Specification Clock Domain Synchronization Assurance Find combinatorial paths that cross clock domains without synchronization Clock1 Clock2 State State element element Logic Path Clock1 and Clock2 controlled by clocks in different clock domains i.e. in different clock groups © Synopsys 2011 4
- 5. Complete and AccurateDesign Specification Check constraints syntax, including TCL/Find constraints Synplify constraints checker © Synopsys 2011 5
- 6. Built-in Safety SEUMitigation with Triple Modular Redundancy • TMR helps mitigate SEUs induced by radiation effects • Insert redundancy during IMPL1 synthesis with triplicated circuitry + voting logic Voting IMPL2 Output • Configure the type of TMR to Logic be used (register, block etc.) • And/or create custom TMR IMPL3 architectures and invoke settings that ensure redundant circuitry is not optimized away © Synopsys 2011 6
- 7. Built-in Safety AutomaticLocal TMR – an example SDC define_global_attribute {syn_radhardlevel} {tmr} RTL (Verilog) /*synthesis syn_radhardlevel="tmr"*/ RTL (VHDL) attribute syn_radhardlevel of behave : architecture is "tmr"; Majority voting logic Triplicated Register © Synopsys 2011 7
- 8. Built-in Safety ImplementingSafe FSMs syn_state_machine Hamming-3 syn_encoding TMR / syn_radhardlevel Output Output Function Register Output Logic syn_keep, State Error syn_preserve, Next Register Detection Input syn_hier, State syn_noprune Logic Reset / Error Mitigation syn_probe Deadlock/Time-out Counter © Synopsys 2011 8
- 9. Power Reduction •Automatic generation of switching activity – Replaces simulator-generated VCD or SAIF – No testbench/vectors or simulation required Synplify Premier – Produces defacto standard SAIF format – Created during logic synthesis Logic Synthesis • Use for early (pre P&R) power estimates Generate Switching – Xilinx XPower tool Activity Data – Other SAIF-based analysis tools • Use for power optimizations Activity Data Netlist + – SAIF drives power optimization in P&R (SAIF) Constraints • Less area also results in lower power ISE P&R with power optimization © Synopsys 2011 9
- 10. Chip Debug Why FunctionalCorrectness is Easier to Assess from the RTL RTL DEBUG D[7:0] Gate level debuggers SEL have limited design C[7:0] 0 0 Z[7:0] visibility, making bugs B[7:0] 1 + 1 harder to find. A[7:0] • Enumerated TYPES in your RTL appear as 1’s and 0’s in the netlist Synthesis • Inferred RAM, DSPs and other synthesis optimizations cause debug nodes of interest to be absorbed or transformed - they can no longer be probed Netlist now includes GATE LEVEL DEBUG names and structures SEL that differ greatly from D[7:0] 0 A[7:0] Z[7:0] the functional RTL C[7:0] + 1 B[7:0] description output no longer gated by SEL signal © Synopsys 2011 10
- 11. Chip Debug Debugand Validate Chip on the Board at the RTL level Using Identify® RTL Debugger Identify Instrumentor Identify Debugger IICE Controller 1 5 a1 b1 2 1 5 a2 Multiplexer a1 b1 3 2 a3 a2 S1 D 3 a3 S2 1 5 a1 b1 2 a2 C ENB 3 a3 IICE Special IICE Controller Set trigger conditions, inserted in design during Create debug logic capture and display synthesis operating data © Synopsys 2011 11
- 12. Chip Debug ValidateFPGA on the Board at the RTL level • RTL Instrumentation Identify – Complex triggering (e.g. FSM) – Control of data sampled – Highly customizable sampling • RTL debugging – FPGA data buffered on chip – Support multiple clocks and cross-triggering between clocks Data “sample” values from – VCD created that can be FPGA annotated on top of RTL displayed superimposed on or in waveform viewer Synplify RTL schematic or in waveform viewer © Synopsys 2011 12
- 13. Chip Debug DuringSynthesis HTML-based Synthesis Reporting © Synopsys 2011 13
- 14. Chip Debug duringSynthesis Error and Warning Messaging in HTML Message Viewer View warning messages in Synplify TCL window Apply warning filter to custom filter messages for easier analysis © Synopsys 2011 14
- 15. Chip Debug andEarly Proof of Concept Using HAPS-6X Series Prototyping Hardware HDL Files HDL Files (VHDL, Verilog, SystemVerilog, EDIF) (VHDL, Verilog, SystemVerilog, EDIF) Synplify Premier Certify / Identify HAPS-600/CHIPit Manager HAPS-64 HAPS-606, 609 ,612, 615, 618 up to 18 M ASIC Gates scalable from 27.5 M up to 81 M ASIC Gates HAPS-61 HAPS-62 up to 4.5 M ASIC Gates up to 9 M ASIC Gates Synplify Premier HAPS-600/CHIPit Manager + Synplify – For single FPGA solution Premier Certify / Identify – High level of automation – For multi-FPGA solution & debug © Synopsys 2011 15
- 16. Chip Debug andEarly Proof of Concept Using HAPS-60 PCB Technology Faster Silicon • Length-matched traces • V6 technology • High signal-integrity board • 15% faster • Unique high-end PCB material for highest possible performance High Speed Connector Advanced Power • Low profile, PCB-based Management • Low noise • Efficient power distribution • Better signal integrity • Precision voltage stability • 30% faster High-Speed Time Division Multiplexing (HSTDM) • 1 Gbit/sec data rate • Automated implementation • Increases interconnect bandwidth Time Division Multiplexing • 25% faster © Synopsys 2011 16
- 17. Reproducible, Documented DesignProcess Document and Trace Design Requirements • RTL, gate and physical schematics – Cross-probe between RTL, Netlist, Vendor and Synplify timing reports and schematics • Timing reports specifying – Start point(s) – End point(s) – Start and end points • Custom reports using Tcl/Find • Regenerate timing report without need to re-run synthesis © Synopsys 2011 17
- 18. Reproducible, Documented DesignProcess Tcl in Synplify Pro/Premier • Access objects in RTL / Technology Database Find command • Often complemented with Filter command • Access object groups and their attributes Collections • Present in Pro/Premier and several ASIC tools Expand • Traverse hierarchies command Use with most Pro/Premier project • add_file, get_env, set_option… etc. commands These commands augment standard Tcl commands © Synopsys 2011 18
- 19. Reproducible, Documented DesignProcess Custom Reporting and Analysis using Tcl/Find … An Example 1. Define a Tcl / Find script analysis_example.tcl open_design implementation_a/top.srm set find_DSP48Es [find -hier –inst {*} -filter @view == {DSP48E*}] set find_negslack [find -hier –seq –inst {*} -filter @slack < {-0.0}] c_print $find_DSP48Es -file DSP48Es.txt c_print -prop slack -prop view $find_negslack -file negslack.txt 2. Run the script from the command line synplify_pro –batch analysis_example.tcl DSP48Es.txt negslack.txt {i:CPU_A_SOC.CPU.MULT.ABH_4[34:0]} Object Name slack view {i:CPU_A_SOC.CPU.MULT.ABH_7[47:0]} {i:CPU_A_SOC.CPU.DATAPATH.GBR[0]} -3.264 "FDE" {i:CPU_B_SOC.CPU.MULT.ABH_0[34:0]} {i:CPU_A_SOC.CPU.DATAPATH.GBR[1]} -3.158 "FDE" {i:CPU_B_SOC.CPU.MULT.ABH_3[47:0]} {i:CPU_A_SOC.CPU.DATAPATH.GBR[2]} -3.091 "FDE" Inferred DSP48E instances Paths with negative slack © Synopsys 2011 19
- 20. Reproducible, Documented DesignProcess Re-synthesize archived designs Each project created in the UI is automatically saved as a tcl script (.tcl file) and as a project (.prj file) and includes source files, reports and results Save designs or hierarchical blocks as full project archive for future reuse project –archive Archives… • Design implementation files Re-import archive later including reports project –unarchive • Tcl files and project file Synthesis project restored • Input files (RTL, constraints) automatically © Synopsys 2011 20
- 21. Reproducible, Documented DesignProcess Preserve Parts of the Design • Synthesis optimizes the design to meet timing and then reduce area, removing redundant logic and collapsing nodes • Use synthesis attributes to preserve – Redundant logic for reliability purposes – Signals that you wish to probe – FSM error mitigation logic Attribute Value Description syn_keep 1/0 Preserve a net syn_probe 1/0 Preserve a net for probing syn_preserve 1/0 Preserve a cell / sequential component syn_hier firm, hard, macro, Preserve a block flatten syn_noprune 1/0 Preserve an instantiated component (Instance) © Synopsys 2011 21
- 22. Reproducible, Documented DesignProcess Preserving Names: RTL Netlist Disable Sequential Optimizations Implementation Options Device tab • 1:1 correspondence between RTL and netlist names • Trades off QoR © Synopsys 2011 22
- 23. Reproducible, Documented DesignProcess Reproducible results with Synplify products • Repeatable results – Synthesis results generally repeatable for a given FPGA device/speed grade targeted – “Path group” technology provides consistent results between runs when smalls change to the RTL or constraints occurs – Incremental flow and block-based flows isolate changes to only those blocks that changed © Synopsys 2011 23
- 24. Verification and EquivalenceChecks Synplify Premier Display /Selection of VCS Simulation Data • View selected simulation results from VCS – Annotated on device pins in Synplify HDL Analyst Schematic Viewer – In WaveForm Viewer • Time-slider updates and displays annotated signal values over time • Tcl scriptable signal /time selection • Use multiple HDL Analyst views to compare different simulations © Synopsys 2011 24
- 25. Verification and EquivalenceChecks Achieving Safety Critical Design Processes such as DO-254 Process Compliance Synplify Premier Synthesis Synphony HLS Algorithmic Reproducible FPGA Synthesis Identify RTL Debug on the (DSP) Synthesis Reporting, Documentation, Traceability Board System-Level Specifications via Schematics and Log Files Accurate Debugging Methodology Easily Documented Results Disable Optimizations that Mar RTL Level Visibility of Final Requirements Tracing Implementation Area, Power and Speed Optimizations Data Archiving and Textual Files for Easily Documented Results Simulink Spec vs. RTL Equivalence Requirements Management Applications VCS Simulation Testbench Simulation FPGA-Based Prototyping Coverage Analysis & Reporting HAPS FPGA-Based Prototype for Proof of Concept Waveform Generation Easily Documented Results & Reports © Synopsys 2011 25
- 26. Summary Key Componentsto Achieving Highly Reliable Design • Accurate design specification • Built-in FPGA design safety – Mitigate effects of radiation that may cause unwanted transients (SETs and SEUs) • Safe FSM implementation • Implement redundancy and voting logic (TMR) – Power Reduction • Evaluate correct design operation quickly – Trace requirements from specification to implementation – Custom reporting – RTL-level debug of the operating design – Debug and early proof of concept of a design using FPGA-based prototypes • Reproducible documented design processes © Synopsys 2011 26
- 27. THANK YOU © Synopsys2011 27