Introduction to Stellaris Family Microcontrollers


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Introduction of the Stellaris family microcontrollers, its basic architecture, and internal functional modules

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  • Welcome to the training module on Luminary Micro Stellaris Family Microcontrollers. This training module introduces the Stellaris family microcontrollers, its basic architecture, and internal functional modules.
  • Luminary Micro delivers the world's first silicon implementation of the Cortex-M3 processor, providing 32-bit performance at 8-/16-bit cost. The embedded microcontroller system designers can utilize 32-bit performance for the same price as their current 8- and 16-bit microcontroller designs! Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural upgrades or software tools changes. Designed for serious microcontroller applications, the Stellaris family provides the entry into the industry's strongest ecosystem, with code compatibility ranging from $1 to 1 GHz.
  • Stellaris family of microcontrollers incorporates the Cortex-M3 MCU core running up to 50 MHz, embedded flash and SRAM, a 32-ch DMA, a low drop-out voltage regulator, battery backed low-power hibernation capability, integrated brown-out reset and power-on reset functions, analog comparators, 10-bit ADC, GPIOs, and watchdog and general purpose timers. The family also integrates several serial interfaces, including 10/100 Ethernet MAC+PHY, CAN, USB On-The-Go, USB Host/Device, SSI/SPI, UARTs, and I 2 C. Finally, the Stellaris family features peripherals designed specifically for intense industrial motor control, including motion control PWMs and quadrature encoder inputs. However, not all Stellaris families have all these features.
  • The Cortex-M3 processor is the first ARM processor based on the ARMv7-M architecture and has been specifically designed to achieve high system performance in power- and cost-sensitive embedded applications, such as microcontrollers, automotive body systems, industrial control systems and wireless networking. It integrates the central processor core, called the CM3Core, with advanced system peripherals to enable integrated capabilities like interrupt control, memory protection and system debug and trace. The central Cortex-M3 core is based on the Harvard architecture characterized by separate buses for instructions and data. By being able to read both an instruction and data from memory at the same time, the Cortex-M3 processor can perform many operations in parallel, speeding application execution. .
  • The Cortex-M3 processor provides a high level of visibility into the system through a traditional JTAG port or the 2-pin Serial Wire Debug (SWD) port. JTAG has dedicated signals for data-in (TDI), data-out (TDO), mode control (TMS), and clocking (TCK), so transfer rates are significantly higher than PIC ICSP. SWD is closer to ICSP in design and is presently not widely supported by ARM debuggers. JTAG can be used for debugging, programming, and for boundary-scan test.
  • Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. The SIR function is programmed using the UARTCTL register. Data received or transmitted is stored in two separate FIFOs. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8.
  • Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes.
  • Some devices in the Stellaris family include Ethernet controller, which consists of a fully integrated media access controller (MAC) and network physical (PHY) interface. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers correspond to the OSI model layers 2 and 1. The CPU accesses the Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the PHY layer via an internal Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus.
  • Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical). Bit rates up to 1Mbps are possible at network lengths less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500 meters). The Stellaris® CAN controller conforms to the CAN protocol version 2.0 (parts A and B).
  • The Inter-Integrated Circuit (I 2 C) bus provides bi-directional data transfer through a two-wire design. The Stellaris I 2 C module provides the ability to communicate to other IC devices over an I 2 C bus. The I 2 C bus supports devices that can both transmit and receive (write and read) data. Devices on the I 2 C bus can be designated as either a master or a slave. The I 2 C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The Stellaris I 2 C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
  • The Stellaris devices contains up to 64KB single-cycle SRAM. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The Flash controller supports up to 256KB Flash. The flash is organized as a set of 1-KB blocks that can be individually erased. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection.
  • A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, it can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. The Stellaris® quadrature encoder interface (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel.
  • Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. Typical applications include switching power supplies and motor control. The Stellaris® PWM module consists of three PWM generator blocks and a control block. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The Stellaris® PWM module provides a great deal of flexibility. It can generate simple PWM signals, paired PWM signals with dead-band delays, and the full six channels of gate controls.
  • System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. System control determines the clocking and control of clocks. There are two fundamental clock sources for use in the device: the main oscillator, driven from either an external crystal or a single-ended source and the internal oscillator. The peripheral blocks are driven by the System Clock signal and can be programmatically enabled/disabled. The main oscillator is used for external resets and power-on resets; the internal oscillator is used during the internal process by internal reset and clock verification circuitry.
  • Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1, Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events.
  • A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
  • The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H). The GPIO module supports 0-60 programmable input/output pins, depending on the peripherals being used.
  • The Hibernation Module manages removal and restoration of power to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source.
  • The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V.
  • An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge.
  • An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris® ADC module features 10-bit conversion resolution and supports up to eight input channels, plus an internal temperature sensor. The ADC module contains four programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority.
  • The Stellaris® family offers efficient performance and extensive integration. Stellaris family is favorably positioned for cost-conscious applications requiring significant control processing and connectivity capabilities, including motion control, monitoring (remote, fire/security, etc.), HVAC and building controls, power and energy monitoring and conversion, network appliances and switches, factory automation, electronic point-of-sale machines, test and measurement equipment, medical instrumentation, and gaming equipment.
  • Thank you for taking the time to view this presentation on the Stellaris ® Family Microcontrollers . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Luminary Micro site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Introduction to Stellaris Family Microcontrollers

    1. 1. Introduction to Stellaris ® Family Microcontrollers <ul><li>Source: LUMINARY MICRO </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module introduces the Stellaris family microcontrollers, its basic architecture, and internal functional modules. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Overview of the Stellaris family </li></ul></ul><ul><ul><li>The basic architecture of the Stellaris family </li></ul></ul><ul><ul><li>Internal functional blocks </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>24 pages </li></ul></ul>
    3. 3. What is Stellaris? <ul><li>Stellaris </li></ul><ul><ul><li>Family of ARM Cortex-M3 based MCUs from Luminary Micro </li></ul></ul><ul><li>Key Advantages </li></ul><ul><ul><li>Designers can utilize 32-bit performance for the same price as their current 8- and 16-bit microcontroller designs </li></ul></ul><ul><ul><li>Stellaris allows for standardization that eliminates future architectural upgrades or software tools changes </li></ul></ul><ul><ul><li>With the ARM Cortex architecture, designers have access to an instruction-set-compatible family that ranges from $1 to 1 GHz </li></ul></ul>
    4. 4. The Stellaris Family Architecture <ul><li>Up to 50 MHz operation with 32-bit ARM Cortex-M3 architecture </li></ul><ul><li>8K to 256K Single-cycle Flash </li></ul><ul><li>8K to 64K Single-cycle SRAM </li></ul><ul><li>Flexible Timer Capability </li></ul><ul><ul><li>Up to 4 general purpose timer </li></ul></ul><ul><ul><li>24-bit system (SysTick) timer </li></ul></ul><ul><ul><li>32-bit watchdog timer </li></ul></ul><ul><li>Several serial interfaces </li></ul><ul><li>LDO voltage regulator </li></ul>In all members of the Stellaris family Optional on certain members of the Stellaris family
    5. 5. About Cortex-M3 <ul><li>The Cortex-M3 processor is the first ARM processor based on the ARMv7-M architecture. </li></ul><ul><li>The central Cortex-M3 core is based on the Harvard architecture. </li></ul><ul><li>The Cortex-M3 processor is a 32-bit processor, with a 32-bit wide data path, register bank and memory interface. </li></ul><ul><li>The Cortex-M3 processor has been designed to be fast and easy to program. </li></ul>CM3Core
    6. 6. Cortex-M3 Core in Stellaris <ul><li>JTAG </li></ul><ul><ul><li>Industry standard boundary scan for in-circuit debug and in-circuit programming </li></ul></ul><ul><li>Parallel JTAG TAP </li></ul><ul><ul><li>Allows access to chip JTAG for boundary scan, or Cortex-M3 JTAG for debug support </li></ul></ul><ul><li>Serial Wire Debug (SWD) </li></ul><ul><ul><li>New technology to provide debug access and control in two pins, with an optional pin for trace information </li></ul></ul><ul><li>Integrated Nested Vectored Interrupt Controller (NVIC) </li></ul><ul><ul><li>Provides deterministic interrupt handling </li></ul></ul>
    7. 7. Universal Asynchronous Receiver/Transmitter (UART) <ul><li>Up to 3 fully programmable 16C550-type UARTs </li></ul><ul><li>Separate transmit and receive FIFOs </li></ul><ul><li>Programmable FIFO length </li></ul><ul><li>FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 </li></ul><ul><li>Programmable baud-rate generator allowing speeds up to up to 3.125 Mbps </li></ul><ul><li>Standard asynchronous communication bits for start, stop and parity </li></ul><ul><li>The UART peripheral includes an IrDA serial-IR (SIR) encoder / decoder block. </li></ul><ul><li>False start bit detection </li></ul><ul><li>Line-break generation and detection </li></ul>
    8. 8. Synchronous Serial Interface (SSI) <ul><li>Master or slave operation </li></ul><ul><li>Programmable clock bit rate and prescale </li></ul><ul><li>Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep </li></ul><ul><li>Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces </li></ul><ul><li>Programmable data frame size from 4 to 16 bits Internal loopback test mode for diagnostic/debug testing </li></ul>
    9. 9. Ethernet Controller <ul><li>Conforms to the IEEE 802.3-2002 specification </li></ul><ul><ul><li>10BASE-T/100BASE-TX IEEE-802.3 compliant </li></ul></ul><ul><li>Multiple operational modes </li></ul><ul><ul><li>Full- and half-duplex 100 Mbps </li></ul></ul><ul><ul><li>Full- and half-duplex 10 Mbps </li></ul></ul><ul><ul><li>Power-saving and power-down modes </li></ul></ul><ul><li>Highly configurable </li></ul><ul><ul><li>Programmable MAC address </li></ul></ul><ul><ul><li>LED activity selection </li></ul></ul><ul><ul><li>User-configurable interrupts </li></ul></ul><ul><ul><li>CRC error-rejection control </li></ul></ul><ul><li>Physical media manipulation </li></ul><ul><ul><li>Automatic MDI/MDI-X cross-over correction </li></ul></ul><ul><ul><li>Register-programmable transmit amplitude </li></ul></ul><ul><ul><li>Automatic polarity correction and 10BASE-T signal reception </li></ul></ul>
    10. 10. Controller Area Network (CAN) <ul><li>CAN protocol version 2.0 part A/B </li></ul><ul><li>32 Bit rates up to 1 Mbps </li></ul><ul><li>32 message objects with individual identifier masks </li></ul><ul><li>Maskable interrupt </li></ul><ul><li>Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications </li></ul><ul><li>Programmable FIFO mode enables storage of multiple message objects </li></ul><ul><li>Programmable Loopback mode for self-test operation </li></ul>
    11. 11. Inter-Integrated Circuit (I 2 C) Interface <ul><li>I 2 C module provides the ability to communicate to other IC devices over an I 2 C bus. </li></ul><ul><li>The four I 2 C modes are: </li></ul><ul><ul><li>Master Transmit </li></ul></ul><ul><ul><li>Master Receive </li></ul></ul><ul><ul><li>Slave Transmit </li></ul></ul><ul><ul><li>Slave Receive </li></ul></ul><ul><li>The Stellaris I 2 C module can operate at two speeds </li></ul><ul><ul><li>Standard - 100 Kbps </li></ul></ul><ul><ul><li>Fast - 400 Kbps </li></ul></ul>
    12. 12. On-chip Memory <ul><li>Integrated single-cycle SRAM </li></ul><ul><ul><li>Stellaris offers from 2KB to 64KB </li></ul></ul><ul><ul><li>Bit-banded, allowing users the ability to use address aliases to access individual bits in a single, atomic operation </li></ul></ul><ul><li>Integrated single-cycle Flash </li></ul><ul><ul><li>Stellaris offers from 8KB to 256KB </li></ul></ul><ul><ul><li>Programmable Flash block protection </li></ul></ul><ul><ul><li>Programmable code protection </li></ul></ul>
    13. 13. Quadrature Encoder Interface (QEI) <ul><li>Position integrator that tracks the encoder position </li></ul><ul><li>Velocity capture using built-in timer </li></ul><ul><li>The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) </li></ul><ul><li>Interrupt generation on: </li></ul><ul><ul><li>Index pulse </li></ul></ul><ul><ul><li>Velocity-timer expiration </li></ul></ul><ul><ul><li>Direction change </li></ul></ul><ul><ul><li>Quadrature error detection </li></ul></ul>
    14. 14. Pulse Width Modulator (PWM) <ul><li>Three PWM generator blocks, each consists of </li></ul><ul><li>One 16-bit counter </li></ul><ul><ul><li>Runs in Down or Up/Down mode </li></ul></ul><ul><ul><li>Output frequency controlled by a 16-bit load value </li></ul></ul><ul><ul><li>Load value updates can be synchronized </li></ul></ul><ul><ul><li>Produces output signals at zero and load value </li></ul></ul><ul><li>Two PWM comparators </li></ul><ul><ul><li>Comparator value updates can be synchronized </li></ul></ul><ul><ul><li>Produces output signals on match </li></ul></ul><ul><li>One PWM generator </li></ul><ul><ul><li>Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals </li></ul></ul><ul><ul><li>Produces two independent PWM signals </li></ul></ul><ul><li>One Dead-band generator </li></ul><ul><ul><li>Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge </li></ul></ul><ul><ul><li>Can be bypassed, leaving input PWM signals unmodified </li></ul></ul><ul><li>Flexible output control block with PWM output enable of each PWM signal </li></ul>
    15. 15. System Control Module <ul><li>System control determines the clocking and control of clocks </li></ul><ul><ul><li>Two fundamental clock sources </li></ul></ul><ul><ul><ul><li>- An external crystal or a single-ended source </li></ul></ul></ul><ul><ul><ul><li>- The internal oscillator </li></ul></ul></ul><ul><ul><li>The clock gating logic for each peripheral or block is controlled for power-saving purposes. </li></ul></ul><ul><li>Reset control </li></ul><ul><ul><li>Power-On Reset (POR) - active on the initial power-up of the controller </li></ul></ul><ul><ul><li>Brown-Out Reset (BOR) - a drop in the input voltage can be used to reset the controller </li></ul></ul><ul><ul><li>Software Reset - each peripheral can be reset by software </li></ul></ul><ul><ul><li>Watchdog Timer Reset - prevents system hangs </li></ul></ul>
    16. 16. General-Purpose Timers <ul><li>4 General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. </li></ul><ul><li>32-bit Timer modes </li></ul><ul><ul><li>Programmable one-shot timer </li></ul></ul><ul><ul><li>Programmable periodic timer </li></ul></ul><ul><ul><li>Real-Time Clock when using an external 32.768KHz clock </li></ul></ul><ul><ul><li>Software-controlled event stalling (excluding RTC mode) </li></ul></ul><ul><ul><li>ADC event trigger </li></ul></ul><ul><li>16-bit Timer modes </li></ul><ul><ul><li>Programmable one-shot timer </li></ul></ul><ul><ul><li>Programmable periodic timer </li></ul></ul><ul><ul><li>General-purpose timer function with an 8-bit prescaler </li></ul></ul><ul><ul><li>ADC event trigger </li></ul></ul><ul><li>16-bit Input Capture modes - Input edge time capture </li></ul><ul><li>16-bit PWM mode - Simple PWM mode with software-programmable output inversion of the PWM signal </li></ul>
    17. 17. Watchdog Timer <ul><li>32-bit down counter with a programmable load register </li></ul><ul><li>Separate watchdog clock with an enable </li></ul><ul><li>Programmable interrupt generation logic with interrupt masking </li></ul><ul><li>Lock register protection from runaway software </li></ul><ul><li>Reset generation logic with an enable/disable </li></ul><ul><li>User-enabled stalling when the controller asserts the CPU Halt flag during debug </li></ul>
    18. 18. General-Purpose Input/Outputs (GPIOs) <ul><li>5V tolerant input/outputs </li></ul><ul><li>Programmable control for GPIO interrupts </li></ul><ul><ul><li>Interrupt generation masking </li></ul></ul><ul><ul><li>Edge-triggered on rising, falling, or both </li></ul></ul><ul><ul><li>Level-sensitive on High or Low values </li></ul></ul><ul><li>Bit masking in both read and write operations through address lines </li></ul><ul><li>Programmable control for GPIO pad configuration </li></ul><ul><ul><li>2mA, 4mA, and 8mA pad drive for digital communication </li></ul></ul><ul><ul><li>Weak pull-up or pull-down resistors </li></ul></ul><ul><ul><li>Slew rate control for the 8-mA drive </li></ul></ul><ul><ul><li>Open drain enables </li></ul></ul><ul><ul><li>Digital input enables </li></ul></ul>
    19. 19. Hibernation Module <ul><li>System power control using discrete external regulator </li></ul><ul><li>Dedicated pin for waking from an external signal </li></ul><ul><li>Low-battery detection, signaling, and interrupt generation </li></ul><ul><li>32-bit real-time counter (RTC) </li></ul><ul><li>Two 32-bit RTC match registers for timed wake-up and interrupt generation </li></ul><ul><li>Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal </li></ul><ul><li>RTC predivider trim for making fine adjustments to the clock rate </li></ul><ul><li>64 32-bit words of non-volatile memory </li></ul><ul><li>Programmable interrupts for RTC match, external wake, and low battery events </li></ul>
    20. 20. LDO Voltage Regulator <ul><li>To provide power to the majority of the controller’s internal logic </li></ul><ul><li>Adjustable from 0.9 to 3.3V in 50mv increments </li></ul><ul><li>To provide software a mechanism to adjust the regulated value </li></ul><ul><li>On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V </li></ul>
    21. 21. Analog Comparators <ul><li>Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample sequence </li></ul><ul><li>Compare external pin input to external pin input or to internal programmable voltage reference </li></ul><ul><li>Compare a test voltage against any one of these voltages </li></ul><ul><ul><li>An individual external reference voltage </li></ul></ul><ul><ul><li>A shared single external reference voltage </li></ul></ul><ul><ul><li>A shared internal reference voltage </li></ul></ul>
    22. 22. Analog-to-Digital Converter (ADC) <ul><li>Up to 8 analog input channels </li></ul><ul><li>Single-ended and differential-input configurations </li></ul><ul><li>On-chip internal temperature sensor </li></ul><ul><li>Flexible, configurable analog-to-digital conversion </li></ul><ul><li>Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs </li></ul><ul><li>Flexible trigger control </li></ul><ul><ul><li>Controller (software) </li></ul></ul><ul><ul><li>Timers </li></ul></ul><ul><ul><li>Analog Comparators </li></ul></ul><ul><ul><li>PWM </li></ul></ul><ul><ul><li>GPIO </li></ul></ul>
    23. 23. Summary <ul><li>Superior integration </li></ul><ul><li>Over 120 Stellaris family members to choose from </li></ul><ul><li>Real MCU GPIOs — all can generate interrupts, are 5V-tolerant, and have programmable drive strength and slew rate control </li></ul><ul><li>Advanced communication capabilities, including 10/100 Ethernet MAC/PHY and CAN controllers </li></ul><ul><li>Sophisticated motion control support in hardware and software </li></ul><ul><li>Both analog comparators and ADC functionality provide on-chip system options to balance hardware and software performance </li></ul><ul><li>Ease of development with the Stellaris Peripheral Driver Library’s high-level API interface to the entire Stellaris peripheral set </li></ul>
    24. 24. Additional Resource <ul><li>For ordering the Stellaris Microcontrollers, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li> </li></ul></ul>