1. AKHIL RANGA
(919) 931-6608 ♦ aranga@ncsu.edu ♦ 2520, Avent Ferry Road, Apt #202, Raleigh, NC – 27606
[LinkedIn: https://www.linkedin.com/in/akhilranga]
OBJECTIVE: Seeking a co-op/internship opportunity for summer 2016 in the field of Digital Design/Verification.
EDUCATION
North Carolina State University, Raleigh, NC GPA: 4.0/4.0 August 2015 - Dec 2016
Master of Science (MS) – Electrical and Computer Engineering
Relevant Coursework: Computer Design & Technology, Architecture of Parallel Computers, Digital ASIC design
Current Courses: GPU Architecture & Programing, Advanced Microarchitecture, 3D - Memory Controller Design
Birla Institute of Technology & Science (BITS), Pilani, India GPA: 7.85/10 August2009- June 2013
Bachelor of Engineering (Honors) – Electrical and Electronics Engineering
Relevant Coursework: VLSI Architecture, Analog & Digital VLSI design; Digital Electronics and Computer
Organization; Microprocessor programming and Interfacing; Micro Electronic Circuits.
TECHNICAL SKILLS
 Hardware Languages: Verilog, SystemVerilog , UVM.
 EDA tools: Cadence Virtuoso tools, NCSim, Modelsim, Aldec, Design Compiler, Xilinx (EDA&SDK kit)
 Scripting: Perl, Shell
 Programming: C and C++
PROFESSIONAL EXPERIENCE
 Concept2SiliconSystems, Bangalore, India Jul 2013 – Jun 2015
(Verification Engineer)
 Developed reference designs for Ethernet MAC IPs on 3-D programmable logic devices where time is used
as a third dimension.
 Functional Verification of Ethernet MAC IPs that support various IEEE flow control standards like Pause
Frame, Priority Flow Control (PFC), Auto-negotiation & have a bandwidth of 10G, 40G & 100Gbps.
 Added test-bench support in UVM based environment to enable verification of DDR PHY module for new
DDR4 features like CRC. Worked on UVM agents, Sequencers, TLM ports & TLM FIFOs.
 Broadcom India Research Ltd., Bangalore, India May – Dec 2012
(ASIC Verification, Co-op)
 Functional Verification of various flow control mechanisms implemented by an Ethernet switch with a data
bandwidth of 10 Gigabit.
 Gained working experience in design verification cycle right from test-bench development in System
Verilog (monitors, checkers, transactors) leading up to the feature verification, coverage evaluation and
running regressions.
ACADEMIC PROJECTS
 Designed a C++ Simulator for multi-level Cache hierarchy that supports WBWA, WTNA write policies and
uses LRU replacement policy. I have also simulated a victim cache for L1 cache.
 Extended above simulator to support Symmetric Multiprocessor (SMP) systems by implementing bus based
cache coherence protocols (MSI, MESI & Dragon).
 Designed a simulator that speculatively determines the direction of a branch instruction using bimodal,
gshare or hybrid predictors.
 Designed, Simulated & Synthesized hardware that implements Bellman Ford Algorithm to find shortest path
between any two nodes in a network.
 Designed a simulator for 9 stage pipeline superscalar out-of-order processor that has issue queue & reorder
buffer to support register renaming & mis-prediction recovery.
WORK AUTHORIZATION: Eligible to intern in the US with CPT.