This document discusses the construction of an arithmetic logic unit (ALU) using a hardware description language and field programmable gate arrays. Specifically, it simulates and analyzes various parameters of ALUs built using VHDL on the Xilinx ISE 9.2i software and a SPARTAN 3E FPGA board. It also discusses using FPGAs to implement sub-systems for an open-source FPGA-based mobile telephone handset as part of a long-term and complex project. A focus of this project is developing an Ethernet controller and memory mapped I/O interface for an Ethernet PHY.