The document covers the topic of digital logic related to counters and flip-flops, detailing various circuit diagrams and their functions. It includes constructs for D flip-flops, shift registers, synchronous and asynchronous counters, and examples of modulo counters. Also mentioned are practical aspects such as enable and clear capabilities for digital systems.

1. Instructor: Alexander Stoytchev
http://www.ece.iastate.edu/~alexs/classes/
CprE 281:
Digital Logic

2. Counters
CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff
• Homework 8 is out
• It is due on Monday Nov 11, 2013

4. Flip-Flops

5. [ Figure 5.7a from the textbook ]
Circuit Diagram for the Gated D Latch

6. Constructing a D Flip-Flop

7. Constructing a D Flip-Flop

8. Constructing a D Flip-Flop
(with one less NOT gate)

9. Constructing a D Flip-Flop
(with one less NOT gate)

10. Edge-Triggered D Flip-Flops

11. (a) Circuit
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Qm Qs
Clk
Clk
[ Figure 5.9a from the textbook ]
Master-Slave D Flip-Flop

12. D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Qm Qs
Clk
Clk
Negative-Edge-Triggered Master-Slave D Flip-Flop
Positive-Edge-Triggered Master-Slave D Flip-Flop
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Qm Qs
Clk
Clk

13. Registers

14. Register
(Definition)
An n-bit structure consisting of flip-flops

15. A simple shift register
[ Figure 5.17 from the textbook ]
D Q
Q
Clock
D Q
Q
D Q
Q
D Q
Q
In Out
t0
t1
t2
t3
t4
t5
t6
t7
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
Q1 Q2 Q3 Q4 Out
=
In
(b) A sample sequence
(a) Circuit
Q1 Q2 Q3 Q4

16. Parallel-access shift register
[ Figure 5.18 from the textbook ]

17. Counters

18. A three-bit up-counter
[ Figure 5.19 from the textbook ]

19. A three-bit up-counter
[ Figure 5.19 from the textbook ]
The first flip-flop changes
on the positive edge of the clock

20. A three-bit up-counter
[ Figure 5.19 from the textbook ]
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0

21. A three-bit up-counter
[ Figure 5.19 from the textbook ]
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1

22. A three-bit up-counter
[ Figure 5.19 from the textbook ]
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 6 7 0
(b) Timing diagram

23. A three-bit up-counter
[ Figure 5.19 from the textbook ]
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 6 7 0
(b) Timing diagram
The propagation delays get longer

24. A three-bit down-counter
[ Figure 5.20 from the textbook ]

25. A three-bit down-counter
[ Figure 5.20 from the textbook ]
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 7 6 5 4 3 2 1 0
(b) Timing diagram

26. Synchronous Counters

27. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

28. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]
The propagation delay through all AND gates combined must
not exceed the clock period minus the setup time for the flip-flops

29. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 1 2 3 5 9 12 14 0
(b) Timing diagram
T Q
Q
Q3
Q3
4 6 8
7 10 11 13 15 1

30. Derivation of the synchronous up-counter
[ Table 5.1 from the textbook ]
0
0
1
1
0
1
0
1
0
1
2
3
0
0
1
0
1
0
4
5
6
1 1
7
0
0
0
0
1
1
1
1
Clock cycle
0 0
8 0
Q2 Q1 Q0
Q1
changes
Q2
changes

31. Derivation of the synchronous up-counter
[ Table 5.1 from the textbook ]
0
0
1
1
0
1
0
1
0
1
2
3
0
0
1
0
1
0
4
5
6
1 1
7
0
0
0
0
1
1
1
1
Clock cycle
0 0
8 0
Q2 Q1 Q0
Q1
changes
Q2
changes
T0= 1
T1 = Q0
T2 = Q0 Q1

32. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]
T0= 1
T1 = Q0
T2 = Q0 Q1

33. In general we have
T0= 1
T1 = Q0
T2 = Q0 Q1
T3 = Q0 Q1 Q2
…
Tn = Q0 Q1 Q2 …Qn-1

34. Adding Enable and Clear Capability

35. Inclusion of Enable and Clear capability
[ Figure 5.22 from the textbook ]
T Q
Q
Clock
T Q
Q
Enable
Clear_n
T Q
Q
T Q
Q

36. Inclusion of Enable and Clear capability
[ Figure 5.22 from the textbook ]
T Q
Q
Clock
T Q
Q
Enable
Clear_n
T Q
Q
T Q
Q
This is the new thing relative to
the previous figure, plus the clear_n line

37. Figure 5.56. Providing an enable input for a D flip-flop.

38. Synchronous Counter with D Flip-Flops

39. A four-bit counter with D flip-flops
[ Figure 5.23 from the textbook ]

40. Counters with Parallel Load

41. A counter with parallel-load capability
[ Figure 5.24 from the textbook ]

42. A shift register with parallel load and
enable control inputs
[ Figure 5.59 from the textbook ]

43. Reset Synchronization

44. Motivation
• An n-bit counter counts from 0, 1, …, 2n
-1
• For example a 3-bit counter counts up as follow
 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, …
• What if we want it to count like this
 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1, …
• In other words, what is the cycle is not a power of 2?

45. What does this circuit do?
[ Figure 5.25a from the textbook ]

46. A modulo-6 counter with synchronous reset
[ Figure 5.25 from the textbook ]
Enable
Q0
Q1
Q2
D0
D1
D2
Load
Clock
1
0
0
0
Clock
0 1 2 3 4 5 0 1
Clock
Count
Q0
Q1
Q2
(a) Circuit
(b) Timing diagram

47. A modulo-6 counter with asynchronous reset
[ Figure 5.26 from the textbook ]
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count
(b) Timing diagram
0 1 2 3 4 5 0 1 2

48. A modulo-6 counter with asynchronous reset
[ Figure 5.26 from the textbook ]
T Q
Q
Clock
T Q
Q
T Q
Q
1
Q0 Q1 Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count
(b) Timing diagram
0 1 2 3 4 5 0 1 2
The number 5 is displayed
for a very short amount of time

49. Questions?

50. THE END