This document describes a proposed low-power CORDIC-based DCT architecture that prioritizes processing of low-frequency DCT coefficients over high-frequency coefficients to reduce power consumption with minimal image quality degradation. It uses a look-ahead CORDIC approach to allow varying the number of CORDIC iterations for different coefficients. Experimental results show the proposed architecture achieves 38.1% area and power savings compared to DA-based DCT, with comparable power to MCM-based DCT but using 100% less area and a minor 0.04dB quality loss.
Area Time Efficient Scaling Free Rotation Mode Cordic Using Circular TrajectoryIOSR Journals
Abstract: This paper presents an area-time efficient Coordinate Rotation Digital Computer (CORDIC) algorithm that completely eliminates the scale-factor. Besides we have proposed an algorithm to reduce the number of CORDIC iterations by increasing the number of stages. The efficient scale factor compensation techniques are proposed which adversely effect the latency/throughput of computation. The proposed CORDIC algorithm provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. The CORDIC is an iterative arithmetic algorithm for computing generalized vector rotations without performing multiplications. Index Terms: coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array (FPGA), most-significant-1, recursive architecture, Discrete Fourier Transform (DFT), Discrete Cosine transform (DCT), Iterative CORDIC, Pipelined CORDIC.
FPGA Implementation of 2-D DCT & DWT Engines for Vision Based Tracking of Dyn...IJERA Editor
Real time motion estimation for tracking is a challenging task. Several techniques can transform an image into frequency domain, such as DCT, DFT and wavelet transform. Direct implementation of 2-D DCT takes N^4 multiplications for an N x N image which is impractical. The proposed architecture for implementation of 2-D DCT uses look up tables. They are used to store pre-computed vector products that completely eliminate the multiplier. This makes the architecture highly time efficient, and the routing delay and power consumption is also reduced significantly. Another approach, 2-D discrete wavelet transform based motion estimation (DWT-ME) provides substantial improvements in quality and area. The proposed architecture uses Haar wavelet transform for motion estimation. In this paper, we present the comparison of the performance of discrete cosine transform, discrete wavelet transform for implementation in motion estimation.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
Area Time Efficient Scaling Free Rotation Mode Cordic Using Circular TrajectoryIOSR Journals
Abstract: This paper presents an area-time efficient Coordinate Rotation Digital Computer (CORDIC) algorithm that completely eliminates the scale-factor. Besides we have proposed an algorithm to reduce the number of CORDIC iterations by increasing the number of stages. The efficient scale factor compensation techniques are proposed which adversely effect the latency/throughput of computation. The proposed CORDIC algorithm provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. The CORDIC is an iterative arithmetic algorithm for computing generalized vector rotations without performing multiplications. Index Terms: coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array (FPGA), most-significant-1, recursive architecture, Discrete Fourier Transform (DFT), Discrete Cosine transform (DCT), Iterative CORDIC, Pipelined CORDIC.
FPGA Implementation of 2-D DCT & DWT Engines for Vision Based Tracking of Dyn...IJERA Editor
Real time motion estimation for tracking is a challenging task. Several techniques can transform an image into frequency domain, such as DCT, DFT and wavelet transform. Direct implementation of 2-D DCT takes N^4 multiplications for an N x N image which is impractical. The proposed architecture for implementation of 2-D DCT uses look up tables. They are used to store pre-computed vector products that completely eliminate the multiplier. This makes the architecture highly time efficient, and the routing delay and power consumption is also reduced significantly. Another approach, 2-D discrete wavelet transform based motion estimation (DWT-ME) provides substantial improvements in quality and area. The proposed architecture uses Haar wavelet transform for motion estimation. In this paper, we present the comparison of the performance of discrete cosine transform, discrete wavelet transform for implementation in motion estimation.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
HARDWARE EFFICIENT SCALING FREE VECTORING AND ROTATIONAL CORDIC FOR DSP APPLI...VLSICS Design
The COordinate Rotation DIgital Computer CORDIC algorithm has proved its versatility in computing
various transcendental functions by only using the shift and adds operations. This paper presents a new
hardware efficient scaling free CORDIC algorithm to operate in vectoring and in rotation mode. The
micro rotation of the vector is always in one direction with no scale factor correction. The Range of
Convergence RoC is from 0 to 2. No pre and post processing circuitry is required. 16 bit Scaling free
CORDIC Pipelined architecture based on the proposed algorithm is synthesized on FPGA Xilinx VirtexII P
device coded in Verilog. Synthesized results show totally scaling free performance with very small
dynamic power consumption of .06 mW and maximum delay of 4.123 ns and 9.925 ns in the rotational and
vectoring modes respectively. The minimum BEP of the proposed algorithm implementation is 12.
Proposed algorithm is faster and efficient in terms of area and accuracy as compared to conventional
CORDIC.
Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
Highly Parallel Pipelined VLSI Implementation of Lifting Based 2D Discrete Wa...idescitation
The lifting scheme based Discrete Wavelet
Transform is a powerful tool for image processing
applications. The lack of disk space during transmission and
storage of images pushes the demand for high speed
implementation of efficient compression technique. This paper
proposes a highly pipelined and distributed VLSI architecture
of lifting based 2D DWT with lifting coefficients represented
in fixed point [2:14] format. Compared to conventional
architectures [11], [13]-[16], the proposed highly pipelined
architecture optimizes the design which increases
significantly the performance speed. The design raises the
operating frequency, at the expense of more hardware area.
In this paper, initially a software model of the proposed design
was developed using MATLAB ®. Corresponding to this
software model, an efficient highly parallel pipelined
architecture was designed and developed using verilog HDL
language and implemented in VIRTEX ® 6 (XC6VHX380T)
FPGA. Also the design was synthesized on TSMC 0.18μm
ASIC Library by using Synopsis Design Compiler. The entire
system is suitable for several real time applications.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
HIGH SPEED REVERSE CONVERTER FOR HIGH DYNAMIC RANGE MODULI SETP singh
In this paper a new reverse converter architecture for the five moduli set {2n, 2n/2-1, 2n/2+1, 2n+1, 22n-1-1} is presented. The proposed converter is designed in two levels architecture by using of New Chinese Reminder Theorem-I (New CRT-I) and Mixed Radix Conversion (MRC). The proposed architecture has achieved significant improvement in terms of delay of the reverse converter compared to state-of-the-art reverse converters.
EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGAVLSICS Design
Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
A verilog based implementation of transcendental function calculator using co...eSAT Journals
Abstract The CORDIC (COordinate Rotation DIgital Computer) algorithm is an iterative algorithm developed by Volder [1] in 1959. It rotates the vector, iteratively and in finite steps to calculate Sine and Cosine of a given angle. Additional work has been done by Walther [2] in 1971. The main principle of CORDIC are calculations based on shift−registers and adders instead of multiplications, which makes use of limited reconfigurable CLB’s in FPGA efficiently saving hardware resources. All trigonometric functions can be computed using vector rotation. CORDIC is also used for polar to rectangular and rectangular to polar conversions, calculation of vector magnitude, and also for transforms like discrete Fourier transform (DFT)/FFT on reconfigurable platform. This paper presents the CORDIC Algorithm for calculation of elementary functions Sine and Cosine in IEEE-754 Format and Q-Format. The paper analyses the feasibility of CORDIC algorithm for implementing the elementary angle computation in FPGA .The CORDIC algorithm is implemented using Verilog language and results are obtained from Xilinx ISE simulation. Keywords: CORDIC, Elementary angle, FPGA, SDR, VHDL
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
Direct digital synthesis based cordic algorithm a novel approach towards digi...eSAT Journals
Abstract Modulation is the technique in which carrier signal varies according to amplitude of modulating signal. A brilliant solution for realizing digital modulators is CORDIC (CO-ordinate Rotation Digital Computer) algorithm. Rotation mode and vector mode are two modes in which this algorithm is used. Here rotation mode is used to convert the coordinates from polar mode to rectangular mode. This paper presents the implementation of different communication subsystems like ASK, FSK, PSK, BPSK, QPSK, 4 QAM, 16 QAM that can be found in software defined radio by using CORDIC algorithm. The focus of this paper is to analysis and simulation of modulation scheme using Direct Digital Synthesizer having CORDIC algorithm. Keywords: Software Defined Radio, CORDIC algorithm, DDS, ASK, FSK, PSK, BPSK, QPSK, 4-QAM, 16-QAM.
Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine GenerationIOSR Journals
Abstract: This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.
HARDWARE EFFICIENT SCALING FREE VECTORING AND ROTATIONAL CORDIC FOR DSP APPLI...VLSICS Design
The COordinate Rotation DIgital Computer CORDIC algorithm has proved its versatility in computing
various transcendental functions by only using the shift and adds operations. This paper presents a new
hardware efficient scaling free CORDIC algorithm to operate in vectoring and in rotation mode. The
micro rotation of the vector is always in one direction with no scale factor correction. The Range of
Convergence RoC is from 0 to 2. No pre and post processing circuitry is required. 16 bit Scaling free
CORDIC Pipelined architecture based on the proposed algorithm is synthesized on FPGA Xilinx VirtexII P
device coded in Verilog. Synthesized results show totally scaling free performance with very small
dynamic power consumption of .06 mW and maximum delay of 4.123 ns and 9.925 ns in the rotational and
vectoring modes respectively. The minimum BEP of the proposed algorithm implementation is 12.
Proposed algorithm is faster and efficient in terms of area and accuracy as compared to conventional
CORDIC.
Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
Highly Parallel Pipelined VLSI Implementation of Lifting Based 2D Discrete Wa...idescitation
The lifting scheme based Discrete Wavelet
Transform is a powerful tool for image processing
applications. The lack of disk space during transmission and
storage of images pushes the demand for high speed
implementation of efficient compression technique. This paper
proposes a highly pipelined and distributed VLSI architecture
of lifting based 2D DWT with lifting coefficients represented
in fixed point [2:14] format. Compared to conventional
architectures [11], [13]-[16], the proposed highly pipelined
architecture optimizes the design which increases
significantly the performance speed. The design raises the
operating frequency, at the expense of more hardware area.
In this paper, initially a software model of the proposed design
was developed using MATLAB ®. Corresponding to this
software model, an efficient highly parallel pipelined
architecture was designed and developed using verilog HDL
language and implemented in VIRTEX ® 6 (XC6VHX380T)
FPGA. Also the design was synthesized on TSMC 0.18μm
ASIC Library by using Synopsis Design Compiler. The entire
system is suitable for several real time applications.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
HIGH SPEED REVERSE CONVERTER FOR HIGH DYNAMIC RANGE MODULI SETP singh
In this paper a new reverse converter architecture for the five moduli set {2n, 2n/2-1, 2n/2+1, 2n+1, 22n-1-1} is presented. The proposed converter is designed in two levels architecture by using of New Chinese Reminder Theorem-I (New CRT-I) and Mixed Radix Conversion (MRC). The proposed architecture has achieved significant improvement in terms of delay of the reverse converter compared to state-of-the-art reverse converters.
EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGAVLSICS Design
Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
A verilog based implementation of transcendental function calculator using co...eSAT Journals
Abstract The CORDIC (COordinate Rotation DIgital Computer) algorithm is an iterative algorithm developed by Volder [1] in 1959. It rotates the vector, iteratively and in finite steps to calculate Sine and Cosine of a given angle. Additional work has been done by Walther [2] in 1971. The main principle of CORDIC are calculations based on shift−registers and adders instead of multiplications, which makes use of limited reconfigurable CLB’s in FPGA efficiently saving hardware resources. All trigonometric functions can be computed using vector rotation. CORDIC is also used for polar to rectangular and rectangular to polar conversions, calculation of vector magnitude, and also for transforms like discrete Fourier transform (DFT)/FFT on reconfigurable platform. This paper presents the CORDIC Algorithm for calculation of elementary functions Sine and Cosine in IEEE-754 Format and Q-Format. The paper analyses the feasibility of CORDIC algorithm for implementing the elementary angle computation in FPGA .The CORDIC algorithm is implemented using Verilog language and results are obtained from Xilinx ISE simulation. Keywords: CORDIC, Elementary angle, FPGA, SDR, VHDL
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
Direct digital synthesis based cordic algorithm a novel approach towards digi...eSAT Journals
Abstract Modulation is the technique in which carrier signal varies according to amplitude of modulating signal. A brilliant solution for realizing digital modulators is CORDIC (CO-ordinate Rotation Digital Computer) algorithm. Rotation mode and vector mode are two modes in which this algorithm is used. Here rotation mode is used to convert the coordinates from polar mode to rectangular mode. This paper presents the implementation of different communication subsystems like ASK, FSK, PSK, BPSK, QPSK, 4 QAM, 16 QAM that can be found in software defined radio by using CORDIC algorithm. The focus of this paper is to analysis and simulation of modulation scheme using Direct Digital Synthesizer having CORDIC algorithm. Keywords: Software Defined Radio, CORDIC algorithm, DDS, ASK, FSK, PSK, BPSK, QPSK, 4-QAM, 16-QAM.
Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine GenerationIOSR Journals
Abstract: This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.
A CORDIC based QR Decomposition Technique for MIMO Detection IJECEIAES
CORDIC based improved real and complex QR Decomposition (QRD) for channel pre-processing operations in (Multiple-Input Multiple-Output) MIMO detectors are presented in this paper. The proposed design utilizes pipelining and parallel processing techniques and reduces the latency and hardware complexity of the module respectively. Computational complexity analysis report shows the superiority of our module by 16% compared to literature. The implementation results reveal that the proposed QRD takes shorter lat ency compared to literature. The power consumption of 2x2 real channel matrix and 2x2 complex channel matrix was found to be 12mW and 44mW respectively on the state-of-the-art Xilinx Virtex 5 FPGA.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
“ Implimentation of SD Processor Based On CRDC Algorithm ”inventionjournals
In Digital Signal Processing (DSP) there are many complex algorithms for which an efficient hardware implementation is required in real time applications. One such complex algorithm is Singular-value Decomposition (SD) which is an important algorithm with applications in varied domains of signal processing such as direction estimation, spectrum analysis and systems identification. It is a generalized extension to the eigen-decomposition for non-square matrices and is hence of great importance, particularly for subspace based algorithms in signal processing. But SD is known to be a very complicated algorithm with computational complexity ~O(N3 ) (for a NxN square matrix). For real-time computation of such a complex algorithm the use of a parallel and direct mapped hardware solution is indeed desired.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Energy efficiency is one of the most critical issue in design of System on Chip. In Network On
Chip (NoC) based system, energy consumption is influenced dramatically by mapping of
Intellectual Property (IP) which affect the performance of the system. In this paper we test the
antecedently extant proposed algorithms and introduced a new energy proficient algorithm
stand for 3D NoC architecture. In addition a hybrid method has also been implemented using
bioinspired optimization (particle swarm optimization) technique. The proposed algorithm has
been implemented and evaluated on randomly generated benchmark and real life application
such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing algorithm (spiral and crinkle) and has shown better
reduction in the communication energy consumption and shows improvement in the
performance of the system. Comparing our work with spiral and crinkle, experimental result
shows that the average reduction in communication energy consumption is 19% with spiral and
17% with crinkle mapping algorithms, while reduction in communication cost is 24% and 21%
whereas reduction in latency is of 24% and 22% with spiral and crinkle. Optimizing our work
and the existing methods using bio-inspired technique and having the comparison among them
an average energy reduction is found to be of 18% and 24%.
ENERGY AND LATENCY AWARE APPLICATION MAPPING ALGORITHM & OPTIMIZATION FOR HOM...cscpconf
Energy efficiency is one of the most critical issue in design of System on Chip. In Network On
Chip (NoC) based system, energy consumption is influenced dramatically by mapping of
Intellectual Property (IP) which affect the performance of the system. In this paper we test the
antecedently extant proposed algorithms and introduced a new energy proficient algorithm
stand for 3D NoC architecture. In addition a hybrid method has also been implemented using
bioinspired optimization (particle swarm optimization) technique. The proposed algorithm has
been implemented and evaluated on randomly generated benchmark and real life application
such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing algorithm (spiral and crinkle) and has shown better
reduction in the communication energy consumption and shows improvement in the
performance of the system. Comparing our work with spiral and crinkle, experimental result
shows that the average reduction in communication energy consumption is 19% with spiral and
17% with crinkle mapping algorithms, while reduction in communication cost is 24% and 21%
whereas reduction in latency is of 24% and 22% with spiral and crinkle. Optimizing our work
and the existing methods using bio-inspired technique and having the comparison among them
an average energy reduction is found to be of 18% and 24%.
A Novel Image Compression Approach Inexact Computingijtsrd
This work proposes a novel approach for digital image processing that relies on faulty computation to address some of the issues with discrete cosine transformation DCT compression. The proposed system has three processing stages the first employs approximated DCT for picture compression to eliminate all compute demanding floating point multiplication and to execute DCT processing with integer additions and, in certain cases, logical right left modifications. The second level reduces the amount of data that must be processed from the first level by removing frequencies that cannot be perceived by human senses. Finally, in order to reduce power consumption and delay, the third stage employs erroneous circuit level adders for DCT computation. A collection of structured pictures is compressed for measurement using the suggested three level method. Various figures of merit such as energy consumption, delay, power signal to noise ratio, average difference, and absolute maximum difference are compared to current compression techniques an error analysis is also carried out to substantiate the simulation findings. The results indicate significant gains in energy and time reduction while retaining acceptable accuracy levels for image processing applications. Sonam Kumari | Manish Rai "A Novel Image Compression Approach-Inexact Computing" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-6 | Issue-6 , October 2022, URL: https://www.ijtsrd.com/papers/ijtsrd52197.pdf Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/52197/a-novel-image-compression-approachinexact-computing/sonam-kumari
FPGA Implementation of Pipelined CORDIC Sine Cosine Digital Wave Generator cscpconf
The coordinate rotation digital computer (CORDIC) algorithm is well known iterative
algorithm for performing rotations in digital signal processing applications. Hardware
implementation of CORDIC results increase in Critical path delay. Pipelined architecture isused in CORDIC to increase the clock speed and to reduce the Critical path delay. In this paper a hardware efficient Digital sine and cosine wave generator is designed and implemented using Pipelined CORDIC architecture. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device
Design and analysis of optimized CORDIC based GMSK system on FPGA platform IJECEIAES
The gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.
https://technoelectronics44.blogspot.com/
GDI TECHNOLOGY, here you get GDI implementation and design of GDI based gates AND, OR, XOR, and Adders like CLA, CIA, CSKA, performance analysis of CMOS And GDI
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr AlgorithmIJERA Editor
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There
are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to
the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different
versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance.
The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory
consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this
increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select
(ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3
FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT
log BCJR decoder.
A NEW DATA ENCODER AND DECODER SCHEME FOR NETWORK ON CHIPEditor IJMTER
System-on-chip (soc) based system has so many disadvantages in power-dissipation as
well as clock rate while the data transfer from one system to another system in on-chip. At the same
time, a higher operated system does not support the lower operated bus network for data transfer.
However an alternative scheme is proposed for high speed data transfer. But this scheme is limited to
SOCs. Unlike soc, network-on-chip (NOC) has so many advantages for data transfer. It has a special
feature to transfer the data in on-chip named as transitional encoder. Its operation is based on input
transitions. At the same time it supports systems which are higher operated frequencies. In this
project, a low-power encoding scheme is proposed. The proposed system yields lower dynamic
power dissipation due to the reduction of switching activity and coupling switching activity when
compared to existing system. Even-though many factors which is based on power dissipation, the
dynamic power dissipation is only considerable for reasonable advantage. The proposed system is
synthesized using quartus II 9.1 software. Besides, the proposed system will be extended up to
interlink PE communication with help of routers and PE’s which are performed by various
operations. To implement this system in real NOC’s contains the proposed encoders and decoders for
data transfer with regular traffic scenarios should be considered.
A RESEARCH - DEVELOP AN EFFICIENT ALGORITHM TO RECOGNIZE, SEPARATE AND COUNT ...Editor IJMTER
Coins are important part of our life. We use coins in a places like stores, banks, buses, trains
etc. So it becomes a basic need that coins can be sorted, counted automatically. For this, there is
necessary that the coins can be recognized automatically. Automated Coin Recognition System for the
Indian Coins of Rs. 1, 2, 5 and 10 with the rotation invariance. We have taken images from the both
sides of coin. So this system is capable to recognizing coins from both sides. Features are taken from the
images using techniques as a Hough Transformation, Pattern Averaging etc.
Analysis of VoIP Traffic in WiMAX EnvironmentEditor IJMTER
Worldwide Interoperability for Microwave Access (WiMAX) is currently one of the
hottest technologies in wireless communication. It is a standard based on the IEEE 802.16 wireless
technology that provides a very high throughput broadband connections over long distances. In
parallel, Voice Over Internet Protocol (VoIP) is a new technology which provides access to voice
communication over internet protocol and hence it is becomes an alternative to public switched
telephone networks (PSTN) due to its capability of transmission of voice as packets over IP
networks. A lot of research has been done in analyzing the performances of VoIP traffic over
WiMAX network. In this paper we review the analysis carried out by several authors for the most
common VoIP codec’s which are G.711, G.723.1 and G.729 over a WiMAX network using various
service classes. The objective is to compare the results for different types of service classes with
respect to the QoS parameters such as throughput, average delay and average jitter.
A Hybrid Cloud Approach for Secure Authorized De-DuplicationEditor IJMTER
The cloud backup is used for the personal storage of the people in terms of reducing the
mainlining process and managing the structure and storage space managing process. The challenging
process is the deduplication process in both the local and global backup de-duplications. In the prior
work they only provide the local storage de-duplication or vice versa global storage de-duplication in
terms of improving the storage capacity and the processing time. In this paper, the proposed system
is called as the ALG- Dedupe. It means the Application aware Local-Global Source De-duplication
proposed system to provide the efficient de-duplication process. It can provide the efficient deduplication process with the low system load, shortened backup window, and increased power
efficiency in the user’s personal storage. In the proposed system the large data is partitioned into
smaller part which is called as chunks of data. Here the data may contain the redundancy it will be
avoided before storing into the storage area.
Aging protocols that could incapacitate the InternetEditor IJMTER
The biggest threat to the Internet is the fact that it was never really designed. For e.g., the
BGP protocol is used by Internet routers to exchange information about changes to the Internet's
network topologies. However, it also is among the most fundamentally broken; as Internet routing
information can be poisoned with bogus routing information. Instead, it evolved in fits and start,
thanks to various protocols that have been cobbled together to fulfill the needs of the moment. Few
of protocols from them were designed with security in mind. or if they were sported no more than
was needed to keep out a nosy neighbor, not a malicious attacker. The result is a welter of aging
protocols susceptible to exploit on an Internet scale. Here are six Internet protocols that could stand
to be replaced sooner rather than later or are (mercifully) on the way out.
A Cloud Computing design with Wireless Sensor Networks For Agricultural Appli...Editor IJMTER
The emergence of exactitude agriculture has been promoted by the numerous developments within
the field of wireless sensing element actor networks (WSAN). These WSANs offer important data
for gathering, work management, development of crops, and limitation of crop diseases. Goals of
this paper to introducing cloud computing as a brand new way (technique) to be utilized in addition
to WSANs to any enhance their application and benefits to the area of agriculture.
A CAR POOLING MODEL WITH CMGV AND CMGNV STOCHASTIC VEHICLE TRAVEL TIMESEditor IJMTER
Carpooling (also car-sharing, ride-sharing, lift-sharing), is the sharing of car journeys so
that more than one person travels in a car. It helps to resolve a variety of problems that continue to
plague urban areas, ranging from energy demands and traffic congestion to environmental pollution.
Most of the existing method used stochastic disturbances arising from variations in vehicle travel
times for carpooling. However it doesn’t deal with the unmet demand with uncertain demand of the
vehicle for car pooling. To deal with this the proposed system uses Chance constrained
formulation/Programming (CCP) approach of the problem with stochastic demand and travel time
parameters, under mild assumptions on the distribution of stochastic parameters; and relates it with a
robust optimization approach. Since real problem sizes can be large, it could be difficult to find
optimal solutions within a reasonable period of time. Therefore solution algorithm using tabu
heuristic solution approach is developed to solve the model. Therefore, we constructed a stochastic
carpooling model that considers the in- fluence of stochastic travel times. The model is formulated as
an integer multiple commodity network flow problem. Since real problem sizes can be large, it could
be difficult to find optimal solutions within a reasonable period of time.
Sustainable Construction With Foam Concrete As A Green Green Building MaterialEditor IJMTER
A green building is an environmentally sustainable building, designed, constructed and
operated to minimise the total environmental impacts. Carbon dioxide (CO2) is the primary
greenhouse gas emitted through human activities. It is claimed that 5% of the world’s carbon dioxide
emission is attributed to cement industry, which is the vital constituent of concrete. Due to the
significant contribution to the environmental pollution, there is a need for finding an optimal solution
along with satisfying the civil construction needs. Apart from normal concrete bricks, a clay brick,
Foam concrete is a new innovative technology for sustainable building and civil construction which
fulfills the criteria of being a Green Material. This paper concludes that Foam Concrete can be an
effective sustainable material for construction and also focuses on the cost effectiveness in using
Foam Concrete as a building material in replacement with Clay Brick or other bricks.
USE OF ICT IN EDUCATION ONLINE COMPUTER BASED TESTEditor IJMTER
A good education system is required for overall prosperity of a nation. A tremendous
growth in the education sector had made the administration of education institutions complex. Any
researches reveal that the integration of ICT helps to reduce the complexity and enhance the overall
administration of education. This study has been undertaken to identify the various functional areas
to which ICT is deployed for information administration in education institutions and to find the
current extent of usage of ICT in all these functional areas pertaining to information administration.
The various factors that contribute to these functional areas were identified. A theoretical model was
derived and validated.
Textual Data Partitioning with Relationship and Discriminative AnalysisEditor IJMTER
Data partitioning methods are used to partition the data values with similarity. Similarity
measures are used to estimate transaction relationships. Hierarchical clustering model produces tree
structured results. Partitioned clustering produces results in grid format. Text documents are
unstructured data values with high dimensional attributes. Document clustering group ups unlabeled text
documents into meaningful clusters. Traditional clustering methods require cluster count (K) for the
document grouping process. Clustering accuracy degrades drastically with reference to the unsuitable
cluster count.
Textual data elements are divided into two types’ discriminative words and nondiscriminative
words. Only discriminative words are useful for grouping documents. The involvement of
nondiscriminative words confuses the clustering process and leads to poor clustering solution in return.
A variation inference algorithm is used to infer the document collection structure and partition of
document words at the same time. Dirichlet Process Mixture (DPM) model is used to partition
documents. DPM clustering model uses both the data likelihood and the clustering property of the
Dirichlet Process (DP). Dirichlet Process Mixture Model for Feature Partition (DPMFP) is used to
discover the latent cluster structure based on the DPM model. DPMFP clustering is performed without
requiring the number of clusters as input.
Document labels are used to estimate the discriminative word identification process. Concept
relationships are analyzed with Ontology support. Semantic weight model is used for the document
similarity analysis. The system improves the scalability with the support of labels and concept relations
for dimensionality reduction process.
Testing of Matrices Multiplication Methods on Different ProcessorsEditor IJMTER
There are many algorithms we found for matrices multiplication. Until now it has been
found that complexity of matrix multiplication is O(n3). Though Further research found that this
complexity can be decreased. This paper focus on the algorithm and its complexity of matrices
multiplication methods.
Malware is a worldwide pandemic. It is designed to damage computer systems without
the knowledge of the owner using the system. Software‟s from reputable vendors also contain
malicious code that affects the system or leaks information‟s to remote servers. Malware‟s includes
computer viruses, spyware, dishonest ad-ware, rootkits, Trojans, dialers etc. Malware detectors are
the primary tools in defense against malware. The quality of such a detector is determined by the
techniques it uses. It is therefore imperative that we study malware detection techniques and
understand their strengths and limitations. This survey examines different types of Malware and
malware detection methods.
SURVEY OF TRUST BASED BLUETOOTH AUTHENTICATION FOR MOBILE DEVICEEditor IJMTER
Practical requirements for securely demonstrating identities between two handheld
devices are an important concern. The adversary can inject a Man-In- The-Middle (MITM) attack to
intrude the protocol. Protocols that employ secret keys require the devices to share private
information in advance, in which it is not feasible in the above scenario. Apart from insecurely
typing passwords into handheld devices or comparing long hexadecimal keys displayed on the
devices’ screen, many other human-verifiable protocols have been proposed in the literature to solve
the problem. Unfortunately, most of these schemes are unsalable to more users. Even when there are
only three entities attempt to agree a session key, these protocols need to be rerun for three times.
So, in the existing method a bipartite and a tripartite authentication protocol is presented using a
temporary confidential channel. Besides, further extend the system into a transitive authentication
protocol that allows multiple handheld devices to establish a conference key securely and efficiently.
But this method detects only the outsider attacks. Method does not consider the insider attacks. So,
in the proposed method trust score based method is introduced which computes the trust values for
the nodes and provide the security. The trust score is computed has a positive influence on the
confidence with which an entity conducts transactions with that node. Network the behavior of the
node will be monitored periodically and its trust value is also updated .So depending on the behavior
of the node in the network trust relation will be established between two nodes.
GLAUCOMA is a chronic eye disease that can damage optic nerve. According to WHO It
is the second leading cause of blindness, and is predicted to affect around 80 million people by 2020.
Development of the disease leads to loss of vision, which occurs increasingly over a long period of
time. As the symptoms only occur when the disease is quite advanced so that glaucoma is called the
silent thief of sight. Glaucoma cannot be cured, but its development can be slowed down by
treatment. Therefore, detecting glaucoma in time is critical. However, many glaucoma patients are
unaware of the disease until it has reached its advanced stage. In this paper, some manual and
automatic methods are discussed to detect glaucoma. Manual analysis of the eye is time consuming
and the accuracy of the parameter measurements also varies with different clinicians. To overcome
these problems with manual analysis, the objective of this survey is to introduce a method to
automatically analyze the ultrasound images of the eye. Automatic analysis of this disease is much
more effective than manual analysis.
Survey: Multipath routing for Wireless Sensor NetworkEditor IJMTER
Reliability is playing very vital role in some application of Wireless Sensor Networks
and multipath routing is one of the ways to increase the probability of reliability. More over energy
consumption is constraint. In this paper, we provide a survey of the state-of-the-art of proposed
multipath routing algorithm for Wireless Sensor Networks. We study the design, analyze the tradeoff
of each design, and overview several presenting algorithms.
Step up DC-DC Impedance source network based PMDC Motor DriveEditor IJMTER
This paper is devoted to the Quasi Z source network based DC Drive. The cascaded
(two-stage) Quasi Z Source network could be derived by the adding of one diode, one inductor,
and two capacitors to the traditional quasi-Z-source inverter The proposed cascaded qZSI inherits all
the advantages of the traditional solution (voltage boost and buck functions in a single stage,
continuous input current, and improved reliability). Moreover, as compared to the conventional qZSI,
the proposed solution reduces the shoot-through duty cycle by over 30% at the same voltage boost
factor. Theoretical analysis of the two-stage qZSI in the shoot-through and non-shoot-through
operating modes is described. The proposed and traditional qZSI-networks are compared. A
prototype of a Quasi Z Source network based DC Drive was built to verify the theoretical
assumptions. The experimental results are presented and analyzed.
SPIRITUAL PERSPECTIVE OF AUROBINDO GHOSH’S PHILOSOPHY IN TODAY’S EDUCATIONEditor IJMTER
The paper reflects the spiritual philosophy of Aurobindo Ghosh which is helpful in today’s
education. In 19th century he wrote about spirituality, in accordance with that it is a core and vital part
of today’s education. It is very much essential for today’s kid. Here I propose the overview of that
philosophy.At the utmost regeneration of those values in today’s generation is the great deal with
education system. To develop the values and spiritual education in the youngers is the great moto of
mine. It is the materialistic world and without value redefinition among them is the harder task but not
difficult.
Software Quality Analysis Using Mutation Testing SchemeEditor IJMTER
The software test coverage is used measure the safety measures. The safety critical analysis is
carried out for the source code designed in Java language. Testing provides a primary means for
assuring software in safety-critical systems. To demonstrate, particularly to a certification authority, that
sufficient testing has been performed, it is necessary to achieve the test coverage levels recommended or
mandated by safety standards and industry guidelines. Mutation testing provides an alternative or
complementary method of measuring test sufficiency, but has not been widely adopted in the safetycritical industry. The system provides an empirical evaluation of the application of mutation testing to
airborne software systems which have already satisfied the coverage requirements for certification.
The system mutation testing to safety-critical software developed using high-integrity subsets of
C and Ada, identify the most effective mutant types and analyze the root causes of failures in test cases.
Mutation testing could be effective where traditional structural coverage analysis and manual peer
review have failed. They also show that several testing issues have origins beyond the test activity and
this suggests improvements to the requirements definition and coding process. The system also
examines the relationship between program characteristics and mutation survival and considers how
program size can provide a means for targeting test areas most likely to have dormant faults. Industry
feedback is also provided, particularly on how mutation testing can be integrated into a typical
verification life cycle of airborne software. The system also covers the safety and criticality levels of
Java source code.
Software Defect Prediction Using Local and Global AnalysisEditor IJMTER
The software defect factors are used to measure the quality of the software. The software
effort estimation is used to measure the effort required for the software development process. The defect
factor makes an impact on the software development effort. Software development and cost factors are
also decided with reference to the defect and effort factors. The software defects are predicted with
reference to the module information. Module link information are used in the effort estimation process.
Data mining techniques are used in the software analysis process. Clustering techniques are used
in the property grouping process. Rule mining methods are used to learn rules from clustered data
values. The “WHERE” clustering scheme and “WHICH” rule mining scheme are used in the defect
prediction and effort estimation process. The system uses the module information for the defect
prediction and effort estimation process.
The proposed system is designed to improve the defect prediction and effort estimation process.
The Single Objective Genetic Algorithm (SOGA) is used in the clustering process. The rule learning
operations are carried out sing the Apriori algorithm. The system improves the cluster accuracy levels.
The defect prediction and effort estimation accuracy is also improved by the system. The system is
developed using the Java language and Oracle relation database environment.
Software Cost Estimation Using Clustering and Ranking SchemeEditor IJMTER
Software cost estimation is an important task in the software design and development process.
Planning and budgeting tasks are carried out with reference to the software cost values. A variety of
software properties are used in the cost estimation process. Hardware, products, technology and
methodology factors are used in the cost estimation process. The software cost estimation quality is
measured with reference to the accuracy levels.
Software cost estimation is carried out using three types of techniques. They are regression based
model, anology based model and machine learning model. Each model has a set of technique for the
software cost estimation process. 11 cost estimation techniques fewer than 3 different categories are
used in the system. The Attribute Relational File Format (ARFF) is used maintain the software product
property values. The ARFF file is used as the main input for the system.
The proposed system is designed to perform the clustering and ranking of software cost
estimation methods. Non overlapped clustering technique is enhanced with optimal centroid estimation
mechanism. The system improves the clustering and ranking process accuracy. The system produces
efficient ranking results on software cost estimation methods.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
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Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Reconfigurable CORDIC Low-Power Implementation of Complex Signal Processing for Reducing Power Dissipation
1. Scientific Journal Impact Factor (SJIF): 1.711
International Journal of Modern Trends in Engineering
and Research
www.ijmter.com
@IJMTER-2014, All rights Reserved 291
e-ISSN: 2349-9745
p-ISSN: 2393-8161
Reconfigurable CORDIC Low-Power Implementation of Complex
Signal Processing for Reducing Power Dissipation
K.Srinivasan1
, S.Sathyamoorthy2
II-M.E(CS)1
, AP / ECE2
, Dhanalakshmi Srinivasan Engineering College, Perambalur.
Abstract— In recent years, CORDIC algorithms has been used extensively for various image processing
system& biomedical applications. By using CORDIC algorithm we can able to reducing the number of
iteration to process the image in the system. Low power design is to be challenging process during system
operations. Previous approaches scope to minimize the power consumption without image quality
consideration. In this paper CORDIC Based Low Power DCT iterations process equally based upon their
image quality. An hardware implementation of ROM & control logic circuit to require large hardware
space in this system. Look-ahead CORDIC Approach is used to finish the iteration at one time. When
reducing hardware area & reducing number of iterations for maximize battery lifetime. This idea used to
achieve the low power design of image and video compression application
Index Terms—CO-ordinate Rotation Digital Computer(CORDIC), look-ahead, datapaths, Low-power,
Discrete Cosine Transform(DCT)
I. INTRODUCTION
With the explosive growth of multimedia system services running on moveable application, the demand
for low-power implementations of advanced signal process algorithms is enormously increasing. the
foremost vital a part of multimedia system systems square measure the applications involving image and
video process, that square measure terribly computationally intensive and so ought to be enforced with
low price due to the restricted battery period of time of moveable devices. several previous analysis efforts
square measure targeted on reducing power dissipation of image and video applications. Especially, low-
power style of separate trigonometric function rework (DCT) has been of specific interest, since DCT is
one amongst the foremost computationally intensive operations in video and compression, and it's wide
adopted in several standards like JPEG , MPEG, and H.264.
Since first planned in 1959 , coordinate rotation data processor system} (CORDIC) has been wide
accustomed calculate the pure mathematics functions in signal processing applications, like QR
decomposition, quick Fourier rework, singular price decomposition then on. Since CORDIC will be
merely enforced with the unvaried operations of additives and shifts, it's been wide used for the number
less low-power DCT architectures. several previous analysis works centered on reducing the hardware
quality of DCT like distribute arithmetic (DA)-based DCT and multiple constant multiplication (MCM)-
based approach. though bit-serial DA-based approach offers an everyday and straightforward DCT design,
massive hardware space is required for bit-parallel operations owing to further ROMs and management
logics. MCM-based DCT will be merely enforced with a smaller variety of shift-and-add operations,
however, to create a trade-off between the image quality and computation energy, the computation sharing
in numerous knowledge ways ought to be utterly re-considered. For the low-power CORDIC-based DCT
design conferred in knowledge correlations between neighboring pixels area unit with efficiency
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accustomed skip the interior CORDIC iterations. Approximation technique or incorporating compensation
steps into the division is additionally exploited to scale back the ability consumption of CORDIC-based
DCT design. Most of the previous analysis works area unit in the main centered on reducing the amount
of arithmetic units; the inherent knowledge priorities in DCT coefficients, however, haven't been exploited
within the CORDIC-based DCT.
In DCT, all the computations don't seem to be equally necessary in generating the frequency domain
outputs (DCT coefficients). In alternative words, a number of the computations in DCT area unit important
for determinant the output image quality, whereas others play comparatively minor roles. This attention-
grabbing property is wont to offer the correct trade off between the output image quality and power
dissipations. during this paper, we have a tendency to gift a low-power CORDIC-based DCT design,
wherever the necessary variations among the DCT coefficients area unit with efficiency exploited to
realize the facility savings minimum image quality degradation. to use the priority-based processing, look
ahead CORDIC architectures area unit adopted to beat the inherent data-dependencies in the traditional
CORDIC design. Thus, the amount of CORDIC iterations is dynamically controlled considering the
importance of DCT coefficients by that appreciable power savings is achieved.
The rest of this paper is organized as follows. the fundamentals of CORDIC rule and also the typical
CORDIC-based DCT area unit bestowed in Section II. The planned low-power CORDIC-based DCT
design and its hardware implementation area unit bestowed in Section III. supported the planned DCT
design, a reconfigurable CORDIC-based DCT is bestowed in Section IV. Finally, conclusions area unit
drawn in Section V.
II. SYSTEM MODEL
A. CORDIC Architecture
The basic principal of CORDIC is to iteratively rotate a vector using a rotation matrix, which is
represented as follows:
ݔ
ݕ
ݖ
൩ =
ݔିଵିߪ2ଵି
ݕିଵ
ݕିଵ + ߪ2ଵି
ݔିଵ
ݖିଵ − ߪߙ
where x and y are the vector coordinate components of x and y axes, respectively, i is the i th iteration
step, ߪ is the sign-bit that can be +1 or −1 indicating the direction of the vector rotation, z is the
accumulated rotation angle, and α is the predefined angle value of each micro rotation step, In the
CORDIC architecture, the amplitude and argument of a given vector can be calculated using the vectoring
mode, while the sine and cosine values of the given angle are obtained with the rotation mode.
1) Look-ahead CORDIC Approach: Within the CORDIC equation shown , to calculate the output of
this stage, the results from the previous stage iterations ought to be computed initial. These
knowledge dependencies square measure the most performance bottleneck within the typical
CORDIC hardware. to induce over the information dependencies, look-ahead CORDIC is
developed, wherever look-ahead implies that variety of CORDIC iterations may be computed
ahead to complete the iterations at just one occasion. associate degree example of four-iteration
step look-ahead CORDIC. it's noteworthy that if the sign-bits square measure proverbial ahead,
the subsequent stage iterations may be directly computed exploitation the input vectors of this stage
iteration while not computing the intermediate results.
2) Scale-Factor in CORDIC Operations: In the CORDIC operation, the magnitude of the rotated
vector is scaled and accumulated after every iteration according to the following equation:
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ܭ =
1
ඥ1 + 2ଶ(ଵି)
B. CORDIC-Based DCT Architecture
The 2-D DCT process is decomposed into an 1-D DCT (row DCT) followed by another 1-D DCT (column
DCT), which is expressed as the following equation
ܻ = ܶܶݔ்
= ܶ(ܶݔ்
)்
where x and Y are 8 × 8 size of image data matrix and 2-D DCT transformed output matrix,
respectively. T is the 8 × 8 1-D DCT basis matrix.
x X=xcos(ɵ) +ysin(ɵ)
y Y=xsin(ɵ)+ycos(ɵ)
After 2-D DCT operation, the computer file in house domain is remodelled to the frequency domain,
that is that the eight × eight block of sixty four DCT coefficients shown in Fig. 4. Here, as DCT has the
signal compaction property, the signal energy of the output knowledge (DCT coefficients) is generally
targeting many low-frequency elements, whereas the opposite higher frequency elements square measure
related to tiny signal energy. The high-frequency DCT coefficients become even smaller once the division
step [5], which implies that the low-frequency elements (DC) square measure a lot of sensitive to human
eyes than high-frequency elements.
The main plan during this paper is predicated on the actual fact that low-frequency DCT coefficients
square measure comparatively a lot of necessary than high-frequency coefficients. Our CORDIC-based
DCT design is intended considering the importance differences between the low and high-frequency DCT
coefficients. Generally, because the a lot of variety of iterations is performed in CORDIC, the a lot of
correct results square measure obtained. There-fore, within the projected DCT design, a bigger variety of
CORDIC iterations square measure allotted to come up with the low-frequency DCT coefficients, whereas
the comparatively smaller variety of iterations square measure used for the high-frequency elements. the
quantity of CORDIC iterations is judiciously designated specified the image quality degradation owing to
the smaller iterations may be reduced. elaborate explanations on the DCT hardware are conferred within
the following sections.
CORDIC
Algorithm
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III. PRIORITY-BASED LOW-POWER DCT ARCHITECTURE USING LOOKAHEAD
CORDIC APPROACH
A. Data Priority Considered Look-ahead CORDIC Architecture
In the typical CORDIC structure , because of the crossing-data path, ever-changing the quantity of
iterations for 2 separate CORDIC datapaths isn't possible. To assign totally different variety of iterations
to the 2 CORDIC datapaths, we tend to adopt the look-ahead CORDIC approach within the projected
DCT design.
Assuming that if the CORDIC results need four iterations for x whereas 3 iterations square measure
required for y, the look-ahead CORDIC equation for each results is expressed as follows, which
suggests that we are able to single.
The distinction between the standard crossing CORDIC design and therefore the look-ahead-based
approach. once the look-ahead approach is applied to the CORDIC design, the quantity of iterations is
simply controlled as all the inner datapath become freelance
In the projected CORDIC-based DCT design, wherever a unique variety of iterations square measure
allotted for generating DCT coefficients, the quantity of iterations ought to be rigorously set to attenuate
the error between the required input angle and also the corresponding accumulated angle. Table I shows
the iterations dead at i th stages and also the corresponding rotation direction σ (sign-bits). for instance, to
rotate the vector by π/16, solely the i th iterations (i = zero, 1, 3, 10) square measure dead and also the
remainder of the iterations is skipped for power savings.
In our DCT, the iterations to be skipped square measure rigorously elite specified the error between
the required angle and also the corresponding accumulated angle doesn't exceed zero.004 for all the given
angles. the quantity of CORDIC iterations for combination accustomed derive look-ahead CORDIC
algorithmic program is set mistreatment package modeling method bestowed in Section III-C.
As mentioned in Section II-A2, the scale-factor is set per the quantity of the dead CORDIC iterations.
because the variety of iterations is thought ahead, the scale-factors square measure planned, that square
measure shown in Table II. within the table, the scale-factors square measure delineate as signed power
of 2 format, and also the quantization error of the scaling issue is below 10E −4.
One fascinating observation once the look-ahead approach is applied to CORDIC is that removing
high shift-terms has the similar impact with the look-ahead CORDIC exploitation less variety of iterations.
as an example, if the CORDIC rotation with π/16 is dead exploitation 3 iterations (i = 0, 1, 3). Please note
that the amount of CORDIC iterations are often merely controlled by removing the high shift-terms.
B. Proposed Low-Power CORDIC-Based DCT Architecture
As mentioned within the last a part of Section III-A, considering the information priorities in DCT
constant, high shift-term of the look-ahead CORDIC are often fastidiously removed, that has constant
impact with the less variety of CORDIC iterations. as a result of the less variety of CORDIC iterations
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means that the CORDIC with low procedure complexness, a low-power CORDIC-based DCT design are
often derived and its careful implementation is as follows.
Inside the CORDIC module, the look-ahead CORDIC comes exploitation the parameters. The scale-
factors also are such that. associate example of the look-ahead CORDIC formula for 7π/16 rotation and
also the corresponding scale-factors square measure given within the equations shown. to scale back the
amount of iterations, the high shift-terms square measure removed as given in Section III-A. we have a
tendency to any scale back the reduced parts considering the information priorities in DCT coefficients.
In the projected hardware design, all the shift parts for every of look-ahead CORDIC formula and also
the scale-factors square measure precomputed exploitation the look-ahead CORDIC equations. within the
numbers within the circle represent the shift operation, and also the black color chart means that the 2’s
complement components of the shifted element, that square measure used for calculate operations. The
line represents the omitted computations, thus, the 2 ends up in look-ahead CORDIC modules have the
various variety of terms, that results in power savings as a result of the smaller variety of iterations.
C. Experimental Results of the Proposed Low-Power CORDIC-Based DCT Architecture
In this section, the experimental results of the projected CORDIC-based DCT design are given. First,
the quantity of CORDIC iterations is determined in line with the target PSNR of thirty one.5 dB, that is
that the average PSNR obtained mistreatment 9 benchmark pictures listed in Table IV. PSNRs of the
benchmark pictures are obtained mistreatment the subsequent equation
PSNR = 20. logଵ(
255
√MSE
)
ܧܵܯ =
1
݉݊
[ܫ(,ݔ ݕ) − ܭ(,ݔ ݕ)]ଶ
ିଵ
௬ୀ
ିଵ
௫ୀ
where I is m × n size of original image, and K is the reconstructed image.
For comparisons, varied DCT architectures like DA-based DCT, MCM, CORDIC-based DCT, and
CORDIC-based Loeffler DCT, are enforced mistreatment 0.13 µm CMOS galvanic cell library. The
enforced 2-D DCT is given with a line in Fig. 2, and Table III shows the implementation results. within
the table, power consumptions for various DCT architectures are measured mistreatment nanosim with a
hundred rate clock cycles, 1.2 V provide voltage over 500 input vectors are wont to acquire the typical
power. Compared with the DA-based design, the projected DCT shows 38.1% of space and pure gold
power savings. Compared with the MCM-based DCT , the projected DCT shows comparable power
consumption and 100 percent smaller space with a minor image quality degradation of 0.04 dB as a result
of a number of the upper order shift-terms in CORDIC iterations will be removed considering the
importance differences of DCT coefficients, our projected DCT design shows all-time low gate count and
power consumption compared with different CORDIC-based architectures. Especially, the projected DCT
design shows 21.87% of power savings compared to the CORDIC-based Loeffler DCT with even higher
PSNR results.
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IV. RECONFIGURABLE CORDIC-BASED DCT ARCHITECTURE
A. Proposed Reconfigurable Low-Power CORDIC-Based DCT Architecture
Using the low-power DCT design bestowed within the previous section, to additional cut back the
facility consumption at the expense of a minor image quality degradation we have a tendency to propose
a reconfigurable CORDIC-based DCT design during this section. many trade-off modes square measure
bestowed, and therefore the projected reconfigurable design will dynamically modification the CORDIC
iterations to adaptively trade off the computation energy for the image quality within the same hardware.
Generally, within the look-ahead CORDIC, the shift-terms for scheming low-frequency DCT
coefficients (terms for scheming X (0), X (1) in (8)) square measure a lot of vital than the shift-terms for
scheming high-frequency coefficients. in addition, among the shift-terms in one look-ahead CORDIC
equation, the foremost vital terms square measure low shift-terms whereas the comparatively minor terms
square measure high shift-terms. to save lots of the computation power at the expense of minimum image
quality degradation, first, the smallest amount vital shift-term in X(7) is removed supported Greedy
algorithmic program. Again, we have a tendency to explore for succeeding least vital shift-term to cancel
the computation. As we have a tendency to repeat the method, the a lot of range of shift-terms square
measure removed, which suggests that the computation power is reduced with minimum image quality
degradation.
With the approach shown in Fig. 7, we have a tendency to propose three modes of trade-off levels:
traditional mode, and modes one and a couple of. As we have a tendency to visit the upper trade-off levels
(sacrificing the image quality in favor of lower power), the quantity of shift-terms composing look-ahead
CORDIC equations is reduced. Table IV shows the PSNR results of the benchmark pictures for 3 trade-
off levels. The image quality constraints for traditional mode, mode 1, and mode two area unit geared
toward the common PSNR of 31.5, 30, and 27 dB, severally, for 9 benchmark pictures. the quantity of
trade-off modes and therefore the minimum allowable PSNRs may be modified in line with the user’s
selection.
The number of shift-terms in the look-ahead CORDIC equation and the scaling factors for three different
modes of operations. As an example, to calculate
ܺଷగ ଵ∗⁄ = (1 − 2ିସ)ݔ + (−2ିଵ
− 2ିଷ)ݕ
ܺగ ଵశ⁄ = (1 + 2ିଵ)ݔ + (2ିଶ
)ݕ
B. Hardware Implementation of the Reconfigurable DCT and Experimental Results
The image quality and machine energy trade-off approach projected within the previous section may
be realized as a reconfigurable hardware victimization the DCT design shown. At traditional mode of
operation, the low-power DCT design in Section III-B is employed.
For different trade-off modes, the projected DCT design may be dynamically reconfigured by merely
dynamical the management signal ф to trade-off minor image quality for consumption energy. Once a
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trade-off mode is decided, the management signal ф controls the turnoff gate arrays for of the CORDIC
equations terms & the scaling terms.
The power consumption is measured with nanosim with 100-MHz clock cycles, 1.2 V offer voltage.
The PSNR within the Table V shows the common PSNR of nine benchmark pictures. As shown within
the table, the projected design offers vital power savings as image quality decreases. Compared with the
traditional mode, mode two provides 38.73% of power savings with the image quality degradation.
Compared with the CORDIC-based Loeffler DCT that was shown in Table III, the projected design shows
45.3% of power savings at mode one at the expense of 0.52-dB image quality degradation. At exchange
level two, the projected DCT design achieves up to 59.5% of power savings compared with the standard
CORDIC-based DCT with appreciable image quality degradations.
V. PERFORMANCE RESULTS
In this section we present a set of performances results, This method reduces the total computation
power energy. The proposed multiplier less CORDIC-based DCT architecture produces high throughput
and is easy to implement in VLSI.
In Fig A & B shows that we enter the value in format of binary number in Force Constant Value
Fig.A Assigning of the input value to determine angle value
Fig.B Enter the input value in Force Constant Value
There will be the input value from in1[3:0] to in8[3:0] in Simulate Behavioral Window. The binary
value assign in the Force Constant Value.
The best approach of CORDIC algorithm, it can be concluded that the propose algorithm is more
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efficient than state-of-the-art CORDIC algorithm. In Fig C shows that the output value of the input data
applied in it
We don’t consider small varied value appeared during the time of iterations with CORDIC
algorithms & assign the intermediate value in between input value and the output value. Coding
efficiency using different accuracy both in rotation angle approximation of the rotators and the bit
accuracy of the adders in butterfly operators and rotators) for various DCT-based applications.
It has a much shorter latency which maintaining high image quality and minimize hardware complexity
that simultaneously satisfies low-energy requirements
Fig C Output appear on the screen
VI. CONCLUSIONS
In this paper We using this CORDIC algorithm with DCT to minimize the number of iterations based
upon the image quality and reducing hardware complexity present in the system.
The data correlation used to decrease the internal iteration between neighboring pixels in the images.
Reconfigurable CORDIC Low Power using DCT method can effectively processed to achieve power
saving in this system. In this method to achieve power consumption without any image degradation.
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