The document describes the design and implementation of a non-restoring reversible divider circuit using quantum-dot cellular automata (QCA). Key points: 1) A non-restoring divider circuit was designed using Feynman and Haghparast gates in a reversible logic approach to minimize quantum cost and garbage outputs. 2) The divider circuit was synthesized and implemented in QCADesigner, achieving a cell complexity of 269 and area of 0.54 μm2. 3) The proposed reversible divider design was shown to have lower quantum cost, fewer garbage outputs, and gates than previous non-reversible divider designs.

1. Implementation of Non-restoring
Reversible Divider Using a Quantum-Dot
Cellular Automata
Ritesh Singh, Neeraj Kumar Misra and Bandan Bhoi
Abstract The CMOS-based integrated circuit may scale down to nanometer range.
The primary challenge is to further downscale the device and high-energy dissi-
pation. Reversible logic does not dissipate energy and no information loss. In this
way, the state-of-the-art technology such as QCA was forced toward high-speed
computing with negligible energy dissipation in the physical foreground. This work
targets the design of non-restoring reversible divider circuit and its implementation
in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block
construction and also show the QCA implementation having cost-efficient
approach. Further, the divider circuit has synthesized with FG and HNG gates
and QCA implementation. This divider circuit inherits many benefits such as fewer
garbage outputs, reduce quantum cost are achieved, and also reduced QCA prim-
itives can be improved by using efficient QCA layout scheme. Simulation inves-
tigations have been verified by QCA Designer. The proposed non-restoring divider
also compares the reversible metrics results with some of other existing works.
Keywords Quantum-dot cellular automata ⋅ Nanoelectronics ⋅ Clocking
Reversible computing ⋅ High-speed nanoelectronics
R. Singh ⋅ N. K. Misra
Department of Electronics Engineering, Institute of Engineering and Technology,
Lucknow 226021, India
e-mail: ritesh.singh089@gmail.com
N. K. Misra (✉)
Department of Electronics and Communication Engineering,
Bharat Institute of Engineering and Technology, Hyderabad 501510, India
e-mail: neeraj.mishra@ietlucknow.ac.in
B. Bhoi
Departement of Electronics and Telecommunication, Veer Surendra Sai University
of Technology, Burla 768018, India
e-mail: bkbhoi_etc@vssut.ac.in
© Springer Nature Singapore Pte Ltd. 2019
H. S. Behera et al. (eds.), Computational Intelligence in Data Mining,
Advances in Intelligent Systems and Computing 711,
https://doi.org/10.1007/978-981-10-8055-5_41
459

2. 1 Introduction
Due to the increased density of the chip with high-energy dissipation, the chip
design has become complex and faces lots of challenges [1]. The reversible logic
circuit seems to tackle these difficulties such as no information loss, energy-free
computation, and application of quantum computing [2]. This synthesis approach is
an emerging area of the domain because it recovered input information from the
output information. Reversible gates have a bijective mapping from the input to the
output vectors and essential of balanced inputs and outputs. Reversible circuits
are necessary of feedback free, fan-out free, and no loops [3]. Reversible circuit
has same inputs and outputs, and there are restricted criteria of balanced. If
non-balanced criteria exist in the reversible circuit, then garbage output is required
to be balanced. The standard design of the reversible logic circuit is to explicit its
figure of merits such as quantum cost, delay, garbage outputs, and ancilla inputs [4].
The construction of a gate or a circuit is essential for low figure of merits belonging
to the efficient quantum computing regime. In focus on reversible logic, two criteria
exist such as logical reversibility and physical reversibility [5]. In the logic
reversibility, a one-to-one mapping is established. Physical reversibility computes
the information without the energy dissipation as the second level of criteria. These
two rules are necessary for reversible circuit design.
QCA is a prominent technology that employs nanometric scale level to perform
logic computing [6]. QCA technology is focused on a concept that position of
electron is possible by Coulomb repulsion, whereas CMOS device required voltage
for computation [7]. The computing advantages are high density, high speed, and
low power. QCA design has always preferred the lower value of primitives such as
latency, area usages, and complexity [8]. The information such as binary ‘0’ and ‘1’
is stored by polarization value of the cell, and clock zones achieve flow of infor-
mation. QCA design interacts the cells with the nearest neighbor cells, and polar-
ization changes to stored information. QCA was first originated by Lent and
implemented in the physical foreground in the year 1997 and proves the physical
existence possible in nanoelectronics area [9].
The divider is the popular operation that is used mostly in arithmetic and logic
unit and central processing units [10]. The proposed non-restoring divider circuits
are better than the prior circuits in the sense of the architecture complexity. In terms
of reversible figure of metrics, this optimization is considered regarding a number
of inputs and outputs, the number of garbage output (GO), constant input (CI),
quantum cost (QC), and the count of one and two-qubit gates [11]. This work
targets to design toward non-restoring divider based on reversible technique. The
design of non-restoring divider consists of two blocks such as FG and HNG gates.
The individual blocks are tested in QCADesigner tool. Further, the cascaded-based
approach is to design the higher order non-restoring divider. The design of
non-restoring divider is a target on a single layer of QCA technology. The proposed
single-layer design of the non-restoring divider in QCA has better primitives’
results based on a simulation study. The proposed design claims the lower area and
460 R. Singh et al.

3. high computation speed as compared to prior work. QCADesigner tool was adopted
to simulation and verification of result in the physical foreground. In addition, some
improvement is made in the primitives’ results based on QCA design.
The following are the attempts of the proposed work:
• We presented a compact non-restoring divider which is adopted a reversible
approach. The design has been achieved by utilizing existing FG and HNG
gates.
• We synthesize non-restoring block in QCADesigner which works on the prin-
ciple of Columbia interaction. The achievement of this implementation such as
complexity, area, and latency is pretty good and suitable for nanoelectronics
application.
This work is organized in the following sections: Sect. 2 deals with the neces-
sary background related to QCA technology to understand. Section 3 provides a
necessary existing work related to the non-restoring divider. This section also deals
with an existing work with its pros and cons. Section 5 details the architecture,
including the QCA design and explication of results. Section 7 provides the
comparative results based on prior work, and Sect. 8 discusses their conclusion.
2 QCA Concept
QCA is established on the four quantum dots in which maximum distance settles
the two electrons [12]. A polarization outline in the cell is presented in Fig. 1a. The
two polarizations are shown as P = −1, i.e., binary ‘0,’ and P = +1, i.e., binary ‘1.’
The activity of cell is changed due to the Coulombic interaction between cells.
Majority gate and inverter are the essential gates that are devoted to building any
circuits, which are shown in Fig. 1b, 1c respectively. The two same logic infor-
mation is transferred into two output nodes that are shown in Fig. 1d. Normally,
QCA cells are provided by four-phase clock. The four-phase clock is known as a
switch, hold, release, and relax as presented in Fig. 1e. The clock zones provide the
information flow in cells. The simple architecture of majority gate in experimental
view is drawn in Fig. 1f. The simple QCA cell architecture is shown in Fig. 1g.
3 Preliminary Work
Several approaches have been reviewed in the literature to achieve restoring and
non-restoring divider designs[13–18]. In the existing divider [16] based on
non-restoring and restoring, there is more computing QCA metrics. However, the
designs have attempted in non-reversible approach. Ali Bolhassani et al. presented
the reversible divider-based different modules [10]. The modules used in the design
Implementation of Non-restoring Reversible Divider … 461

4. are a multiplexer, left-shift register, and parallel adder/subtraction. All the modules
are cascaded to meet the design requirement of the divider. These designs are more
complex and high reversible figure of metric regarding gate count, garbage output,
and quantum cost. These designs of 1-bit divider utilize CI of 19, GO of 26, and QC
of 90, whereas n-bit divider uses (10n + 9) CI, (11n + 15) GO, and (52n + 38)
QC. These designs required more functional units. It is essential that the design
required a fewer functional unit with a large size of divider unit. We compared the
proposed design against the existing state-of-the-art design in [10]. Some other
works have been presented by T. N. Sasmal et al. [17]. These 2 × 2 and 3 × 3 type
non-restoring design was employed divider functionality to nanocomputing QCA
based. The 4 × 4 non-restoring divider in QCA design implementation can be
realized with 3180 number of cell count, the latency of 12, and area of 6.5 µm2
.
These designs are implemented in a single layer with coplanar technique.
Reversible synthesis of the divider, which is a popular technique in the recent area,
P= ‘-1’, Binary ‘0’ P= ‘+1’, Binary ‘1’
Input
Out 1
Out 2
Clock
0
Clock
1
Clock
2
Clock
3
Time
Signal Propagation
(a)
(c)
(d)
(f) (g)
(e)
(b)
QCA Cell with definite polarization
Electrometer
Input
A= ‘1’
Input
C= ‘1’
Input
B= ‘1’ Polarization = -1
(Binary 0)
Polarization = +1
(Binary 1)
1
2
3
4
Electron
Quantum-dot
Tunnel
Junction
Fig. 1 QCA concept: a Polarization, b majority gate architecture, c inverter architecture,
d fan-out, e clocking, f experiment of cell, g cell
462 R. Singh et al.

5. is studied in limited state-of-the-art designs. The noted work in this area reduced the
reversible figure of merits.
4 Popular Reversible Gates
Feynman gate (FG) and Haghparast (HNG) are the widely used gates in the design
of Ex-OR, multiplier, full adder, and full subtraction because of its low quantum
cost [3]. The following section shows these gate schematics, quantum equivalent,
and nanoscale implementation in QCA to prove the efficiency in the physical
foreground. We also presented these gates’ quantum circuit along with Toffoli gate
and elemental gate.
Feynman gate (FG): Inputs and outputs for a 2 × 2 FG are shown as follows:
Iv = A, Ov = A⊕B The schematic of FG and quantum circuit based on Toffoli gate is
presented in Fig. 2a. Feynman gate is used as “Ex-OR” and “repeating one bit”
with no junk outputs. Figure 2b, c presents the QCA implementation and the
corresponding simulation results of FG. The cell layout of FG has zero latency and
consists of 14 cell count and area of 0.02µm2
.
Haghparast gate: Inputs and outputs of HNG gate are presented in the schematic
diagram Fig. 3a. Figure 3b, c represents Toffoli gate block as well as elemental
quantum gate-based representation of the HNG gate. To realize the QCA imple-
mentation of HNG gate, cell complexity of 14, area of 0.02 µm2
, and zero latency
are needed as depicted in Fig. 4a. The simulation result of HNG is shown in
Fig. 4b.
Fig. 2 Feynman gate:
a Block diagram and its
quantum circuit, b QCA
implementation, c simulation
result
Implementation of Non-restoring Reversible Divider … 463

6. 5 The Proposed Architecture of Non-restoring Divider
By cascading the FG and HNG gates, the reversible non-restoring divider can
simply be constructed as shown in Fig. 5a. Reversible FG and HNG gates are
chosen to optimize the quantum cost of the design. The non-restoring cell is shown
in Fig. 5a. The Toffoli gate and elemental quantum gate-based representation of
non-restoring divider are presented in Fig. 5b, c, respectively. The design is con-
structed two outputs S and C. Recently, lots of existing work [13–18] have been
available showing the non-reversible synthesis approach.
Figure 5a shows the schematic representation of the one-by-one non-restoring
reversible divider. Note that, in order to obtain an output, individual block provides
the intermediate outputs. These intermediate outputs are applied to other blocks and
synthesize the required outputs of the divider. However, the individual block
architecture is a general solution for achieving the one-by-one non-restoring
Fig. 3 HNG gate: a Block diagram, b reversible circuit, c quantum circuit
Fig. 4 QCA implementation of HNG: a Layout, b simulation result
464 R. Singh et al.

7. divider. Therefore, the topology selection and the synthesis of the non-restoring
divider are the key points in the design construction.
The FG and HNG gates are used to design the two-by-two non-restoring
reversible divider. By using the 3 × FG and 4 × HNG gate, a new architecture of
non-restoring divider is designed which is drawn in Fig. 6. In the architecture, T is
used as a control input, A0, A1, A2 are used as inputs, R0, and R1 denote the
remainder, Q0 and Q1 represent the quotient. The synthesis of four inputs based on
non-restoring divider for the solution of divider construction is shown in Fig. 6.
The four inputs based on non-restoring divider are designed using 8 gate count
(4 × FG, and 4 × HNG), 28 quantum cost (4 × 1 + 4 × 6 = 28), and 13
garbage output.
Fig. 5 Proposed one-by-one non-restoring reversible divider a basic block, b Toffoli implemen-
tation, c elemental quantum gate diagram
FG
HNG
FG
HNG
FG
HNG
FG
HNG
Fig. 6 Proposed architecture of a two-by-two non-restoring reversible divider
Implementation of Non-restoring Reversible Divider … 465

8. 6 Implementation of Proposed Non-restoring Divider
in QCA Framework
Table 1 provides the results obtained in QCADesigner. In spite of simplicity, this
synthesis approach for non-restoring reversible divider succeeded its achieving cell
complexity of 269 and area of 0.54 µm2
by the layout design as shown in Fig. 7.
Most of the existing work [13–18] in non-restoring divider has emphasized on
non-reversible approach. The non-reversible approach often lacks recovered out-
puts from inputs and loss of inputs information as the outputs obtained. This work
introduces a one-by-one non-restoring reversible divider which utilizes a 7 quantum
cost and 3 garbage output. The important statistical features of QCA design used
were complexity, area, and latency. Latency was employed to perform clock delay.
Table 1 QCA primitives’ result in statistics as compared to existing works
Non-restoring divider Attempt Complexity Area (µm2
) Technique
Proposed R 268 0.54 Coplanar
[16] NR 235 0.35 Multilayer
[17] NR 60 0.08 Coplanar
[18] NR 147 0.27 Coplanar
Fig. 7 QCA implementation of two-by-two non-restoring reversible divider
466 R. Singh et al.

9. The robust design of non-restoring divider is that it used less statistical features for
fast computation and efficiency.
7 Comparison Result and Discussion
Most of the existing work has designed the non-reversible approach, whereas
existing work deals with the reversible technique. The present work deals with the
robust design approach of the divider. Such an efficient, simple, and unique design
model will successfully evaluate the behavior of a design which is established to be
most suitable for nanoelectronics application. The garbage outputs, quantum cost,
gate count, and ancilla inputs of design based on the quantum equivalent circuit of
the proposed design are compared through Table 2. This comparison result shows
the proposed reversible implementation of the non-restoring divider that is very
effective in quantum computing paradigm with very low quantum cost, fewer
garbage outputs, and gate count.
8 Conclusions
In this paper, a non-restoring reversible divider is realized on QCA. Design gates
for the non-restoring divider are presented in QCA in addition to the complete
design adopted in coplanar technique. Unique design as compared to existing
makes these cost-efficient approaches. Therefore, the less critical delay of the
non-restoring divider is very beneficial to reversible computing application. Thus,
the non-restoring adder is usually implemented as two-by-two that is used to
construct large size order of non-restoring adder. The study presented here shows
that this synthesis of the non-restoring divider is a less reversible figure of merit in
the sense of quantum computing framework. A simulation carried out on QCA-
Designer tool reveals that the proposed structure of non-restoring binary divider
outperformed the state-of-the-art designs and demonstrated promising ability
against nanoelectronics technology. Here, in this work, both the better primitive’s
Table 2 Comparison of statistics results with existing works
Designs R GC CI GO QC HC QE
New Yes 2 0 3 7 6α + 2β Yes
[10] Yes – 19 26 90 65α + 7β + 52δ No
[13] Yes – 21 29 111 59α + 67β + 33δ No
[14] Yes – 26 32 149 84α + 82β + 42δ No
[15] Yes – 28 41 104 91α + 98β + 50δ No
Note GC gate count, CI ancilla input, GO unwanted output, QC quantum cost, HC hardware
complexity, R reversible, NR non-reversible, QE quantum equivalent
Implementation of Non-restoring Reversible Divider … 467

10. results and correct simulation pattern of individual blocks have been achieved
simultaneously. The non-restoring divider can be used in many computing appli-
cation inside the ALU, microcontroller, and low power devices.
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