Parbhat Kangra is pursuing an M.Tech in Electrical Engineering from IIT Bombay, specializing in Electronic Systems. He completed his undergraduate degree from NIT Kurukshetra in Electronics and Communication Engineering in 2014 and his intermediate education from CBSE schools. His areas of interest include digital VLSI design, testing and verification, and analog VLSI design. For his M.Tech project, he is developing a new fault tolerant routing algorithm for network on chip architectures. He has experience with tools like NGSpice, Modelsim, and programming languages like VHDL, Verilog, C, C++ and Python. Parbhat has participated in various technical workshops and extracurricular activities, and held positions
vlsi projects using verilog code 2014-2015E2MATRIX
E2MATRIX Research Lab
Are you scratching your head to write your M Tech thesis?
Don’t know where to start and where to find the relevant matter on the topic?
We Provide Complete Thesis Help For M.Tech / Phd Studnets.
E2MATRIX deals with Thesis guidance and research work for M.Tech, PhD Students.
If you are looking for professional thesis guidance then of course you are at the right place. We have a best team of Technical Developers and professionals who specialize in developing and delivering best and authenticated work with an assurance of on time delivery.
Contact : +91 9041262727, 9779363902.
Email : support@e2matrix.com
Web : www.e2matrix.com
vlsi projects using verilog code 2014-2015E2MATRIX
E2MATRIX Research Lab
Are you scratching your head to write your M Tech thesis?
Don’t know where to start and where to find the relevant matter on the topic?
We Provide Complete Thesis Help For M.Tech / Phd Studnets.
E2MATRIX deals with Thesis guidance and research work for M.Tech, PhD Students.
If you are looking for professional thesis guidance then of course you are at the right place. We have a best team of Technical Developers and professionals who specialize in developing and delivering best and authenticated work with an assurance of on time delivery.
Contact : +91 9041262727, 9779363902.
Email : support@e2matrix.com
Web : www.e2matrix.com
Extracting a Rails Engine to a separated applicationJônatas Paganini
As a Rails Application grows, there is a need to decouple heavy systems from the monolithic applications. Several teams in different companies are doing the same: extracting (micro) services from their monolithic applications to give the engineering teams more flexibility to speed up the workflow.
From the separation of the business logic to the server's setup, every change should respect the zero-downtime approach.
This talk shares the automated steps and exercises we created to have a smooth transition to the new system.
I'll share the context of the tool that is automatically extracting an entire
rails engine from a project and moving it to a separate service.
Compering audio processing algorithms and evaluate the performance of the algorithm on GPU and CPU.
Analysis of Audio Processing Algorithm Effects:
Equalizer, Delay, Reverb, Compression.
In a school ERP system, all data are stored in one place. Therefore, all the data can be easily tracked down. A school ERP system can eliminate the collaboration between different departments. For more details visit the site https://web-school.in/
Extracting a Rails Engine to a separated applicationJônatas Paganini
As a Rails Application grows, there is a need to decouple heavy systems from the monolithic applications. Several teams in different companies are doing the same: extracting (micro) services from their monolithic applications to give the engineering teams more flexibility to speed up the workflow.
From the separation of the business logic to the server's setup, every change should respect the zero-downtime approach.
This talk shares the automated steps and exercises we created to have a smooth transition to the new system.
I'll share the context of the tool that is automatically extracting an entire
rails engine from a project and moving it to a separate service.
Compering audio processing algorithms and evaluate the performance of the algorithm on GPU and CPU.
Analysis of Audio Processing Algorithm Effects:
Equalizer, Delay, Reverb, Compression.
In a school ERP system, all data are stored in one place. Therefore, all the data can be easily tracked down. A school ERP system can eliminate the collaboration between different departments. For more details visit the site https://web-school.in/
Entando is a powerful and extensible open source, component-based, UI software platform that simplifies the end-to-end development of web, mobile and hybrid applications that leverage devices, data and services.
Abstractions and Directives for Adapting Wavefront Algorithms to Future Archi...inside-BigData.com
In this deck from PASC18, Robert Searles from the University of Delaware presents: Abstractions and Directives for Adapting Wavefront Algorithms to Future Architectures.
"Architectures are rapidly evolving, and exascale machines are expected to offer billion-way concurrency. We need to rethink algorithms, languages and programming models among other components in order to migrate large scale applications and explore parallelism on these machines. Although directive-based programming models allow programmers to worry less about programming and more about science, expressing complex parallel patterns in these models can be a daunting task especially when the goal is to match the performance that the hardware platforms can offer. One such pattern is wavefront. This paper extensively studies a wavefront-based miniapplication for Denovo, a production code for nuclear reactor modeling.
We parallelize the Koch-Baker-Alcouffe (KBA) parallel-wavefront sweep algorithm in the main kernel of Minisweep (the miniapplication) using CUDA, OpenMP and OpenACC. Our OpenACC implementation running on NVIDIA's next-generation Volta GPU boasts an 85.06x speedup over serial code, which is larger than CUDA's 83.72x speedup over the same serial implementation. Our experimental platform includes SummitDev, an ORNL representative architecture of the upcoming Summit supercomputer. Our parallelization effort across platforms also motivated us to define an abstract parallelism model that is architecture independent, with a goal of creating software abstractions that can be used by applications employing the wavefront sweep motif."
Watch the video: https://wp.me/p3RLHQ-iPU
Read the Full Paper: https://doi.org/10.1145/3218176.3218228
and
https://pasc18.pasc-conference.org/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
1. Parbhat Kangra 153070081
Electrical Engineering M.Tech.
IIT Bombay Male
Specialization: Electronic Systems DOB: 26 Sep 1992
Examination University Institute Year CPI / %
Post Graduation IIT Bombay IIT Bombay 2017 8.21
Undergraduate Specialization: Electronics & Communication
Graduation NIT Kurukshetra NIT Kurukshetra 2014 7.37
Intermediate/+2 CBSE Shiksha Bharti Vidyalay 2010 75.20
Matriculation CBSE Shiksha Bharti Vidyalay 2008 67.80
AREAS OF INTEREST
Digital VLSI Design, Testing and Verification, Analog VLSI Design, Embedded Systems
TECHNICAL SKILLS
• Tools: NGSpice, Modelsim, Xilinx, Noxim Simulator, GHDL, MATLAB, EAGLE, Code Composer Studio
• Languages: VHDL, Verilog, System C (HDL), C, C++, Python (Programming))
MAJOR PROJECTS
• M.Tech Project (Ongoing) (May 2016 - Present)
Title: Fault Tolerant Routing for Network on Chip(NoC) Architecture
Guide: Prof. Virendra Singh, IIT Bombay
Keywords: NoC, Packet, Deadlock, Livelock
Idea: Development of a new fault tolerant routing algorithm for NoC architecture
o Routing Algorithm should cover any number of link failures in the network
o This research work focuses on error free transmission of packets in the network
Ongoing and Future Work:
o Studied several design approach for reliable data delivery under faulty environment
o Deadlock and Livelock avoidance is to provided in the network
o Intra-router soft error is to be studied and dedicated hardware can be used
o Link-Level Fault Detection and Protection can be provided using hamming codes
• M.Tech Seminar (January - May 2016)
Title: Design Methodology and Research Approach for NoCs
Guide: Prof. Virendra Singh, IIT Bombay
o Studied several research challenges, and motivation for the design and corresponding approach
o Analysed different design constraints which should be considered during designing of NoC
o Timing-error-tolerant design methodology, parity routing, and packet chaining concepts were studied
• B.Tech Project (January - May 2014)
Title: Implementation of IEEE 754 Standard (FPU) on FPGA
Guide: Prof. Mohammad Arif, NIT Kurukshetra
o Implementation of 8-bit FPU on SPARTAN 3E FPGA using VHDL
o Arithmetic, logical, and shift, all 16 operations were implemented
RELEVANT COURSES
• VLSI Design • Testing and Verification of VLSI circuits
• VLSI Design Lab • CMOS Analog VLSI Design
• System Design • DSP Application
• Electronic System Design • DSP Implementation
• Foundation of VLSI CAD • Embedded System Design
COURSE PROJECTS
• Automatic Test Pattern Generator (ATPG) (Course: Testing and Verification)
o Implemented PODEM algorithm in C++ for combinational circuits
o Simulated for c17 benchmark and few other circuits written in Verilog
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2. • Design of Lift Group Control System (LGCS) (Course: VLSI Design Lab)
o Implemented in VHDL and Verilog, an elevator controller for 3 lifts in a 6 floor building
o Designed the controller for minimizing average waiting time of passengers
• Design of Router for NoC (Course: VLSI Design Lab)
o Implemented in Verilog and System C, a router that uses Distance Ordered Routing
o Synthesized the design and performed post synthesis simulation
• Design of Run Length Encoder (Course: VLSI Design Lab)
o A data compression circuit was implemented in Verilog using run length encoding
o It replaces repeated occurrences of a byte by the repeat count and the byte value
• Design of Greatest Common Divisor (Course: VLSI Design Lab)
o GCD of the two numbers was found using Stein’s algorithm with proper handshake signals
o Stein’s algorithm replaces division with arithmetic shifts, comparisons, and subtraction
o GCD result was verified using distinct set of numbers
• Design of Dadda and Wallace Multipliers (Course: VLSI Design)
o Implemented in VHDL for signed multiplication of two 8-bit numbers
o Carry select architecture for the final adder with square root stacking was used
• Design of folded cascode OpAmp with CMFB (Course: CMOS Analog VLSI Design)
o Designed a two stage folded cascode opamp in 180 nm CMOS technology in Ngspice
o Specification was 90 dB gain, 67 MHz UGB, 66◦
PM for a load capacitor of 10 pF and input common
mode range of 0.6 V for a supply voltage of 1.8V considering differential slew rate better than 20 V/uS
• Digital Tuner for Guitar (Course: DSP Implementation)
o Implemented in real time using Texas Instruments TMS320C5515 DSP processor board
o Silence Region Detection, FFT, Autocorrelation, and Peak Detection Blocks were used
TECHNICAL WORKSHOPS
• Industrial training on electronic relays at C&S Electric Limited, New Delhi (May - July 2013)
• Summer Training in Embedded Robotics at HP Educational Centre, Noida (June - July 2012)
• Workshops on robotics organized by EFY and Emanagineer at NIT Kurukshetra
POSITIONS OF RESPONSIBILITY
• Coordinator in Mood Indigo (December 2015)
o Organised 3 events as a coordinator of INFORMALS team,
o Sniffer Squad, Minute to win it, Segway racing
• Teaching Assistant
o Introduction to Electronics(EE112): Worked out few assignments and did invigilation duty
o VLSI Design(EE671): Responsible for evaluating assignments and answer scripts
EXTRA CURRICULAR
• 1st Prize in Battle of Bands competition at NIT Kurukshetra (February 2011)
• 2nd Prize in Instrumental solo competition at NIT Kurukshetra (February 2013)
• Participated in a Band Competition in PGCult at IIT Bombay (February 2016)
OTHER INTERESTS
• Appreciating Music, Playing Musical Instruments, Making Dubsmash, Martial Arts, Meditation, & Reiki
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