This document provides an overview of the Digital System Design and Labs course taught by Professor Ming Ouhyoung at National Taiwan University. The course covers digital logic design principles like Boolean algebra and finite state machines. Students learn to design combinational and sequential logic circuits using hardware description languages like VHDL. They also complete a digital design project implementing an integrated circuit using FPGAs or application-specific integrated circuits. The goals are for students to gain experience designing and implementing complex digital systems as engineers. On completing the course, students will be able to analyze, design, prototype, and communicate digital circuit designs.

1. Digital System Design and Labs
數位系統與實驗
歐陽明(Ming Ouhyoung)
Professor, Dept.of CSIE,
National Taiwan University

2. 課名: 數位系統與實驗 課號: CSIE 2344 授課: 歐陽明
英文課名:Digital System Design and Lab (選修, 2018/9 改)
• 大綱:
• Digital System Labs
• Introduction to Boolean Algebra and Digital System Design
• The Process of Design, Rapid Electronic System Prototyping
• Minimization of Boolean Function
• Combinational Circuits
• Programmable and Steering Logic
• Sequential Logic Design (Reverse Engineering and Forward Design)
• Finite State Machine Design, Hardware Description Languages
• Digital System Labs: Case Study (ALU design, Memory Control etc.)
•
• 教科書
C. H. Roth, Jr. and L. Kinney, Fundamentals of Logic Design, International
Edition, paper back.

3. Goals
1. Transform students into engineers, capable of
designing and implementing complex digital
systems.
2. Use a hardware description Language (VHDL)
3. Implement with multiple existing integrated
circuits
• PS: Course name in MIT: 6.111 Introductory Digital Systems
Laboratory

4. Objectives and Outcomes
On completion of this course, students will have
confidence in their abilities to conceive and carry out a
complex digital systems design project in a team of two
or three people. More broadly, they will be ready to
handle substantial, challenging design problems. In
particular, students will be able to:
1. explain the elements of digital system abstractions
such as digital logic,Boolean algebra, flip-flops and
finite-state machines (FSMs).

5. 2, design simple digital systems based on these digital
abstractions, and the "digital paradigm" including
discrete, sampled information.
3. use basic digital tools and devices such as digital
oscilloscopes, PALs, PROMs, and VHDL.
4. work in a design team that can propose, design,
successfully implement, and report on a digital circuit
design project.
5. communicate the purpose and results of a design
project in written and oral presentations.

7. Where is this course in the CSIE
course map?
(1) Circuits and Micro-Electronics (optional)
THEN
(2) Digital System Design and Laboratory
THEN
(3) Computer Architecture, or
(4) VLSI design, or (5) Embedded System Design

8. Digital vs. Analog Systems
• Difference
• How to bridge these two systems?

9. AD and DA converter

10. Expected capabilities for students
(see the demos!)
(1)Understand the Digital System Design
principles
(2) Can write a program for Reverse Engineering
(Read a circuit from the System Design, and
explain its function, by a program)
(3) Can write a program for Forward Design
(Read a finite automata or finite state machine,
then generate the circuits with logic gates)

11. Hardware Description Languages
1. VHDL (demo)
2. Verilog (demo)

12. State machines: Moore machine

13. State machines: Moore machine

14. State machines: Mealy machine

15. VHDL
• VHDL was originally developed at the request
of the U.S Department of Defense in order to
document the behavior of the ASICs that
supplier companies were including in
equipment.

16. VHDL
• The idea of being able to simulate the ASICs
from the information in this documentation
was so obviously attractive that logic
simulators were developed that could read
the VHDL files. The next step was the
development of logic synthesis tools that read
the VHDL, and output a definition of the
physical implementation of the circuit.

17. logic synthesis
In electronics, logic synthesis is a process by
which an abstract form of desired circuit
behavior, is turned into a design implementation
in terms of logic gates. Common examples of
this process include synthesis of HDLs,
including VHDL and Verilog. Some tools can
generate bitstreams for
programmable logic devices such
as PALs or FPGAs, while others target the
creation of ASICs. Logic synthesis is one aspect
of electronic design automation.

18. Combinational logic vs. Sequential
logic (with registers)
• A synchronous circuit consists of two kinds of
elements: registers and combinational logic.
Registers (usually implemented as D flip-flops)
synchronize the circuit's operation to the
edges of the clock signal, and are the only
elements in the circuit that have memory
properties. Combinational logic performs all
the logical functions in the circuit and it
typically consists of logic gates.

19. Combinational logic and Sequential
logic (example)

20. Reverse Engineering
Can write a program for Reverse Engineering
(Read a circuit from the System Design, and
explain its function, by a program)

21. Results (a finite state machine!)
Mealy machine vs Moore machine

22. • In the theory of computation, a Moore
machine is a finite-state machine whose
output values are determined solely by its
current state.

23. • In the theory of computation, a Mealy
machine is a finite-state machine whose
output values are determined both by its
current state and the current inputs.

24. Can write a program for Forward Design
(Read a finite automata or finite state machine,
then generate the circuits with logic gates)
Example: design a counter that can count from
1 to 5 (and input bits can overlap).

25. Results (a logic circuit design)

26. Two types of results of circuit Implementation
• (1) 電路板 (麵包板, breadboard) or FPGA (field-
programmable gate array)

27. Results of Implementation (II)
(可送台積電, 聯電製造)
(2) A chip (ASIC, application specific integrated
circuits)

28. That’s why you need the logic lab
in Dept. of CSIE!
To do the FPGA implementation with
breadboard, or chip deign
By writing programs (VHDL, Verilog etc.)!
(and you need debugging, also in hardware, to
be sure that your product is correct!)
THEN you need: logic analyzer (邏輯分析儀,
4GHz one, for example),

29. logic analyzer
• a laboratory test instrument designed to
display and evaluate digital signals. The device
works in a manner similar to the way that
an oscilloscope displays and facilitates the
analysis of analog signals.
• A logic analyzer allows engineers to design,
optimize, and debug the hardware in digital
systems, and can help technicians find and fix
problems in malfunctioning systems.

30. What is the cost of a product from
design to implementation?
(for a machine/a circuit)
• In terms of total time and money used

31. Design goals: constraints=
Design fees + manufacture+ support

32. Total Cost of Circuit/Chip Design
• Cd: design cost, shared by all products N
• Cm: manufacture cost
• Cs: field support cost, including relibility of
components, interconnection, servicing cost
• Solution: Early prototyping, Design for
testability, Programmability (like software
design, using VHDL, Verilog etc IEEE standards)

35. From design to implementation
to debug

36. Design considerations/constraints

37. Dynamic changes of hardware design

38. Radical change in logic design (Chap. 1.1)
(1) Automatic generation of logic circuits using
software tools.
(2) Versatile digital components (programmable,
FPGA, PLA--programmable logic array etc.)
(3) Design emphasis: shifting from detailed
implementation hardware to the software
specification.
Problems: software design, face same problems
in writing a program!

39. The elements of modern design
Representation, circuit technology,
rapid prototyping

40. Digital hardware systems

41. The art of design:
to design is to represent

42. Semiconductor theory:
Why TSMC needs neno tech.?
• (1) Can you explain the function of the
following CMOS inverter, in terms of
Vin (gate voltage), and how the CMOS will
work in terms of fundamental semi-conductor
theory (electron or hole flow)? What is the
cause of flow of electrons or holes?

43. Neno(meter) technology
• 1 Angstrom = 10 to the -10 meters
• 1 Nano-meter = 10 to the -9 meters,
so, 1 nenometer is equivalent to 10
Hydrogen atoms
TSMC : industry leading 20/28 nm (Q4 2015, 16
nm) semiconductor process technology
Collaborates with Fujitsu on 28 nm process

44. CMOS inverter physical layers

45. Semi-conductor theory II
(2) When the poly-silicon and diffusion layer
width is reduced by a factor of R, so are others.
Please answer what is the packing density
(gates/area)? power/gate, gate delay (speed) in
terms of R. Explain with simple explanations
using the following models, and make your own
assumptions.

46. Scaling assumptions
**Voltage scaled by R, oxide thickness (T0) scaled by R,
then device current is scaled by R,
Depletion region width scaled by R, increase the
substrate doping, NA, by R
To simplify the condition:
• Case 1: The source-drain voltage, the width, the length, the
source-drain current flow, and the oxide thickness are ALL
reduced by R.

47. CMOS inverter physical layers

48. Circuit theory
• Delay T is proportional to
Capacitor C and Impedance (Resistance) R
delay T = R*C
speed S is inversely proportional to T
R is proportional to length(L), and inversely
proportional to width(W) of resistor: L/W
C is proportional to area (A) divided by distance
(D)of two plates: A/D

49. Basic scaling properties
• Parameter scaling factor
Dimension L 1/R
W 1/R
t0 (Oxide thickness) 1/R
Doping concentration R
Voltage 1/R
Current 1/R
(current is proportional to W/L*V2/t0 )

50. The effect of scaling (k)
Packing density R2
Capacitance 1/R
Power/gate (VI) 1/R2
Chip power density 1
Gate delay, (CV/I) 1/R
Power/delay product 1/R3

51. Intro. VLSI: Carver Mead (Caltech)Lynn Conway (Xerox
Parc) 1980
CMOS inverter

52. CMOS inverter: black and white
representation

53. Transistors in row

54. Symmetrical arrangement of
transistors (FETs)

55. Basic design rule checking

56. Design rule checking

57. Some example of DRC's in IC design
include:
• Active to active spacing
• Well to well spacing
• Minimum channel length of the transistor
• Minimum metal width
• Metal to metal spacing
• Metal fill density (for processes using CMP)
• ESD and I/O rules
• Antenna effect

58. Rules for design rule checking:
basic rules

59. Four bit counter: with flip-flops

60. Toggle cell stick diagram

61. A counter layout

62. Gate array for four-input CMOS
NOR gates

63. PLA layout

64. Reverse engineering: guess what is
this?

65. Expected capabilities after this
course
• (1) Design (forward design)
• (2) Analysis (reverse engineering)
see the exam problem sets.
(3) Get to know how to build a chip or
computer, and the working environment of
chip/computer design companies.
(4) The world trend in hardware and
software integration.