Embedded Linux Conference 2020:
Linux on RISC-V with open source hardware and open source FPGA tools
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, the Reform laptop and more.
I will also talk about the importance of the open RISC-V instruction set and free software FPGA toolchains. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a SoC capable of running Linux.
Finally, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Linux on RISC-V with Open Hardware (ELC-E 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. I will highlight that OpenHW Group has adopted the PULP Ariane from ETH Zurich for its Core-V CVA64 implementation. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2020 and 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Want to run Linux with RISC-V on Open Source Hardware? This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
How to run Linux on RISC-V (FOSS North 2020)Drew Fustini
Title:
How to run Linux on RISC-V (with open hardware and open source FPGA tools)
Abstract:
Want to run Linux with RISC-V on Open Source Hardware?
This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge using only open source tools thanks to Project Trellis, yosys and nextpnr. I will explain what migen and LiteX are, and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux on VexRiscv.
In conclusion, I will explore the landscape of open source chip designprojects and the Linux-capable RISC-V silicon chips on horizon for 2020, and talk about my desire to collaborate on an affordable (<$100?) OSHW Linux RISC-V board.
Linux on RISC-V with Open Hardware (ELC-E 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. I will highlight that OpenHW Group has adopted the PULP Ariane from ETH Zurich for its Core-V CVA64 implementation. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2020 and 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Want to run Linux with RISC-V on Open Source Hardware? This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
How to run Linux on RISC-V (FOSS North 2020)Drew Fustini
Title:
How to run Linux on RISC-V (with open hardware and open source FPGA tools)
Abstract:
Want to run Linux with RISC-V on Open Source Hardware?
This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge using only open source tools thanks to Project Trellis, yosys and nextpnr. I will explain what migen and LiteX are, and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux on VexRiscv.
In conclusion, I will explore the landscape of open source chip designprojects and the Linux-capable RISC-V silicon chips on horizon for 2020, and talk about my desire to collaborate on an affordable (<$100?) OSHW Linux RISC-V board.
LAS16-106: GNU Toolchain Development LifecycleLinaro
LAS16-106: GNU Toolchain Development Lifecycle
Speakers: Ryan Arnold
Date: September 26, 2016
★ Session Description ★
This presentation will examine the lifecycle of toolchain development from inception of the micro-architecture, to development of the ISA, to delivery of OS enablement in FOSS projects, to adoption in Linux Distributions. It will examine the behaviors of successful silicon vendors as well as behaviors of vendors that struggle to get their platform fully enabled in the GNU/Linux OS.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-106
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-106/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
BKK16-100K1 George Grey, Linaro CEO Opening KeynoteLinaro
George Grey, Linaro CEO, gives the opening keynote on Monday morning. He will discuss Linaro’s activities across the ARM ecosystem from sensor devices to the data-center. New initiatives including end-to-end open source software platform solutions will be announced and demonstrated.
BKK16-310 The HiKey AOSP collaborative experience Linaro
An overview of collaborative effort done by Builds and Baselines, LMG, 96boards and HiKey landing team in getting HiKey integrated into AOSP. Covers work on the AOSP common.git branches, cross kernel/bootloader feature work that provides more form-factor like integration not commonly found on devboards, lessons learned, etc.
Slides for my presentation on RISC-V and open source chip design at PumpingStation1 hackerspace tonight https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
LAS16-106: GNU Toolchain Development LifecycleLinaro
LAS16-106: GNU Toolchain Development Lifecycle
Speakers: Ryan Arnold
Date: September 26, 2016
★ Session Description ★
This presentation will examine the lifecycle of toolchain development from inception of the micro-architecture, to development of the ISA, to delivery of OS enablement in FOSS projects, to adoption in Linux Distributions. It will examine the behaviors of successful silicon vendors as well as behaviors of vendors that struggle to get their platform fully enabled in the GNU/Linux OS.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-106
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-106/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
BKK16-100K1 George Grey, Linaro CEO Opening KeynoteLinaro
George Grey, Linaro CEO, gives the opening keynote on Monday morning. He will discuss Linaro’s activities across the ARM ecosystem from sensor devices to the data-center. New initiatives including end-to-end open source software platform solutions will be announced and demonstrated.
BKK16-310 The HiKey AOSP collaborative experience Linaro
An overview of collaborative effort done by Builds and Baselines, LMG, 96boards and HiKey landing team in getting HiKey integrated into AOSP. Covers work on the AOSP common.git branches, cross kernel/bootloader feature work that provides more form-factor like integration not commonly found on devboards, lessons learned, etc.
Slides for my presentation on RISC-V and open source chip design at PumpingStation1 hackerspace tonight https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Linux on RISC-V with Open Source Hardware (Open Source Summit Japan 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Google Slides link https://tinyurl.com/y6j8lfyz
Linux on Open Source Hardware with Open Source chip design (36c3)Drew Fustini
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
Presented at the 36th Chaos Communication Congress (36c3) in Leipzig, Germany:
https://fahrplan.events.ccc.de/congress/2019/Fahrplan/events/10549.html
Video: https://media.ccc.de/v/36c3-10549-linux_on_open_source_hardware_with_open_source_chip_design
YouTube: https://www.youtube.com/watch?v=mnOBTD9dgsg
Embedded Fest 2019. Wei Fu. Linux on RISC-V--Fedora and Firmware in practiceEmbeddedFest
Summarize Fedora on RISC-V development including the little history, current status and some simple steps describing how to run Fedora on QEMU,FPGA board or the SiFive RV64 development board. Meanwhile, provide the status of current Specs and firmware(OpenSBI/UEFI/uboot) for RISC-V and the kernel development status.
From Make 'n Tell at xHain hackerspace in Berlin, I introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the importance of free software FPGA tools.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
I finish by talking about how Fomu is a great FPGA board to get started with!
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
CPU Diversity is growing: POWER and RISC-V OpenISA are real option with FPGA, ASIC and Motherboard available next year
Which are Open Hardware Power Architecture real options? Microwatt and LibreSoc have samples of low power Open ISA Power chip. The Power Progress Community released the Prototypes of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. What happen around OpenPower Foundations with project like PowerPI and LibreBMC.
Open Source Hardware and Libre SiliconDrew Fustini
My Open Source Hardware and Libre Silicon talk for Penguicon 2017.
Open Source Hardware (OSHW) designs are made publicly available so that anyone can study, modify, distribute, make or sell designs or hardware based on that design. This talk will explore the shared values with Open Source software and the specifics of publishing a hardware project under an Open Source license.
It will include examples of Linux running on OSHW with projects like BeagleBone, CHIP, MinnowBoard and more. The role of the Open Source Hardware Association and annual Open Hardware Summit will also be discussed, along with important OSHW projects for scientific researchers.
There are exciting new developments within the last year for OSHW at the chip level. Projects like lowRISC, J-Core, OnChip and SiFive are working to produce true Open Source silicon processors. The FOSSi Foundation and LibreCores are helping to organize and promote this exciting new ecosystem.
Embedded Recipes 2019 - Linux on Open Source Hardware and Libre SiliconAnne Nicolas
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, Giant board and more. Looking at the benefits and challenges of designing Open Source Hardware for a Linux system, along with BeagleBoard.org’s experience of working with community, manufacturers, and distributors to create an Open Source Hardware platform. In closing also looking at the future, Libre Silicon like RISC-V designs, and where this might take Linux.
Drew Fustini
Automotive Grade Linux on Raspberry Pi: How Does It Work?Leon Anavi
Talk by Leon Anavi at Embedded Linux Conference North America 2020
Automotive Grade Linux (AGL) is a leading embedded Linux distribution for the automotive industry. The AGL Unified Code Base (UCB), using the Yocto Project and OpenEmbedded, has been already adopted by automotive manufacturers and it is present in vehicles like Toyota Camry and all-new 2020 Subaru Outback and Subaru Legacy.
Since 2016 AGL has been ported to Raspberry Pi which nowadays is a prefer getting started platform among the community. The presentation will explore the current status of AGL on Raspberry Pi, reveal war stories and practical experiences for supporting Wayland, PipeWire, libostree for software over the air updates as well as various hardware peripherals.
Guidelines and step by step instructions for building AGL image for Raspberry Pi will be revealed. We will do a deep dive in internals, such as integration of meta-raspberrypi BSP layer, Linux kernel and Mesa versions with firmware KMS to support both HDMI and the official Raspberry Pi touch screen DSI display.
The talk is appropriate for anyone, including beginners. No previous experience is required. Hopefully, the presentation will encourage more people to try AGL on Raspberry Pi and join our community.
PPC64 Open ISA and A2I Core along with the PPC64 Open Hardware Notebook PCB and Libre-Soc project.
This year IBM released the A2I POWER processor core design and associated FPGA environment. In 2019 IBM opened the POWER Instruction Set Architecture (ISA). The Power Progress Community released the PCB of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. Libre-SOC is a software-hardware project that aims to deliver a physical POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR controller. We will discover these concrete projects.
Redfish is an IPMI replacement standardized by the DMTF. It provides a RESTful API for server out of band management and a lightweight data model specification that is scalable, discoverable and extensible. (Cf: http://www.dmtf.org/standards/redfish). This presentation will start by detailing its role and the features it provides with examples. It will demonstrate the benefits it provides to system administrator by providing a standardized open interface for multiple servers, and also storage systems.
We will then cover various tools such as the DMTF ones and the python-redfish library (Cf: https://github.com/openstack/python-redfish) offering Redfish abstractions.
Open Source Hardware, Linux and RISC-VDrew Fustini
Open Source Hardware "Birds of a Feather” (BoF) session at Embedded Linux Conference 2018 in Portland. Topics include elements of open source hardware designs, applications in science, open source hardware that can run Linux, and recent libre silicon efforts including RISC-V architecture and SiFive.
Overview of Open Source, Free Software and Open Source Hardware (OSHW). Survey of Open Source licenses that can used for OSHW projects. Highlight OSHW projects that are democratizing scientific research equipment and enabling citizen science efforts. Review OSHW projects that have become commercial products. Discussion of different OSHW boards that can run Linux.
Introduction to Open Source Hardware (OSHW) including: the philosophy, best practices, CERN Open Hardware License, Open Hardware Summit, Open Source Hardware Association (OSHWA), Open Source Hardware Certification Program, OSHW Products, Linux on OSHW, and OSHW in Science.
Google Summer of Code and BeagleBoard.orgDrew Fustini
Slides for my Maker Faire New York 2016 talk:
Google Summer of Code and BeagleBoard.org
https://drive.google.com/file/d/0B_NI2VDamOOfOU9MV2lCd2dVSjg/view?usp=sharing
Taking the BeagleBone Cookbook recipes beyond BeagleBone BlackDrew Fustini
NOTE: Slides by Jason Kridner and Mark Yoder
Source: http://event.lvl3.on24.com/event/11/07/48/2/rt/1/documents/resourceList1454015491443/cookbookbeyondblack_draft.pdf
I did an overview of Embedded Linux topics (arch, SoCs, SBCs, kernel dev community, real-time, device tree, building root filesystem, etc) in 2014 for the Embedded Systems meetup at my hackerspace: http://www.meetup.com/NERP-Not-Exclusively-Raspberry-Pi/events/183068212/
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
1. Linux on RISC-V
Drew Fustini
drew@beagleboard.org
Twitter: @pdp7
Slides: https://github.com/pdp7/talks/blob/master/rv-elc.pdf
with open source hardware and open source FPGA tools
Embedded Linux Conference 2020
2. Open Source Hardware designer at OSH Park
(PCB manufacturing service in the USA)
drew@oshpark.com / Twitter: @oshpark
Board of Directors, BeagleBoard.org Foundation
drew@beagleboard.org
Board of Directors, Open Source Hardware Assoc.
Certification Program:
https://certification.oshwa.org/
RISC-V Ambassador for RISC-V International
https://riscv.org/
6. RISC-V at ELC
●
RISC-V: Instruction Sets Want to be Free
– Krste Asanovic (UC Berkeley)
– Wednesday, 10:35am: https://sched.co/c4PV
●
State of RISC-V Software Development Tools
– Khem Raj (Comcast)
– Wednesday 12:15pm: https://sched.co/c3Yn
●
Ask the Expert Session with Calista Redmond
– CEO of RISC-V International
– Thursday 11:45am: https://sched.co/cosw
7. Statement of Principles:
Hardware whose design is
made publicly available so
that anyone can study,
modify, distribute, make,
and sell the design or
hardware based on that design
8. Documentation required for electronics:
Schematics Board Layout
Editable source files for CAD software such as KiCad or EAGLE
Bill of Materials (BoM)
Not strict requirement, but best practice is for all components available from
distributors in low quantity
11. ●
When you write a C or C++ program, it is
compiled into instructions for the
microprocessor (CPU) to execute.
●
How does the compiler know what instructions
the CPU understands?
– defined by the Instruction Set Architecture
– The ISA is a standard, a set of rules that define
the tasks the processor can perform.
– Examples: x86 (Intel/AMD) and ARM
●
Both are proprietary and need commercial licensing
12. ●
RISC-V: Free & Open RISC Instruction Set Arch
– “new instruction set architecture (ISA) that was originally
designed to support computer architecture research and
education and is now set to become a standard open
architecture for industry”
– The 5th RISC instruction to come out out UC Berkeley
– RISC = Reduced Instruction Set Computer
13. ●
OSS+ELC 2020 Keynote:
“RISC-V: Instruction Sets Want to be Free”
– Krste Asanovic, UC Berkeley
– https://sched.co/c4PV
●
Instruction Sets Want To Be Free: A Case for RISC-V
– David Patterson, UC Berekely (co-creator of the original RISC)
– youtube.com/watch?v=mD-njD2QKN0
21. Is RISC-V Open Source?
●
RISC-V is an open ISA specification
– Creative Commons Attribution 4.0 International
●
An open ISA spec is required to implement an
open source processor
●
Not possible to design an open source processor
for a proprietary ISA such as x86 and ARM
●
Implementations of RISC-V ISA can be both
open source and proprietary
23. RISC-V at ELC
●
Go RISC-V Go:
State of Software Development Tools for RISC-V
– Khem Raj
– Wednesday 12:15pm
– https://sched.co/c3Yn
“Clang/LLVM has newly added backends for RISC-V. In addition, there
is now a golang port, which is still out of tree but headed towards
upstream acceptance. Additionally, GCC is working towards the GCC-
10 release, with several new enhancements to its RISC-V backend.
The LLVM backend also means Rust can now cross-compile to the
RISC-V architecture. The MUSL C library also has a new RISCV 64-bit
port. Additionally, we will discuss the state of tools on the RV32
ecosystem, progress on the glibc port for RV32, and Yocto Project
support for RV32 in its core, where QEMU RV32 port is usable for
doing application port.”
30. RISC-V and Industry
●
Designed to be extensible from microcontroller to
supercomputer!
●
RISC-V International now controls specifications:
riscv.org
– Over 400 members: companies, universities and more
– RISC-V Foundation transitioning to Swiss-based
RISC-V International
– YouTube channel has hundreds of talks!
●
Companies like Nvidia and Western Digital will
ship millions of devices with RISC-V cores
31. RISC-V and Industry
●
Avoid ISA licensing and royalty fees
●
Freedom to choose micro-architecture
implementation
– only a few companies like Apple, Samsung and
Qualcomm have ARM architecture licenses which
allows them to do a custom implementation
●
Freedom to leverage existing open source
implementations
– Berkeley’s Rocket and BOOM, ETH Zurich’s PULP
cores, Western Digital SweRV
32. ●
lowRISC is a not-for-profit organization whose goal
is to produce a fully open source System-on-Chip
(SoC) in volume
– “We will produce a SoC design to populate a low-cost
community development board and to act as an ideal
starting point for derivative open-source and
commercial designs”
●
OpenTitan project with Google
– Announcing OpenTitan, the First Transparent Silicon Root of Trust
33. SiFive
●
“founded by the creators of the free and open
RISC-V architecture as a reaction to the end of
conventional transistor scaling and escalating
chip design costs”
36. ●
SiFive Freedom FU540 SoC
– FOSDEM 2018 talk: “Igniting the Open Hardware
Ecosystem with RISC-V”
37. ●
SiFive Freedom FU540 SoC
– HiFive Unleashed board:
●
powerful but expensive ($1,000) and very limited
quantity
38. “Fedora on RISC-V”, Wei Fu (RV Summit 2019)
https://www.youtube.com/watch?v=WC6e3g8uWdk
39.
40. Kendryte 210
●
400MHz dual core RV64GC
●
8MB SRAM
●
Sipeed MAix BiT for RISC-V is only $13!
●
Damien Le Moal at Linux Plumbers 2019
– “RISC-V NOMMU and M-mode Linux”
●
Full support coming in Linux 5.8
●
Buildroot with busybox
– https://git.io/JJflC
41. Kendryte 210
●
need NOMMU/FDPIC support for better
userspace
– https://youtu.be/GydyykyNjxs (Maciej W. Rozycki)
– 8MB runs out very quick!
●
there is a MMU but an earlier spec which is not
supported by Linux
●
u-boot patch series
– [PATCH v14 00/20] riscv: Add Sipeed Maix support
– Sean Anderson (June 24th)
42.
43. Microchip PolarFire SoC FPGA
●
Hard RISC-V cores with FPGA fabric, similar to Xilinx
Zynq for ARM. Coming 2nd half 2020.
44.
45. OpenHW Group: Core-V Chassis SoC
●
similar to NXP iMX but with RISC-V cores
●
tape-out 2nd half of 2020
47. ●
Keynote at Hackday Supercon 2019 by
Dr. Megan Wachs of SiFive
●
“RISC-V and FPGAs: Open Source Hardware
Hacking”
– https://www.youtube.com/watch?v=vCG5_nxm2G4
48.
49. ●
Project IceStorm for Lattice iCE40
●
“A Free and Open Source Verilog-to-Bitstream Flow for iC
E40 FPGAs”
by Claire Wolf (oe1cxw) at 32c3
Open Source toolchains for FPGAs
50. ●
Project Trellis for Lattice ECP5
– “Project Trellis and nextpnr FOSS FPGA flow for the
Lattice ECP5”
- David Shah (@fpga_dave)
●
youtube.com/watch?v=0se7kNes3EU
Open Source toolchains for FPGAs
51. ●
Project X-Ray & SymbiFlow for Xilinix Series 7
– Timothy ‘mithro’ Ansell: “Xilinx Series 7 FPGAs Now
Have a Fully Open Source Toolchain!” (almost)
●
youtube.com/watch?v=EHePto95qoE
Open Source toolchains for FPGAs
52. Hackspace Magazine column on how
open source FPGA tools developed by
Claire Wolf (oe1cxw), David Shah and others
have made FPGAs more accessible than ever
before to makers and hackers:
hackspace.raspberrypi.org/issues/26/
Open Source and FPGAs
53. Section:
Linux on the Hackaday Badge
Slides: https://github.com/pdp7/talks/blob/master/rv-elc.pdf
54. Hackaday 2019 Supercon badge
●
RISC-V “soft” core on ECP5 FPGA
●
Gigantic FPGA In A Game Boy Form Factor
56. “Team Linux on Badge”
●
Blog post: Hackaday Supercon badge boots
Linux using SDRAM cartridge
●
Michael Welling (@QwertyEmedded), Tim
Ansell (@mithro), Sean Cross (@xobs), Jacob
Creedon (@jacobcreedon)
●
First attempt: use the built-in 16MB SRAM…
no luck :(
57. “Team Linux on Badge”
●
Second attempt:
– Jacob Creedon designed an a cartridge board that
adds 32MB of SDRAM to the Hackaday Supercon
badge… before the event!
58. “Team Linux on Badge”
●
Second attempt:
– Jacob Creedon designed an a cartridge board that
adds 32MB of SDRAM to the Hackaday Supercon
badge… before the event!
59.
60. Designing Hardware in Python?
●
Yes!
●
“Using Python for creating hardware to record
FOSS conferences!”
●
Tim “mithro” Ansell
●
youtube.com/watch?v=MkVX_mh5dOU
62. ●
LiteX used to build cores, create SoCs and full
FPGA designs.
●
LiteX is based on Migen
●
Migen lets you do FPGA design in Python!
●
https://github.com/enjoy-digital/litex
64. Linux on LiteX-VexRiscv
●
VexRiscv: 32-bit Linux Capable RISC-V CPU
●
SoC built using VexRiscv core and LiteX
modules like LiteDRAM, LiteEth, LiteSDCard, ...
– github.com/litex-hub/linux-on-litex-vexriscv
65.
66. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
67. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
68. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
69.
70.
71.
72.
73.
74. ●
Greg Davill got the screen working with LiteVideo!
– twitter.com/GregDavill/status/1231082623633543168
75. Open Source boards with
ECP5 FPGA
(can run Linux)
Slides: https://github.com/pdp7/talks/blob/master/rv-elc.pdf
91. RISC-V at ELC
●
RISC-V: Instruction Sets Want to be Free
– Krste Asanovic (UC Berkeley)
– Wednesday, 10:35am: https://sched.co/c4PV
●
State of RISC-V Software Development Tools
– Khem Raj (Comcast)
– Wednesday 12:15pm: https://sched.co/c3Yn
●
Ask the Expert Session with Calista Redmond
– CEO of RISC-V International
– Thursday 11:45am: https://sched.co/cosw