This document summarizes the NOEL-V processor family from Cobham Gaisler. It describes the NOEL-V as a RISC-V compliant 64-bit processor with fault tolerance features. It provides details on the processor architecture, peripherals, software ecosystem, verification process, and commercial and open source availability. Examples of projects adopting the NOEL-V include the European H2020 funded De-RISC and SELENE projects for safety-critical computing.

1. Information Classification: General
CONTRIBUTE.
COLLABORATE.
COMMERCIALIZE.
December 8-10 | Virtual Event

2. Information Classification: General
December 8-10 | Virtual Event
NOEL-V:A New High-Performance
RISC-V Processor Family
Johan Klockars and Alen Bardizbanyan
Cobham Gaisler
#RISCVSUMMIT

3. Information Classification: General
What We Do
The NOEL-V Processor Family
NOEL-V Fault Tolerance
NOEL-V Verification
NOEL-V Availability
Current NOEL-V Adoption

4. Information Classification: General
Cobham Gaisler – Space Computing
One-Stop-Shop
Synthesizable Processor Library Components
Compilers & Operating Systems Systems
Development Boards
Simulators & Debuggers

5. Information Classification: General
GRLIB – Define your own SoC
• GRLIB is a complete design environment
– Processors, Peripherals, Memory controllers
• AMBA on-chip bus with plug&play
• Fault-tolerant and standard versions
• Support for tools and prototyping boards
• Portability between technologies
– Classic VHDL for tool support
– IP cores instantiate abstractions, which then
map to an element in the target technology
– Common FPGA and ASIC technology mappings
• FPGA board template designs
NOEL-V

6. Information Classification: General
What We Do
The NOEL-V Processor Family
NOEL-V Fault Tolerance
NOEL-V Verification
NOEL-V Availability
Current NOEL-V Adoption

7. Information Classification: General
NOEL-V Processor Core
RISC-V RV64 and RV32 Processor Model
Characteristics:
• RISC-V 32- and 64-bit compliant processor core
• Superscalar – dual issue
• Fault Tolerance - Error Correction Codes (ECC)
• Leverage foreseen uptake of RISC-V software
and tool support in the commercial domain
• Compatible with GRLIB IP Core library
* GCC9.3.0 20200312 (RTEMS 5, RSB 5 (c53866c98fb2), Newlib 7947581
-g -march=rv64ima -mabi=lp64 -B /gsl/data/products/noelv/rtems-noel-1.0.3//kernel/riscv-rtems5/noel64ima/lib --specs bsp_specs
-qrtems -lrtemsdefaultconfig -O2 -funroll-all-loops -funswitch-loops -fgcse-after-reload -fpredictive-commoning -mtune=sifive-7-series
-finline-functions -fipa-cp-clone -falign-functions=8 -falign-loops=8 -falign-jumps=8 --param max-inline-insns-auto=20
** Using "#define ee_u32 int32_t" in core_portme.h, as is common for 64 bit RISC-V.
Primary feature set:
• RISC-V RV64GC
• AHB and AXI4 bus support
Performance (currently):
• CoreMark*/MHz
• dual-issue 4.41**
• single-issue 3.05**
https://www.gaisler.com/NOEL-V

8. Information Classification: General
NOEL-V Processor Architecture
RISC-V RV64GC (IMAFDC):
• 64-bit Base integer instructions (RV64I)
• MUL/DIV (M)
• Atomics (A)
• Single/Double Float (FD)
• GPL, small and slow
• Commercial, fully pipelined except div/sqrt
• Compressed instructions (C)
• Supported modes: M/S/U
• Physical Memory Protection (PMP)
• MMU
Pipeline features:
• 7-stage dual-issue in-order
• Late ALUs and branch unit
• Dynamic branch prediction
• BTB, BHT
• Return Address Stack (RAS)
Additional extensions:
• 32-bit Base instructions (RV32I)
• Hardware hypervisor support (H)
• Pending standardization
• User-level interrupts (N)
• Pending standardization
• Bit Manipulation (B)
• Pending standardization
• Vector operations (V)
• Being investigated
fetch decode
register
access
ALU0
ALU1
branch
late ALU0
late ALU1
late branch
memory
mul / div
FPU
register
write-back
CSR write
exception
L1 cache:
• Separate instruction and data caches
• Up to 2x16 kByte

9. Information Classification: General
NOEL-V MMU and cache
L2 cache (commercial license)
• AHB or AXI4 back-end
• Up to 128 bit wide frontside and back-end
• LRU or pseudo-random
• Up to 4-way associativity and 2 Mbyte
• Can be split between cores
• Address range configurable
• Write-through
• Write-back
• Uncacheable
MMU and L1 cache integrated
• MMU / PMP
• 39/32 bit virtual address (Sv39/Sv32)
• Configurable actual physical address bits
• Separate instruction and data TLBs
• Fully associative
• PMP available with or without MMU
• Hardware page table walk and
dirty/accessed bit handling
• Uncacheable address ranges
• Hardcoded
• In page tables (experimental)
• L1 caches
• Single cycle access
• Up to 128 bit AHB bus towards L2 cache etc
• Virtually indexed, physically tagged (VIPT)
• LRU
• Up to 4-way associativity and 16 kByte
• Instruction cache
• Delivers 64 bits per cycle to enable dual-issue
of non-compressed instructions
• Data cache
• Write-through
• Snooping for coherence
• Store-buffer

10. Information Classification: General
NOEL-V Integer Pipeline
• Buffer and align instructions
• Expand compressed
instructions
• Check for dual-issue conflicts
• Swap instructions if needed
• Check for illegal or
privileged instructions
• Check for RAS hit and
early branch
• Decide on early/late ALU/BU
• Insert pipeline bubbles
• Generate ALU and instruction control
• Read CSR
• FPU runs in parallel from here
• Combinational virtual address
to data cache
• Trigger
• Stall pipeline if needed
• Align data from cache
fetch decode
register
access
ALU0
ALU1
branch
late ALU0
late ALU1
late branch
memory
mul / div
FPU
register
write-back
CSR write
exception
• Collect exceptions
• External interrupts
• Debug
• BHT and BTB • Commit FPU operations
• Update BHT / BTB / RAS
• Trace
FE DE RA EX MEM EXC WB

11. Information Classification: General
NOEL-V Processor Peripherals
Implementing open standards
RISC-V Debug Module (DM)
• Compatible with the RISC-V debug specification
• JTAG Debug Module Interface
• Hart Run Control
• GPR and CSR register access
• Program buffer
• Triggers (match and instruction count)
• Instruction trace
• Bus trace
RISC-V Platform Level Interrupt Controller (PLIC)
• Compatible with the Platform Level Interrupt controller specification

12. Information Classification: General
NOEL-V Configurations
• The NOEL-V processor core is available as part of a subsystem that also contains system peripherals.
The subsystem can be configured to use the processor configurations listed in the table below.
• It is also possible to tailor additional configuration settings to
create custom processor configurations by editing the VHDL generic
(configuration parameter) assignments in the subsystem.
• Please see https://www.gaisler.com/NOEL-V for latest version and updates

13. Information Classification: General
Software Ecosystem
Software provided by Cobham Gaisler
Software NOEL-V
Bare-C toolchain Pre-built toolchain provided by Cobham Gaisler.
RTEMS Pre-built toolchain with BSP provided by Cobham Gaisler.
Work planned to upstream BSP during 2020.
Linux Prebuilt Linux images, GCC toolchain and buildroot environment provided by Cobham Gaisler.
VxWorks Cobham Gaisler provides NOEL-V BSP for VxWorks7 SR0650 and LLVM, Binutils toolchains.
Zephyr RISC-V support available upstream. NOEL-V support under assessment.
Simulators Currently not provided by Cobham Gaisler.
Future TSIM3 support for RISC-V is planned.
Debuggers GRMON3.
Boot loaders Currently not provided by Cobham Gaisler.
Hypervisors XNG, PikeOS, and Jailhouse, currently being ported.
Other 3rd party providers.

14. Information Classification: General
What We Do
The NOEL-V Processor Family
NOEL-V Fault Tolerance
NOEL-V Verification
NOEL-V Availability
Current NOEL-V Adoption

15. Information Classification: General
NOEL-V Fault Tolerance
• Under development.
• Hard errors: SEL, Destructive events
• Mitigated with target technology platform
• Soft errors (SEUs, MBUs, SETs, SEFI)
• Mitigated using cell selection and at design level
• Focus on protecting the system against Single Event Effects (SEE).
• energy deposited by heavy ions, or high energy proton, electron or neutron
• NOEL-V FT purpose
• Allow software execution to continue uninterrupted in the presence of correctable errors
• Prevent corrupted state from propagating outside the SoC
• Minimize jitter in execution time due to error correction
• Prevent error built up to avoid uncorrectable errors.
• NOEL-V FT core features
• Protection of processor core internal SRAM, adapted per target technology
• Reporting of detected correctable and uncorrectable errors
• Complemented by
• GRLIB example designs with radiation mitigation techniques applied for specific target technologies
• Protection of on-chip peripherals and external memory
• Software libraries to allow end users to have a coherent handling of errors on SoC level

16. Information Classification: General
What We Do
The NOEL-V Processor Family
NOEL-V Fault Tolerance
NOEL-V Verification
NOEL-V Availability
Current NOEL-V Adoption

17. Information Classification: General
NOEL-V Verification
• NOEL-V verification steps:
• Simulation based software tests + comparison with SPIKE simulation
• FPGA validation
• Trial implementations using Xilinx, Altera, Microchip, and ASIC flows
• For the simulator + SPIKE set up, verification is done through comparing each executed instruction from VHDL simulation with SPIKE traces.
• It is possible to pass events to a slightly modified SPIKE hence even timer interrupts can be simulated.
• Verification is independent from all the possible latencies which can vary on VHDL (hardware implementation).
• This allows to even compare each executed instruction when booting Linux and running tests on it during VHDL simulation.
• Main verification is done through extensive inhouse random instruction generation.
• Additional application simulations like (up to complex simulations like boot of Linux) are complementary to the verification.

18. Information Classification: General
NOEL-V Verification: Spike + Simulator
Random test
pattern
generator
VHDL
Simulation
SPIKE
Simulation
Simulator
transcript
=
SPIKE log
RESULT
Events
Instruction
stream

19. Information Classification: General
What We Do
The NOEL-V Processor Family
NOEL-V Fault Tolerance
NOEL-V Verification
NOEL-V Availability
Current NOEL-V Adoption

20. Information Classification: General
Commercial and Free Open Source
• NOEL-V and the GRLIB IP library are available in a dual licensing scheme: Commercial and
GNU GPL
• GRLIB (with the LEON3 processor) is a long running HW open source effort (version 1.0
release in 2005) that contains a subset of our IP.
• Having a business model building on an open standard (SPARC V8) and a dual licensing
scheme made it straightforward for us to adopt also RISC-V.
• Open source release allow customers to evaluate, and for the library to be adopted in
academia and by hobbyists.
• Historically, contributions to GRLIB have consisted primarily of template designs and
examples.
• Accepting code contributions has traditionally been difficult due to lack of verification evidence
(work is amplified due to need of doing verification of patches in house, and verification being
more resource consuming vs design).
• Approach taken today:
• Contributions are welcome! Threshold for patch acceptance can be perceived to be
high (verification issue)
• NOEL-V will rank high in terms of completeness of features vs. open source releases
from other vendors – and it is available in readable (V)HDL!
www.gaisler.com/getgrlib

21. Information Classification: General
December 2020 NOEL-V release
• NOEL-V has been released as part of the free open source GRLIB IP Library
• GRLIB contains a wide range of peripheral IP cores and provides template designs for
several FPGA boards, including Xilinx KCU105, Xilinx VC707, and Digilent Arty A7
• NOEL-V is a highly configurable RISC-V 64/32-bit processor IP core. Several standard
configurations have been defined and are listed at www.gaisler.com/NOEL-V
• Prebuilt bitstreams are available for the KCU105 FPGA board (www.gaisler.com/NOEL-
XCKU).
• The 2020-December release of the NOEL-V RISC-V processor includes configuration options
ranging from the High-Performance 64-bit RV64G (HPP64) to our tiniest 32-bit RV32I
(TIN32).
• B, C, H, N and V extensions not yet supported by open source release
• Free open-source model does not include fault-tolerance features
• Logic utilization results are available in area spreadsheet available at
www.gaisler.com/getgrlib
www.gaisler.com/NOEL-V
www.gaisler.com/getgrlib
discourse.grlib.community
www.gaisler.com/NOEL-XCKU

22. Information Classification: General
Building a SoC with GRLIB
• Steps required:
1. Download GRLIB IP library
2. Follow installation instructions
3. Select template design
4. Build template design
5. Test template design on board
6. Adapt template design to user needs, go back to step 4
• A free open source evaluation version of GRLIB can be downloaded from
https://www.gaisler.com/getgrlib
• The free open source version does not include all Cobham Gaisler IP cores
and the FT functionality.
• Visit GRLIB discourse for questions
https://discourse.grlib.community/
NOEL-V

23. Information Classification: General
What We Do
The NOEL-V Processor Family
NOEL-V Fault Tolerance
NOEL-V Verification
NOEL-V Availability
Current NOEL-V Adoption

24. Information Classification: General
H2020 – De-RISC
Dependable Real-Time Infrastructure for Safety-critical Computer
• European Commission Fast Track to Innovation Initiative
• De-RISC is a project that will productize a
multi-core RISC-V system-on-chip from Cobham
Gaisler and to port the XtratuM hypervisor
from fentISS SL to that design, to create a complete
computer platform consisting of hardware and
software.
• Project partners:
• Barcelona Supercomputing Center
• Cobham Gaisler AB
• FentISS SL
• Thales Research and Technology
• More information: http://www.derisc-project.eu
This project has received funding from the European Union’s Horizon 2020 Research and
Innovation programme under Grant Agreement EIC-FTI 869945
www.derisc-project.eu
De-RISC – Dependable Real-time Infrastructure for Safety-critical Computer

25. Information Classification: General
H2020 SELENE
Self-monitored Dependable platform for High-Performance Safety-Critical Systems
• High-performance computing that employs commercial off-the-
shelf components offers an alternative path to increasing the
computational capability of safety-critical applications. Despite
their potential in a number of domains, use of these systems is
limited due to the lack of certified, reliable hardware platforms.
• The EU funded SELENE proposes a safety-critical cognitive
computing platform.
• Project partners
• Technology providers
• Barcelona Supercomputing Center (HW safety and security)
• Cobham Gaisler AB (NOEL-V and SoC)
• Ikerlan (HW/SW safety and AI accelerator)
• OpenTech (SW safety)
• SIEMENS AT/DE (AI accelerator and Jailhouse hypervisor)
• Universitat Politècnica de València (NoC and AI accelerator)
• Use cases
• Airbus Defense and Space DE/FR (space robotics and satellites)
• CAF Signalling (autonomous train)
• Virtual Vehicles (autonomous robot)
• More information: https://www.selene-project.eu/
This project has received funding from the European Union’s Horizon 2020 research and
innovation programme under grant agreement no. 871467
GPP
NOEL-V
RAM
L1
write-through
snooping
L2 single/striped
write-back & write-through
AHB shared/striped
NOEL-V
RAM
L1
write-through
snooping
NOEL-V
RAM
L1
write-through
snooping
NOEL-V
RAM
L1
write-through
snooping
GPP
NOEL-V
RAM
L1
write-through
snooping
L2 single/striped
write-back & write-through
AHB shared/striped
NOEL-V
RAM
L1
write-through
snooping
NOEL-V
RAM
L1
write-through
snooping
NOEL-V
RAM
L1
write-through
snooping
A
X
I
A
X
I
NoC AXI non-coherent
RAM
A
X
I D
D
R
D
D
R
Accelerator
A
X
I
RAM
(AI)
DMA
Accelerator
A
X
I
RAM
(AI)
DMA
A
X
I
I/O
AHB
A
X
I
I/O A
P
B
I/O

26. Information Classification: General
More Information
www.gaisler.com/NOEL-V
www.gaisler.com/getgrlib
discourse.grlib.community

27. Information Classification: General
December 8-10 | Virtual Event
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