This document summarizes Drew Fustini's presentation about Linux on RISC-V. The key points are:
1) RISC-V is an open instruction set architecture that can be used as an alternative to proprietary ISAs like ARM and x86. It allows anyone to freely develop CPUs, SoCs and other hardware.
2) Several companies now offer RISC-V chips that run Linux, such as SiFive's HiFive Unleashed board. Open source projects are also bringing up Linux on chips like the Kendryte K210.
3) Open source FPGA tools like IceStorm, Trellis, X-Ray and SymbiFlow have made FPG
Embedded Linux Conference 2020:
Linux on RISC-V with open source hardware and open source FPGA tools
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, the Reform laptop and more.
I will also talk about the importance of the open RISC-V instruction set and free software FPGA toolchains. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a SoC capable of running Linux.
Finally, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Linux on RISC-V with Open Hardware (ELC-E 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. I will highlight that OpenHW Group has adopted the PULP Ariane from ETH Zurich for its Core-V CVA64 implementation. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2020 and 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Embedded Linux Conference 2020:
Linux on RISC-V with open source hardware and open source FPGA tools
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, the Reform laptop and more.
I will also talk about the importance of the open RISC-V instruction set and free software FPGA toolchains. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a SoC capable of running Linux.
Finally, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Linux on RISC-V with Open Hardware (ELC-E 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. I will highlight that OpenHW Group has adopted the PULP Ariane from ETH Zurich for its Core-V CVA64 implementation. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2020 and 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Want to run Linux with RISC-V on Open Source Hardware? This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
RISC-V growth and successes in technology and industry - embedded world 2021RISC-V International
RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is projected that by 2025 there will be over 62 billion RISC-V CPU cores and the total market for RISC-V IP and software is expected to grow to over $1b by 2025.
In 2020 alone, we saw successes with newly defined RISC-V accelerator architectures, affordable RISC-V open source small-board computers, development boards for personal computers, and an incredibly fast 64-bit RISC-V Core as the community also ratified key specifications and made advances in security.
As we see the growth of RISC-V into industries such as AI, machine learning, blockchain, 5G, medical, and industrial, we will see the ratifications of new extensions that enable this growth.
Join Kim McMahon, Director of Marketing and Stephano Cetola, Technical Program Manager as we take a look at where RISC-V is going in 2021.
LAS16-106: GNU Toolchain Development LifecycleLinaro
LAS16-106: GNU Toolchain Development Lifecycle
Speakers: Ryan Arnold
Date: September 26, 2016
★ Session Description ★
This presentation will examine the lifecycle of toolchain development from inception of the micro-architecture, to development of the ISA, to delivery of OS enablement in FOSS projects, to adoption in Linux Distributions. It will examine the behaviors of successful silicon vendors as well as behaviors of vendors that struggle to get their platform fully enabled in the GNU/Linux OS.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-106
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-106/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there's no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
How to run Linux on RISC-V (FOSS North 2020)Drew Fustini
Title:
How to run Linux on RISC-V (with open hardware and open source FPGA tools)
Abstract:
Want to run Linux with RISC-V on Open Source Hardware?
This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge using only open source tools thanks to Project Trellis, yosys and nextpnr. I will explain what migen and LiteX are, and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux on VexRiscv.
In conclusion, I will explore the landscape of open source chip designprojects and the Linux-capable RISC-V silicon chips on horizon for 2020, and talk about my desire to collaborate on an affordable (<$100?) OSHW Linux RISC-V board.
LAS16-500: The Rise and Fall of Assembler and the VGIC from HellLinaro
LAS16-500: The Rise and Fall of Assembler and the VGIC from Hell
Speakers: Marc Zyngier, Christoffer Dall
Date: September 30, 2016
★ Session Description ★
KVM/ARM has grown up. While the initial implementation of virtualization support for ARM processors in Linux was a quality upstream software project, there were initial design decisions simply not suitable for a long-term maintained hypervisor code base. For example, the way KVM/ARM utilized the hardware support for virtualization, was by running a ‘switching’ layer of code in EL2, purely written in assembly. This was a reasonable design decision in the initial implementation, as the switching layer only had to do one thing: Switch between a VM and the host. But as we began to optimize the implementation, add support for ARMv8.1 and VHE, and added features such as debugging support, we had to move to a more integrated approach, writing the switching logic in C code as well. As another example, the support for virtual interrupts, famously known as the VGIC, was designed with a focus on optimizing MMIO operations. As it turns out, MMIO operations is a less important and infrequent operation on the GIC, and the design had some serious negative consequences for supporting other state transitions for virtual interrupts and had negative performance implications. Therefore, we completely redesigned the VGIC support, and implemented the whole thing from scratch as a team effort, with a very promising result, upstream since Linux v4.7. In this talk we will cover the evolution of this software project and give an overview of the state of the project as it is today.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-500
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-500/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Want to run Linux with RISC-V on Open Source Hardware? This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
RISC-V growth and successes in technology and industry - embedded world 2021RISC-V International
RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is projected that by 2025 there will be over 62 billion RISC-V CPU cores and the total market for RISC-V IP and software is expected to grow to over $1b by 2025.
In 2020 alone, we saw successes with newly defined RISC-V accelerator architectures, affordable RISC-V open source small-board computers, development boards for personal computers, and an incredibly fast 64-bit RISC-V Core as the community also ratified key specifications and made advances in security.
As we see the growth of RISC-V into industries such as AI, machine learning, blockchain, 5G, medical, and industrial, we will see the ratifications of new extensions that enable this growth.
Join Kim McMahon, Director of Marketing and Stephano Cetola, Technical Program Manager as we take a look at where RISC-V is going in 2021.
LAS16-106: GNU Toolchain Development LifecycleLinaro
LAS16-106: GNU Toolchain Development Lifecycle
Speakers: Ryan Arnold
Date: September 26, 2016
★ Session Description ★
This presentation will examine the lifecycle of toolchain development from inception of the micro-architecture, to development of the ISA, to delivery of OS enablement in FOSS projects, to adoption in Linux Distributions. It will examine the behaviors of successful silicon vendors as well as behaviors of vendors that struggle to get their platform fully enabled in the GNU/Linux OS.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-106
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-106/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there's no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.
How to run Linux on RISC-V (FOSS North 2020)Drew Fustini
Title:
How to run Linux on RISC-V (with open hardware and open source FPGA tools)
Abstract:
Want to run Linux with RISC-V on Open Source Hardware?
This talk will explore the current options including how open source FPGA tools can be leveraged to build open Linux-capable systems.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge using only open source tools thanks to Project Trellis, yosys and nextpnr. I will explain what migen and LiteX are, and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux on VexRiscv.
In conclusion, I will explore the landscape of open source chip designprojects and the Linux-capable RISC-V silicon chips on horizon for 2020, and talk about my desire to collaborate on an affordable (<$100?) OSHW Linux RISC-V board.
LAS16-500: The Rise and Fall of Assembler and the VGIC from HellLinaro
LAS16-500: The Rise and Fall of Assembler and the VGIC from Hell
Speakers: Marc Zyngier, Christoffer Dall
Date: September 30, 2016
★ Session Description ★
KVM/ARM has grown up. While the initial implementation of virtualization support for ARM processors in Linux was a quality upstream software project, there were initial design decisions simply not suitable for a long-term maintained hypervisor code base. For example, the way KVM/ARM utilized the hardware support for virtualization, was by running a ‘switching’ layer of code in EL2, purely written in assembly. This was a reasonable design decision in the initial implementation, as the switching layer only had to do one thing: Switch between a VM and the host. But as we began to optimize the implementation, add support for ARMv8.1 and VHE, and added features such as debugging support, we had to move to a more integrated approach, writing the switching logic in C code as well. As another example, the support for virtual interrupts, famously known as the VGIC, was designed with a focus on optimizing MMIO operations. As it turns out, MMIO operations is a less important and infrequent operation on the GIC, and the design had some serious negative consequences for supporting other state transitions for virtual interrupts and had negative performance implications. Therefore, we completely redesigned the VGIC support, and implemented the whole thing from scratch as a team effort, with a very promising result, upstream since Linux v4.7. In this talk we will cover the evolution of this software project and give an overview of the state of the project as it is today.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-500
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-500/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Slides for my presentation on RISC-V and open source chip design at PumpingStation1 hackerspace tonight https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
From Make 'n Tell at xHain hackerspace in Berlin, I introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the importance of free software FPGA tools.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
I finish by talking about how Fomu is a great FPGA board to get started with!
Linux on RISC-V with Open Source Hardware (Open Source Summit Japan 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Google Slides link https://tinyurl.com/y6j8lfyz
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
CPU Diversity is growing: POWER and RISC-V OpenISA are real option with FPGA, ASIC and Motherboard available next year
Which are Open Hardware Power Architecture real options? Microwatt and LibreSoc have samples of low power Open ISA Power chip. The Power Progress Community released the Prototypes of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. What happen around OpenPower Foundations with project like PowerPI and LibreBMC.
Collaborate with us to build the Open Hardware PowerPC GNU/Linux notebook. You can collaborate in many ways, even with the Donation Campaign. https://www.powerpc-notebook.org/campaigns/donation-campaign-for-pcb-design-of-the-powerpc-notebook-motherboard/
Buy hardware, write software -- this is the basic rule we in the FLOSS community followed for many years. But things are changing. Today it is easier than ever before to create own digital hardware, aka. "chips."
In this talk I'll show give a introduction into what (in terms of tools, knowledge and other factors) is required to get a digital hardware design up and running. I'll also show how to get started: where can I find the community to get help and existing code? What existing projects can I contribute to?
Talk given on August 20, 2016 at FrOSCon in St. Augustin, Germany.
Embedded Fest 2019. Wei Fu. Linux on RISC-V--Fedora and Firmware in practiceEmbeddedFest
Summarize Fedora on RISC-V development including the little history, current status and some simple steps describing how to run Fedora on QEMU,FPGA board or the SiFive RV64 development board. Meanwhile, provide the status of current Specs and firmware(OpenSBI/UEFI/uboot) for RISC-V and the kernel development status.
The Open Hardware PowerPC Notebook designed around GNU/Linux will be showed at NOI Techpark. We had presented here its motherboard design in 2018. We will updates regarding last developments for u-boot AMD video drivers, re-design of heat pipes, and CE test certification process. We will give future availability milestones of this notebook and details regarding the GNU/Linux distributions or other OS that could runs on it.
This presentation by Roman Stratiienko (Software Engineer, Consultant, GlobalLogic) and Stanislav Goncharov (Senior Software Engineer, Consultant, GlobalLogic) was delivered at GlobalLogic Kharkiv Embedded TechTalk #5 on November 22, 2019.
Speakers shared their experience and results on the challenge started last year to make porting of cutting edge Android 10 to low-cost Orange Pi Plus 2E platform. They made it open source and available for every embedded s/w enthusiast based on AOSP project and Linux kernel upstream.
Event materials: https://www.globallogic.com/ua/events/kharkiv-embedded-techtalk-5/
PPC64 Open ISA and A2I Core along with the PPC64 Open Hardware Notebook PCB and Libre-Soc project.
This year IBM released the A2I POWER processor core design and associated FPGA environment. In 2019 IBM opened the POWER Instruction Set Architecture (ISA). The Power Progress Community released the PCB of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. Libre-SOC is a software-hardware project that aims to deliver a physical POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR controller. We will discover these concrete projects.
Clear Containers is an Open Containers Initiative (OCI) “runtime” that launches an Intel VT-x secured hypervisor rather than a standard Linux container. An introduction of Clear Containers will be provided, followed by an overview of CNM networking plugins which have been created to enhance network connectivity using Clear Containers. More specifically, we will show demonstrations of using VPP with DPDK and SRIO-v based networks to connect Clear Containers. Pending time we will provide and walk through a hands on example of using VPP with Clear Containers.
About the speaker: Manohar Castelino is a Principal Engineer for Intel’s Open Source Technology Center. Manohar has worked on networking, network management, network processors and virtualization for over 15 years. Manohar is currently an architect and developer with the ciao (clearlinux.org/ciao) and the clear containers (https://github.com/01org/cc-oci-runtime) projects focused on networking. Manohar has spoken at many Container Meetups and internal conferences.
I did an overview of Embedded Linux topics (arch, SoCs, SBCs, kernel dev community, real-time, device tree, building root filesystem, etc) in 2014 for the Embedded Systems meetup at my hackerspace: http://www.meetup.com/NERP-Not-Exclusively-Raspberry-Pi/events/183068212/
Open Source Hardware and Libre SiliconDrew Fustini
My Open Source Hardware and Libre Silicon talk for Penguicon 2017.
Open Source Hardware (OSHW) designs are made publicly available so that anyone can study, modify, distribute, make or sell designs or hardware based on that design. This talk will explore the shared values with Open Source software and the specifics of publishing a hardware project under an Open Source license.
It will include examples of Linux running on OSHW with projects like BeagleBone, CHIP, MinnowBoard and more. The role of the Open Source Hardware Association and annual Open Hardware Summit will also be discussed, along with important OSHW projects for scientific researchers.
There are exciting new developments within the last year for OSHW at the chip level. Projects like lowRISC, J-Core, OnChip and SiFive are working to produce true Open Source silicon processors. The FOSSi Foundation and LibreCores are helping to organize and promote this exciting new ecosystem.
Linux on Open Source Hardware with Open Source chip design (36c3)Drew Fustini
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
Presented at the 36th Chaos Communication Congress (36c3) in Leipzig, Germany:
https://fahrplan.events.ccc.de/congress/2019/Fahrplan/events/10549.html
Video: https://media.ccc.de/v/36c3-10549-linux_on_open_source_hardware_with_open_source_chip_design
YouTube: https://www.youtube.com/watch?v=mnOBTD9dgsg
Open Source Hardware, Linux and RISC-VDrew Fustini
Open Source Hardware "Birds of a Feather” (BoF) session at Embedded Linux Conference 2018 in Portland. Topics include elements of open source hardware designs, applications in science, open source hardware that can run Linux, and recent libre silicon efforts including RISC-V architecture and SiFive.
Overview of Open Source, Free Software and Open Source Hardware (OSHW). Survey of Open Source licenses that can used for OSHW projects. Highlight OSHW projects that are democratizing scientific research equipment and enabling citizen science efforts. Review OSHW projects that have become commercial products. Discussion of different OSHW boards that can run Linux.
Introduction to Open Source Hardware (OSHW) including: the philosophy, best practices, CERN Open Hardware License, Open Hardware Summit, Open Source Hardware Association (OSHWA), Open Source Hardware Certification Program, OSHW Products, Linux on OSHW, and OSHW in Science.
Google Summer of Code and BeagleBoard.orgDrew Fustini
Slides for my Maker Faire New York 2016 talk:
Google Summer of Code and BeagleBoard.org
https://drive.google.com/file/d/0B_NI2VDamOOfOU9MV2lCd2dVSjg/view?usp=sharing
Taking the BeagleBone Cookbook recipes beyond BeagleBone BlackDrew Fustini
NOTE: Slides by Jason Kridner and Mark Yoder
Source: http://event.lvl3.on24.com/event/11/07/48/2/rt/1/documents/resourceList1454015491443/cookbookbeyondblack_draft.pdf
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Epistemic Interaction - tuning interfaces to provide information for AI support
Linux on RISC-V
1. Linux on RISC-V
Drew Fustini
drew@beagleboard.org
Twitter: @pdp7
Slides: https://github.com/pdp7/talks/blob/master/rv-pint.pdf
with open source hardware and open source FPGA tools
Raspberry Pint (May 26th
, 2020)
2. Statement of Principles:
Hardware whose design is
made publicly available so
that anyone can study,
modify, distribute, make,
and sell the design or
hardware based on that design
3. Documentation required for electronics:
Schematics Board Layout
Editable source files for CAD software such as KiCad or EAGLE
Bill of Materials (BoM)
Not strict requirement, but best practice is for all components available from
distributors in low quantity
6. ●
When you write a C or C++ program, it is
compiled into instructions for the
microprocessor (CPU) to execute.
●
How does the compiler know what instructions
the CPU understands?
– defined by the Instruction Set Architecture
– The ISA is a standard, a set of rules that define
the tasks the processor can perform.
– Examples: x86 (Intel/AMD) and ARM
●
Both are proprietary and need commercial licensing
7. ●
RISC-V: Free and Open RISC Instruction Set
Arch
– “new instruction set architecture (ISA) that was
originally designed to support computer architecture
research and education and is now set to become a
standard open architecture for industry”
8. ●
RISC-V: Free and Open RISC Instruction Set
Arch
●
Instruction Sets Want To Be Free: A Case for RISC-V
– David Patterson, UC Berekely – co-creator of the original RISC!
– https://www.youtube.com/watch?v=mD-njD2QKN0
●
RISC-V Summit 2019: State of the Union
– Krste Asanovic, UC Berkeley
– https://www.youtube.com/watch?v=jdkFi9_Hw-c
9.
10.
11. RISC-V and Industry
●
Designed to be extensible
– Microcontroller to supercomputer
●
RISC-V Foundation now controls standard: riscv.org
– Over 400 members: companies, universities and more
– YouTube channel has hundreds of talks!
●
https://www.youtube.com/channel/UC5gLmcFuvdGbajs4VL-WU3g
●
Companies like Nvidia and Western Digital will ship millions of
devices with RISC-V
●
Avoid ARM licensing fees
●
Freedom to leverage open source implementations
●
BOOM, Rocket, PULP, SweRV, and many more
12. ●
lowRISC is a not-for-profit organisation whose goal
is to produce a fully open source System-on-Chip
(SoC) in volume
– “We will produce a SoC design to populate a low-cost
community development board and to act as an ideal
starting point for derivative open-source and
commercial designs”
●
OpenTitan project with Google
– Announcing OpenTitan, the First Transparent Silicon Root of Trust
13. ●
My column in the Hackspace Magazine is an
introduction to RISC-V and how it is enabling
open source chip design:
– hackspace.raspberrypi.org/issues/27/
14. SiFive
●
“founded by the creators of the free and open
RISC-V architecture as a reaction to the end of
conventional transistor scaling and escalating
chip design costs”
17. ●
FOSDEM 2018 talk
– YouTube: “Igniting the Open Hardware Ecosystem
with RISC-V: SiFive's Freedom U500 is the World's
First Linux-capable Open Source SoC Platform”
– Interview with Palmer Dabbelt of SiFive
SiFive: Linux on RISC-V
19. RISC-V Summit 2019: Linux on RISC V Fedora and
Firmware Status Update
●
https://www.youtube.com/watch?v=WC6e3g8uWdk
●
Wei Fu – Software Engineer, Red Hat
20.
21.
22.
23.
24.
25. ●
Linux now runs the low cost Kendryte K210
RISC-V processor
– dual core 64-bit RISC-V at 400MHz with 8MB SRAM
– Sipeed MAix BiT for RISC-V is only $13!
– Damien Le Moal at Linux Plumbers Conf:
RISC-V NOMMU and M-mode Linux
●
youtube.com/watch?v=ycG592N9EMA&t=10394
●
jump to 2h 53m
– Many RISC-V Improvements Ready For Linux 5.5: M-
Mode, SECCOMP, Other Features
– How to Build & Run Linux on Kendryte K210 RISC-V
NOMMU Processor
26.
27.
28. ●
Sipeed now has prebuilt Linux 5.6
– https://twitter.com/SipeedIO/status/1228594799675990
016/
29. ●
Microchip PolarFire SoC FPGA
– Hard RISC-V with FPGA fabric… like the Xilinx
Zync for ARM
●
OpenHW Core-V SoC which is similar to NXP
iMX with RISC-V instead of ARM!
– “OpenHW Group Unveils CORE-V Chassis SoC Pr
oject, Building on PULP Project IP”
Coming in 2020
32. ●
Keynote at Hackday Supercon 2019 by
Dr. Megan Wachs of SiFive
●
“RISC-V and FPGAs: Open Source Hardware
Hacking”
– https://www.youtube.com/watch?v=vCG5_nxm2G4
33.
34. ●
Project IceStorm for Lattice iCE40
●
“A Free and Open Source Verilog-to-Bitstream Flow for iC
E40 FPGAs”
by Claire Wolf (oe1cxw) at 32c3
Open Source toolchains for FPGAs
35. ●
Project Trellis for Lattice ECP5
– “Project Trellis and nextpnr FOSS FPGA flow for the
Lattice ECP5”
- David Shah (@fpga_dave)
●
youtube.com/watch?v=0se7kNes3EU
Open Source toolchains for FPGAs
36. ●
Project X-Ray & SymbiFlow for Xilinix Series 7
– Timothy ‘mithro’ Ansell: “Xilinx Series 7 FPGAs Now
Have a Fully Open Source Toolchain!” (almost)
●
youtube.com/watch?v=EHePto95qoE
Open Source toolchains for FPGAs
37. ●
Hackspace Magazine column about how about
open source FPGA tools developed by
Claire Wolf (oe1cxw), David Shah and others
have made FPGAs more accessible than ever
before to makers and hackers:
– hackspace.raspberrypi.org/issues/26/
Open Source and FPGAs
38. Section:
Linux on the Hackaday Badge
Slides: https://github.com/pdp7/talks/blob/master/rv-munich.pdf
39. Hackaday 2019 Supercon badge
●
RISC-V “soft” core on ECP5 FPGA
●
Gigantic FPGA In A Game Boy Form Factor
41. “Team Linux on Badge”
●
Blog post: Hackaday Supercon badge boots Linux
using SDRAM cartridge
– https://blog.oshpark.com/2019/12/20/boot-linux-on-this-
hackaday-supercon-badge-with-this-sdram-cartridge/
●
Michael Welling (@QwertyEmedded), Tim Ansell
(@mithro), Sean Cross (@xobs), Jacob Creedon
(@jacobcreedon)
●
First attempt: use the built-in 16MB SRAM…
no luck :(
– (though xobs now might have a way to do it)
42. “Team Linux on Badge”
●
Second attempt:
– Jacob Creedon designed an a cartridge board that
adds 32MB of SDRAM to the Hackaday Supercon
badge… before the event!
43. “Team Linux on Badge”
●
Second attempt:
– Jacob Creedon designed an a cartridge board that
adds 32MB of SDRAM to the Hackaday Supercon
badge… before the event!
44.
45. Designing Hardware in Python?
●
Yes!
●
“Using Python for creating hardware to record
FOSS conferences!”
●
Tim “mithro” Ansell
●
youtube.com/watch?v=MkVX_mh5dOU
51. ●
LiteX used to build cores, create SoCs and full
FPGA designs.
●
LiteX is based on Migen
●
Migen lets you do FPGA design in Python!
●
https://github.com/enjoy-digital/litex
53. Linux on LiteX-VexRiscv
●
VexRiscv: 32-bit Linux Capable RISC-V CPU
●
SoC built using VexRiscv core and LiteX
moduels like LiteDRAM, LiteEth, LiteSDCard, ...
– github.com/litex-hub/linux-on-litex-vexriscv
54.
55. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
56. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
57. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
58.
59.
60.
61.
62.
63.
64. ●
Greg Davill got the screen working with LiteVideo!
– twitter.com/GregDavill/status/1231082623633543168
65. Open Source boards with
ECP5 FPGA
(can run Linux)
Slides: https://github.com/pdp7/talks/blob/master/rv-munich.pdf