Andes enhancing verification coverage for risc v vector extension using riscv-dv
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1) The document discusses using RISCV-DV, an open source framework, to enhance verification coverage for the RISC-V Vector extension. 2) It describes how RISCV-DV implements the Vector extension through instruction support, programmer's model support, and constrained random generation of vector programs. 3) A case study shows how Andes customized RISCV-DV to verify their NX27V processor implementation of the Vector extension through co-simulation and directed instruction streams.
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Andes enhancing verification coverage for risc v vector extension using riscv-dv
- 1. Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV DingKai Huang, Andes Technology Tao Liu, Google
- 2. Agenda Motivation 1 RISCV-DV Framework 2 Vector Extension in RISCV-DV 3 Case study: Andes NX27V 4
- 3. Taking RISC-V® Mainstream 3 Vector Computation Integer arithmetic Atomic memory operation Fixed-point arithmetic Memory access Floating-point arithmetic Vector reduction Vector mask Permutation Length agnostic Register grouping Masking 32 vector registers Scalar operands Vector operands Control and status registers RISC-V Vector Extension
- 4. Taking RISC-V® Mainstream 4 Enhance Verification Coverage RISCV-DV Open source ISA Extensions uArchitecture-aware Randomness Performance Extendibility Instruction variation Sequence Programmer’s model Architecture uArchitecture Arithmetic Load Br Add SEW VL LMUL RVV RV32 RV64 FSM Issue Scoreboard FIFO RF Privileged Architecture Memory Access Permutation
- 5. Taking RISC-V® Mainstream 5 RISCV-DV Framework RISCV-DV source code Compile generator Generate assembly Compiler ISS sim RTL sim Compare Binary Assembly Log Log Simulator Simulator ISS ISS Simulator
- 6. Taking RISC-V® Mainstream 6 RISCV-DV Program Generator Generated Program RISC-V Program Generator Modular ISA classes I M C F D A V X RISC-V processor configuration Page table generator Illegal instruction generator Trap handler generator Data/stack section generator Directed instruction stream Initialization routine Main program Sub program 0 … ... Sub program n Interrupt / trap handler Data sections Stack section Instruction Page table
- 7. Taking RISC-V® Mainstream 7 Vector Extension Implementation Status Instruction class refactoring Basic V0.8 arithmetic instruction support Vector extension implementation from Andes Support register grouping, unit load/store etc Merged V0.8 basic version Added v0.8 strided/indexed load/store, vector AMO etc Vector extension v0.8 -> v0.9 migration (WIP) Vector extension v0.8 tag release Vector extension v0.9 -> v1.0 migration Vector extension coverage model, co-simulation flow Future work RISCV-DV Upstream
- 8. Taking RISC-V® Mainstream 8 Vector Extension in RISCV-DV Vector V0.9 Vector Instructions Programmer’s Model Integer Arithmetic Memory Access Permutation V/X/F GPR Configuration Setting Floating-Point/Fix-Point Reduction Mask Initialization Register Grouping Random Selection Random VTYPE/VL Random LMUL AMO
- 9. Taking RISC-V® Mainstream 9 Vector Extension Programmer’s Model SEW SEW SEW SEW VLEN 0 1 2 3 4 5 6 7 LMUL Fractional LMUL VSTART VL Mask SEW EEW=2*SEW Widening SEW EEW=2*SEW Narrowing VMA/VTA
- 10. Taking RISC-V® Mainstream 10 Make a Vector Instruction Legal Vector Instruction LMUL SEW Destination Reg Source Reg VL VSTART Mask VLEN XLEN FLEN ELEN (2*SEW <= ELEN) and (2*LMUL <= 8) Widening Destination Reg != V0 Masked Destination Reg != Source Reg Others SEW < ELEN LMUL ≤ 8 VSTART<VL FP ELEN>=64 for Quad widening VL < VLEN*LMUL/SEW SEW < 64 All Reg Index % vlmul == 0 Reg Index % (2*vlmul) == 0 Others
- 11. Taking RISC-V® Mainstream 11 Additional Build-in Features Address Mode Unitstrided Strided Indexed Address Randomization Address Span Data Page Page Size Register Reg Reservation Base Address Setup Vector Load/Store Segment V2 V4 V6 … Reserved vector register VV VX VI … Allowed variants VF VEC ZVLSSEG FF Instruction subgroups Vector load store stream
- 12. Taking RISC-V® Mainstream 12 Case Study: Andes NX27V • AndeStar™ V5 ISA – RISC-V compliant – Andes Extensions • Andes Custom Extension™ (ACE) • Advanced CoDense™ technology • RISC-V Vector extension – Out-of-Order – Andes extended format for AI
- 13. Taking RISC-V® Mainstream 13 Andes RISCV-DV Framework Randomized Processor Configuration RISCV-DV Program Constraint Program Andes RISC-V SoC ISS Co-simulation Coverage Monitors Assertions Modular ISA classes I M C F D A V X Andes ISA Extensions
- 14. Taking RISC-V® Mainstream 14 Andes CoSimulation Flow RISCV-DV Compiler Assembly Link Script Binary ISS Memory Andes NX27V Simulation Log Compare Andes SoC
- 15. Taking RISC-V® Mainstream 15 Customize an Instruction Stream riscv_rand_instr_test andes_rand_instr_test • Override generation config • Simulation control • Directed instruction streams instr_limit_test RVV Arithmetic Functional Unit Stress Test Issue Unit Stress Test Scoreboard Stress Test Others Others riscv_rand_instr_stream andes_rand_instr_stream • Customized randomization constraint init_vector_gpr randomize_gpr randomize_instr insert_instr mix_instr_steram insert_instr_stream
- 16. Taking RISC-V® Mainstream 16 Constrained Random Verification Vector Extension F/D Extension XLEN/VLEN ELEN VTYPE/VL/LMUL Mask Instruction Sets HW Configurations Vector Configurations Constraints Instruction Sequence Custom Extension Additional Constraints B2B Instructions Register Dependences
- 17. Taking RISC-V® Mainstream 17 uArch-level Constrained Random Scoreboard Issue Logic FIFOs FUs GPR Dependency Instruction with Long Latency B2B Issue Interleaved FUs Full/Empty B2B Execution Micro Operations RF Maximum Read Port VIQ Issue Issue Issue FP INT L/S Scoreboard VRF …
- 18. Taking RISC-V® Mainstream 18 Instruction Streams • Back-to-Back Execution Integer ADD Integer SUB Floating-Point ADD Floating-Point SUB • Register dependency V1 = V2 + V3 V4 = V1 + V4 Integer ADD V0 Mask Integer SUB • Structural Hazard V1 Load Integer ADD Vpermute V1 LS Unit Integer Unit • FIFO VDIV VADD VSUB Long latency
- 19. Taking RISC-V® Mainstream 19 Bugs Found VIQ Issue Issue Issue FP INT L/S Scoreboard Decode VRF … Data Dependency • Between functional Units Structural Hazard • Read port conflict • Write port conflict ISS Bugs • Unexpected exception • CSR update • Unexpected value for corner case Floating-Point • Scalar operand with mask • Precision change • NaN value Unexpected illegal exception • LMUL • SEW
- 20. Taking RISC-V® Mainstream 20 Future Work • Vector extension support for spec v1.0 • Illegal instruction testing for vector extension • Functional coverage model for vector extension