Report on PLL in IEEE format

1. Phase Locked Loop
Authors Name: Manojit Roy
Applied Electronics & Instrumentation Engineering
Haldia Institute of Technology
Haldia, India
roy.manojit44instru@gmail.com
Authors Name: Dev Dutta Ghosh
Applied Electronics & Instrumentation Engineering
Haldia Institute of Technology
Haldia, India
Abstract— This report is based on Phase Locked Loop. A
slight overview is been implanted in this report on 2 types of
Phase Locked Loop i.e. Analog PLL and Digital PLL. The circuit
and operation of PLL is also discussed and its application in the
field of communication.
Keywords—PLL, Digital PLL, Analog PLL, VCO, DCO
I. INTRODUCTION
Modern era is of electronics. Without electronics we can’t
imagine our life. Communication is also one of the main aspect
in our life. Phase Locked Loop or PLL is a device used for
frequency and phase tracking, carrier and symbol
synchronization, demodulation, and frequency synthesis, are
fundamental building blocks in today's complex
communications systems. It is therefore essential for both
students and practicing communications engineers interested in
the design and implementation of modern communication
systems to understand and have insight into the behavior of
these important and ubiquitous devices. The PLL behaves as a
nonlinear device (at least during acquisition). PLL used as a
frequency multiplier, as a FM & AM demodulator, as a
synchronizer in communication system etc. PLL also have a
major role in space communication. There are basically analog
as well as digital PLL. But here we discuss about the analog
PLL. PLL is of immense importance in electronics
communication, it is a one of the basic building blocks in many
major communication system.
II. PHASE LOCKED LOOP
Full form of PLL is ‘Phase Locked Loop’. PLL is a circuit,
synchronizing an output signal (generated by an oscillator)
with a reference or input signal in the frequency as well as in
phase. A negative feedback control system whose operation is
closely linked to frequency modulation (FM). Automatically
adjusts the frequency, and phase of a control signal to match a
reference signal. Commonly used for carrier synchronization
and indirect frequency demodulation. A phase-locked
loop or phase lock loop (PLL) is a control system that
generates an output signal whose phase is related to the phase
of an input "reference" signal. It is an electronic circuit
consisting of a variable frequency oscillator and a phase
detector. This circuit compares the phase of the input signal
with the phase of the signal derived from its output oscillator
and adjusts the frequency of its oscillator to keep the phases
matched.
III. PLL DESIGN
A. Analog PLL
There are major 4 functional block of analog PLL. They
are Phase detector, low pass filter, VCO and a feedback path.
A phase detector is basically a comparator that compares
the input frequency f_in with feedback frequency f_out.
Comparing the input frequency & output frequency it provides
a error signal which is basically a Dc voltage. The loop is
locked when these two signals are of the same frequency and
have a fixed phase difference. Basically Phase Detector works
as an Ex-OR gate.
Low-pass filter is used to remove high frequency
components and noise from the output of the phase detector.
Low Pass Filter provides a steady dc level voltage which
becomes the input of VCO.
Voltage-controlled oscillator generates frequency
controlled by input voltage. The dc level output of a low-pass
filter is applied as control signal to the voltage-controlled
oscil¬lator (VCO). The VCO frequency is adjusted till it
becomes equal to the frequency of the input signal. During this
adjustment, PLL goes through three stages-free running,
capture and phase lock.
B. Digital PLL
Digital PLL have major 3 components. They are Phase
error detector, Digital filter and DCO.

2. Counter - starts counting on the positive-going edge of the
flip-flop waveform. The content of the counter, No, which is
proportional to the phase error, is applied to digital filter. The
output of the digital filter K controls the period of the DCO.
DCO - programmable divide-by-K counter.
IV. PLL OPERATION
A. Free Running Stage
When no input is applied at the phase detector, then due to
VCO, PLL works in Free Running Stage. The output
frequency of this stage is dependent on the free running
frequency of VCO.
B. Capture Stage
When a input frequency is applied at the phase detector,
then due to feedback mechanism PLL tries to track the output
with respect to input. This stage is called Capture Stage.
C. Phase Locked State
Due to feedback mechanism, the frequency comparison
stops as soon as the output frequency become equal to the
input frequency. This stage is called Phase Locked State.
ACKNOWLEDGMENT
Apart from the efforts of myself, the success of any project
depends largely on the encouragement and guidelines of many
others. I take this opportunity to express my gratitude to the
people who have been helpful in the successful completion of
this report. I want to express my gratitude to all the people
who have given their heart whelming support to finish this
report. I would like to thanks whole Applied Electronics &
Instrumentation Department for their support.
REFERENCES
[1] Mao Lai and Michino Nakano, “ Special Section on Phase Locked Loop
Techniques”, Guest Editorial, IEEE Transactions on Industrial
Electronics,Vol 43, No 6, December 1996.
[2] Guan Chyun Hsich and James C Hung, “Phase Locked Loop Techniques
–A Survey”, IEEE Transactions on Industrial Electronics, Vol 43, No 6,
December 1996.
[3] F.M Gardner, “Phase Locked Loop Techniques”, 2nd edition; New
York; Wiley 1979
[4] William C Lindsey and Chak Chie, “ A survey of Digital Phase Locked
Loops”, Procedings of the IEEE, vol 69, No 4, April 1981
[5] Silicon Laboratories, “Introduction to FPGA based ADPLL”, rev
0.13/11, An 575, 2011
[6] R.E Best, “Phase Locked loops, theory Design and Applications”, New
York; Mc Graw Hill, 1993, 2nd edition.
[7] J R Cessna, “Digital phase locked loops with sequential loop filters. A
case for coarse quantization”, In proc. Int. Telemetering Conf; vol VIII,
pp 136-148, October 1972
[8] A Yamamoto and S Mori, “ Performance of a binary quantized all digital
phase locked loop with a new class of sequential filter”, IEEE
Transactions on Information Theory, Vol IT-18, pp 488-493, July 1972
[9] Liangge Xu, Saaka Lindfors, Kari Stadius and Jussi Ryynanen, “ A
2.4GHz low power all digital phase locked loop”, IEEE Transactions on
solid state circuits, Vol 45, No 8, August 2010.