Joseph Alvarez has over 10 years of experience as an IC development engineer and design verification engineer at ROHM LSI Design Philippines, where he is involved in all stages of IC product development from design to manufacturing and has worked on projects including various memory chips and display drivers. He holds a Bachelor's degree in Electronics and Communications Engineering from Don Bosco Technical College and is skilled in using EDA tools from Cadence and Synopsys for simulation, layout, and verification. In his free time, he enjoys music, boxing, and spending time with his family.

1. Joseph Anthony Efa Alvarez
83 St. Joseph Ave., Dela Costa Homes, Barangka, Marikina City | 0917-7906803| josephanthonyalvarez@yahoo.com
Experience
· IC DevelopmentEngineer
· ROHM LSI Design Philippines, Inc. (Oct. 2008 – Present)
· Design Verification – used EDA Tools, as well as bench equipment tocompletely evaluate a specific set of test
parameters of various integrated IC’s (current consumption, operating voltage range, input/output voltage High and
Low, POR, UVLO, etc.) and observe behavior or any dependencies it will show against varying voltage, load,
temperature,and other factors that may affect its overall function
· Development Engineer – product development is divided to 5 phases:
· Design – IC starts with a design specification, which are then used as a basis in computing and analyzing circuits
and blocks. Design of circuits may be new, or old ones may be modified if needed. To speed things up, EDA Tools
and various techniques (checkpoints) are followed to ensure commitment to the specifications.
· Layout – Masks are then developed to create and actualize the design on a silicon wafer. Again, EDA tools are used
to make netlist-driven “polygons” and create photomasks. As the developer,making sure the proper layout
techniques and precautions are implemented.
· Evaluation/TEST – after Wafer fabrication, “design samples” are then tested on a bench setup or an automated
machine. Parameter planning, setup,execution, and analysis of the results are the main tasks, wherein the goal is
to judge whether it passed the standards that were already presented during its design.
· Manufacturing Transfer (Yield Analysis) – after passing rigorous tests, a “mock” run is done to check upon
structural defects that cannot be easily seen during evaluation. Test parameters and test limits are planned
carefully (since Design), to properly separate good samples from defective ones, and guarantee a delivery of
sorted design samples to customers. Proper interpretation of Pareto diagrams, histograms, shot and DUT
defects/dependencies is a must.
· Previous Projects include:
· 125degC Operation 2kBit EEPROM uWire Bus (Automotive)
· 128k,64k, 8k, 4k, 2k, 1k EEPROM with SPI bus (Non-automotive series)
· 128kEEPROM SPI Bus with ECC (error correction code, Automotive)
· 144-dot LCD Segment Driver (1/3 and ½ bias, ¼ Duty, I2C Bus, Non-Automotive)
· 80,144,200-Dot LCD Segment Driver (same as above, Automotive)
· Other Experiences
· SPICE-to-Spectre Model Conversion
· TLP Model Development (Spectre/SPICE)
· Verilog-A Model Development of a Switching Regulator
· Monte Carlo Analysis (using Cadence Analog Design Environment XL)
· SpectreVerilog Mixed-mode simulation
· Library Development using Synopsys EDA Tools
· ESD Analysis, with tasks that includes:
· TLP (Transmission Line Pulse) Machine operation
· AirDischarge Simulation (NoiseKen)
· ESD Machine Operation (M7000)
· FIB (Focused Ion Beam) Machine operation
· Licensed Electronics Engineer (Lic. No. 0044147)

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Education
BACHELOR’S DEGREE IN ENGINEERING | MARCH 2008 | DON BOSCO TECHNICAL COLLEGE
· Major: Electronics and Communications
· Completed and Published Thesis: Wireless Scoring System for Fencing using RFID Technology
· http://www.worldacademicunion.com/journal/SSCI/SSCIvol02no02paper03.pdf
· Dean’s List for 2 years (2nd year and 4th year)
· Graduated with Distinction (Overall QPA: 1.97)
Skills & Abilities / Tools used
· Cadence and Synopsys EDA Tools, including
· Virtuoso Schematic Editor (understands and modifies CDFproperties)
· Analog Design Environment
· Verilog-A, Verilog-XL, NC-Verilog
· Simvision and Simcompare
· Cadabra and Liberty NCX (interprets Non-linear delay models)
· Verifault and PowerFault IDDq (development of patterns for Fault and IDDq coverage)
· PowerVolt
· ASCA-ISMO Alpha-SX Tools
· Shell Scripting
· Used in almost ALL development phases; can make tedious tasks faster and error-free
· Developed EDAT (EDS Log Analysis Tool)
· Used to interpret log files and process it to create useful files and tasks, including test summary,DUT Defect Rate,
Fail items according to test parameters and /or BIN, Cp-Cpkcalculation and judgement,etc.
· Test Bench Equipment (Power Supplies, Oscilloscopes, Pattern and Function Generators, DC Supplies,Curve Tracer,
etc.)
· Driving (12 years)
Other Information
· About Me:
· Sports: Boxing, Muay Thai, MMA(W:1, L:0, Draws:0)
· Hobbies: Music (Electric and Bass Guitar, Drums); co-founder of RLDP Music
· Knights of the Altar (retired) – member since 1997,coordinator from 2003 to2008
· Don Bosco ECE Society Auditor (2007-2008)
· Married: 2014,Fathered: 2015