This document is a resume for Brian D. Charron, an ASIC design engineer with over 20 years of experience seeking a new opportunity. It lists his professional strengths such as experience with ASIC implementation, physical layout, timing analysis, signal integrity analysis, and collaboration. It also provides details of his professional experience at Intel, Toshiba, and Digital Equipment Corporation, where he has worked on physical design, packaging, DFT, and simulation of ASICs and SOCs from HDL to GDSII. His education includes a bachelor's degree in computer engineering technology from Northeastern University.
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1. Brian D. Charron Cell: 508-341-9058
6 Drummer Lane Home: 978-466-7734
Leominster, MA 01453 brian.charron62@gmail.com
ASIC Design Engineer with a proven track record of success seeking a new opportunity
to utilize my skills in complex ASIC/SOC implementation.
PROFESSIONAL STRENGTHS
Experienced ASIC Implementer
Detail Oriented /Job Right 1st
Time
HDL Netlist to GDS Successes
Package & Die Selection
IO Ring Layout & Analysis
Chip & Block Level Floorplanning
Chip & Block Level Physical Layout
Clock Tree Synthesis
Process Enhancements
Perl Scripting Innovation
ASIC/SOC Customer Interface
IO Ring ESD Analysis
Manufacturing Checks & Resolution
Static Timing Analysis & Closure
Power Planning & IRdrop Analysis
Test Vector Simulation
SI Analysis & Resolution
DFT Broadside Simulation
IP Test Vectors & Simulation
ECO Innovation
National & International
Collaboration
Consummate Team Player
SoftTools & Programming
- Synopsys Design Compiler,
Primetime, Star-RCXT, Test
Compiler, VCS, ICC Trained
- Mentor Graphics Modelsim/Questa
Core, SystemVerilog Trained
- Cadence Silicon Ensemble,
Conformal LEC & LP, Verilog XL
- Toshiba Apex, ANGELS
- VHDL, Verilog
- Tcl
- Linux tcsh
- C++, C
- Perl Programming
- DOS, MS-WINDOWS
- Emacs Macro Programming
PROFESSIONAL EXPERIENCE
Intel Corporation, Hudson, MA 2/17/2015 – 5/22/2015
Circuit Design Engineer, Intel Federal Division
ASIC Physical Design – block level implementation synthesis through timing closure.
Toshiba America Electronics Components Inc., Marlborough, MA 2012 – 2014
Senior Staff Design Engineer, Marlboro Technology Design Center
Physical Implementation:
Full chip and hierarchical block physical integration with custom and 3rd
party IP
and I/O cells (i.e. PLL, USB, ADC, DAC, ARM, PCI Express (PCIe), DDR,
Serdes, SRAM, DRAM) (40nm, 65nm, 90nm)
Work with customer to vet chip and hierarchical timing constraints
Clock tree insertion and balancing
Multi-mode and multi-corner static timing analysis and closure
ECO implementation
Signal integrity robust techniques & problem resolution
Low Power Partitioning & Analysis
Automated Cadence’s Celtic Signal integrity analysis for use by Design Center
2. Perl scripting to parse log files into usable input for downstream tools and to
extract error and warning messages
Manufacturing checks & problem resolution
Documentation and design review with foundry in Japan
Packaging:
Work with customer to establish die pad layout and package pin out
Interface with Japanese colleagues to procure special I/O cells
Identify simultaneous switching I/O and perform power/ground analysis
Perform package substrate routing and verification and submit prototype to
foundry for implementation
Perl scripting to parse log files into usable input for downstream tools and to
extract error and warning messages
Led peer training for Design Center ESD design analysis methodology
Perform pad ESD analysis to meet HBM, CDM, and MM standards
Documentation and design review with foundry in Japan
DFT & Simulation:
DFT implementation and verification
Serial simulation to verify scan chain setup/hold timing
Test plan documentation
Test bench stimulus, response capture, and problem diagnosis
Parallel simulations to fault grade chip and hierarchical block scan topology
Write test vectors to verify PLL spin up and VCO frequencies
Collaboration
Interface with customer to answer questions and offer solutions
Work with International colleagues on design, internal tool, and IP issues
Work with our EDA group on tools, design flows, and 3rd
party tool issues
Work with 3rd
party tool vendors to resolve technical and tool issues
Toshiba America Electronics Components Inc., Marlborough, MA 2006 – 2012
Staff Design Engineer, Marlboro Technology Design Center
Toshiba America Electronics Components Inc., Marlborough, MA 1999 – 2006
Senior Design Engineer, Marlboro Technology Design Center
(Recipient Toshiba Core Value Award 2004)
Toshiba America Electronics Components Inc., Wakefield, MA 1997 – 1999
Design Engineer II, Boston Technology Design Center
Toshiba America Electronics Components Inc., Wakefield, MA 1996 – 1997
Design Engineer I, Boston Technology Design Center
Digital Equipment Corporation, Marlborough, MA
E.S.T.G ASIC Applications, Consultant Technician
(Recipient Outstanding Performer Award Aug/94)
EDUCATION
Northeastern University Boston, MA
Bachelor’s Degree, Computer Engineering Technology Summa Cum Laude