2. A Basic MIPS Implementation
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We're ready to look at an implementation of the MIPS
Simplified to contain only:
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memory-reference instructions: lw, sw
arithmetic-logical instructions: add, sub, and, or, slt
control flow instructions: beq, j
• Generic Implementation:
– use the program counter (PC) to supply instruction address
– get the instruction from memory
– read registers
– use the instruction to decide exactly what to do
• All instructions use the ALU after reading the registers
Why? memory-reference? arithmetic? control flow?
5.1 Introduction
3. • Memory Reference Instruction uses
the ALU for an Address Calculation.
• ALU Reference Instruction uses the
ALU for the Operation Execution.
• Branch Instruction uses ALU for
Comparison.
4. • A memory Reference Instruction has access the memory
either to read data for a load (or) write data for store.
• An ALU Instruction (or) Load Instruction has to write the
data from ALU (or) memory back in to register.
• Finally for branch instruction, we may need to change the
next instruction address based on the comparison,
otherwise we have to increment the PC by 4 to get the
address of the next instruction.
5. An Overview of the Implementation
• For most instructions: fetch instruction, fetch operands, execute,
store.
•
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Missing Multiplexers, and some Control lines for read and write.
6. 4
An Overview of the Implementation
• The program counter gives the instruction address to the instruction
memory.
• After the instruction is fetched ,the register operands required by an
instruction are specified by fields of that instruction.
Once the register operands have been fetched, they can be used to
compute a memory address( for a load and store), to compute an
arithmetic result( for an integer arithmetic-logical instruction) or a
compare(for a branch).
If the instruction is an arithmetic-logical instruction, the result from the
ALU must be written to a register.
If the operation is a load or store, the ALU result is used as an address to
either store a value from memory into the registers. The result from the
ALU or memory is written back into the register file.
Branches require the use of the ALU output to determine the next
instruction address which comes either from the ALU( where the PC and
branch offset are summed) or from an adder that increments the current
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PC by 4.
7. 5
Continue
• The basic implementation of the MIPS subset including the necessary
multiplexers and control lines.
• Multiplexer (data selector) selects from among several inputs based on
the setting of its control lines. The control lines are set based on
information taken from the instruction being executed.
8. 5.3 Building a Datapath
• Datapath
– Elements that process data and addresses within the CPU
• Register file, ALUs, Adders, Instruction and Data
Memories, …
We need functional units (datapath elements) for:
1. Fetching instructions and incrementing the PC.
2. Execute arithmetic-logical instructions: add, sub, and, or, and slt
3. Execute memory-reference instructions: lw, sw
4. Execute branch/jump instructions: beq, j
1. Fetching instructions and incrementing the PC.
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9. Continue
registers, perform an ALU operation
the registers and write the result
on the contents
to the register.
2. Execute arithmetic-logical instructions: add, sub, and, or, and slt
The arithmetic logic instructions read operands from two
of
So
this instructions as R-type instructions.
add $t1, $t2, $t3 # t1 = t2 + t3
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12. Creating a Single Datapath
• Sharing datapath elements between two different instruction classes ,
we have connected multiple connections to the input of an element and
used a multiplexer and control signals to select among the multiple
inputs.
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13. Continue
Now we con combine all the pieces to make a simple datapath
for the MIPS architecture:
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14. 5.4 A Simple Control Implementation
Scheme
The ALU Control
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22. Why a Single-Cycle Implementation Is Not Used Today
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Example: Performance of Single-Cycle Machines
Calculate cycle time assuming negligible delays except:
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memory (200ps),
ALU and adders (100ps),
register file access (50ps)
Which of the following implementation would be faster:
1. When every instruction operates in 1 clock cycle of fixes length.
2. When every instruction executes in 1 clock cycle using a variable-length
clock.
To compare the performance, assume the following instruction mix:
25% loads
10% stores
45% ALU instructions
15% branches, and
5% jumps
23. 21
Continue
CPU clock cycle (option 1) = 600 ps.
CPU clock cycle (option 2) = 400 45% + 60025% + 550 10% + 350 15% + 2005%
= 447.5 ps.
Performance ratio = 1.34
447.5
600
45% ALU instructions
25% loads
10% stores
15% branches, and
5% jumps
memory (200ps),
ALU and adders (100ps),
register file access (50ps)
24. 5.5 A Multicycle Implementation
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A single memory unit is used for both instructions and data.
There is a single ALU, rather than an ALU and two adders.
One or more registers are added after every major functional unit.
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25. Continue
Replacing the three ALUs of the single-cycle by a single ALU means that the
single ALU must accommodate all the inputs that used to go to the three
different ALUs.
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29. Breaking the Instruction Execution into Clock Cycles
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1. Instruction fetch step
IR <= Memory[PC];
PC <= PC + 4;
30. Breaking the Instruction Execution into Clock Cycles
IR <= Memory[PC];
To do this, we need:
MemRead ➔Assert
IRWrite ➔ Assert
IorD ➔ 0
-------------------------------
PC <= PC + 4;
ALUSrcA ➔ 0
ALUSrcB ➔ 01
ALUOp ➔ 00 (for add)
PCSource ➔ 00
PCWrite ➔ set
The increment of the PC and instruction memory access can occur in parallel, how?
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31. Breaking the Instruction Execution into Clock Cycles
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2. Instruction decode and register fetch step
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Actions that are either applicable to all instructions
Or are not harmful
A <= Reg[IR[25:21]];
B <= Reg[IR[20:16]];
ALUOut <= PC + (sign-extend(IR[15-0] << 2 );
32. A <= Reg[IR[25:21]];
B <= Reg[IR[20:16]];
Since A and B are
overwritten on every
cycle ➔ Done
ALUOut <= PC + (sign-
extend(IR[15-0]<<2);
This requires:
ALUSrcA ➔ 0
ALUSrcB ➔ 11
ALUOp ➔ 00 (for add)
branch target address will
be stored in ALUOut.
The register file access and computation of branch target occur in parallel.
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33. Breaking the Instruction Execution into Clock Cycles
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3. Execution, memory address computation, or branch completion
Memory reference:
ALUOut <= A + sign-extend(IR[15:0]);
Arithmetic-logical instruction:
ALUOut <= A op B;
Branch:
if (A == B) PC <= ALUOut;
Jump:
PC <= { PC[31:28], (IR[25:0], 2’b00) };
34. Memory reference:
ALUOut <= A + sign-extend(IR[15:0]);
ALUSrcA = 1 && ALUSrcB = 10
ALUOp = 00
Arithmetic-logical instruction:
ALUOut <= A op B;
ALUSrcA = 1 && ALUSrcB = 00
ALUOp = 10
Branch:
if (A == B) PC <= ALUOut;
ALUSrcA = 1 && ALUSrcB = 00
ALUOp = 01 (for subtraction)
PCSource = 01
PCWriteCond is asserted
Jump:
PC <= { PC[31:28], (IR[25:0],2’b00) };
PCWrite is asserted
PCSource = 10
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38. Defining the Control
Two different techniques to specify the control:
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Finite state machine
Microprogramming
Example: CPI in a Multicycle CPU
Using the SPECINT2000 instruction mix, which is: 25% load, 10% store, 11%
branches, 2% jumps, and 52% ALU.
What is the CPI, assuming that each state in the multicycle CPU requires 1
clock cycle?
Answer:
The number of clock cycles for each instruction class is the following:
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Load: 5 25%
Stores: 4 10%
ALU instruction: 4 52%
Branches: 3 11%
Jumps: 3 2%
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39. Example Continue
The CPI is given by the following:
CPI
CPU clock cycles
Instruction counti CPIi
Instruction count Instruction count
Instruction count
The ratio
Instruction counti
Instruction count
is simply the instruction frequency for the instruction class i. We can therefore
substitute to obtain:
CPI = 0.255 + 0.104 + 0.524 + 0.113 + 0.023 = 4.12
This CPI is better than the worst-case CPI of 5.0 when all instructions take the
same number of clock cycles.
CPI Instruction counti
i
CPI
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42. Defining the Control (Continue)
• Finite state machine controllers are typically implemented using a
block of combinational logic and a register to hold the current state.
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43. 5.6 Exceptions
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Exceptions
Interrupts
Type of event From where? MIPS terminology
I/O device request
Invoke the operating system from user
program
Arithmetic overflow
Using an undefined instruction
Hardware malfunction
External Interrupt
Internal Exception
Internal
Internal
Either
Exception
Exception
Exception or interrupt
44. How Exception Are Handled
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To communicate the reason for an exception:
1. a status register ( called the Cause register)
2. vectored interrupts
Exception type Exception vector address (in hex)
Undefined instruction
Arithmetic overflow
C000 0000hex
C000 0020hex
45. How Control Checks for Exception
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Assume two possible exceptions:
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Undefined instruction
Arithmetic overflow
