This document describes a project to implement a configurable system with two processors, a RISC and CISC processor, in an FPGA. The RISC processor has 30 instructions and the CISC has 244. It will come with a programming and monitoring interface. The goal is to illustrate the structure and operation of CPUs and allow students to learn computer architecture fundamentals. The project files will be made available online for others to use and expand.

1. ISCKER
Reduced/Complex Instruction Set Computing
Key Educational Resource
Authors:
A. Gualdrón and J. P. Pinilla
Director:
A. Retamoso
Reconfigurable Platform for the Emulation of RISC and CISC Architectures
This is a project planned to illustrate the structure and
operational foundations of Central Processing Units,
through the implementation of a configurable system
with two processors, one RISC (Reduced Instruction
Set Computing) and one CISC(Complex Instruction Set
Computing), described in Verilog for FPGA (Field
Programmable Gate Array), along with a programming
and monitoring user interface software.
ISCKER ISCKER
Instruction OBSERVER
u - I n st r u ct ion
FSM Control Opcode
D D e code r
M AR A
Instruction
Memory
Register A CCA A CCB
File
RG0
PC
A
PROGRAMMER M e m or y A CCD
RG1
D MM
SP
WD D a t a pa t h
Output Port Datapath
A PC
I/O RC ALU D
Unit Result
Tmr1 SP
Tmr2
Data
Input Port Memory I/O IX
Unit Ou t p u t Po r t
ALU Result
I n p u t Po r t CCR
WriteData
WD Tm r 1
Tm r 2
H I N Z V C
MemData
Features RISCKER CISCKER Altera Cyclone IV: EP4CE22 Resources
# of Instructions 30 244
# of Registers 64 4 Platform Resources Used Available Percentage
ALU 16 bits 16bits Total LE 1,436 6%
Memory Architecture Harvard Von Neumann CISCKER Combinational 1,388 6%
Instructions Size Fixed: 16-bits Variable: 8 to 24-bits Registers 362 2%
MUL & DIV Hardware units Iterative Total LE 2,750 12%
Logic, Arithmetic and Rotation 1 bit Logic, Arithmetic and
Shift Operations RISCKER Combinational 2,428 11%
Barrel Shifts. Rotation Shifts.
Registers 1,089 5%
Addressing Modes Immediate,Direct, Indirect,Offset INH,REL,IMM,DIR,EXT,IX,IX+ 22,320
Total LE 2,173 10%
Addressable Memory 65536x32bits 65536x16bits 65536x16bits CISCKER
Combinational 2,062 9%
# of Branch Conditions 2 14 Observer
Timers 2 x 16 bits 2 x 16 bits Registros 832 4%
2 by Timer 2 by Timer Total LE 3,436 15%
Interruptions RISCKER
2 External 2 External Combinational 3,140 14%
Observer
Control Unit Type HCU MCU Registers 1,643 7%
Similar Architectures MIPS HC08 and HC11 Freescale
The X-ISCKER platform delivers the Verilog HDL description of two processors, an IDE
software and the documentation that will allow new learners to familiarize with computer
architecture foundations, and computer designers to come up with custom embedded
processor solutions to their applications.
The source files for the X-ISCKER platform and related further development
will be kept available at the ADT (Advanced Digital Technologies) students’
research group of the UPB website.
http:/semilleroadt.upbbga.edu.co/xiscker