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An LTE PHY for Catapult
             Communications


             Catapult Communications is a leader in the field of Network Test Equipment.
             Catapult’s products are used around the world to test developments and
             implementations of advanced digital communications systems. Catapult’s latest
             product is the patent-pending LTE User Equipment (UE) Simulator, the t600
             platform, equipped with the LTE UE Sector Card Sets, that work as a peripheral
             platform to the Catapult DCT2000®. This platform uses a Physical Layer
             interface to connect to the target eNode B.




Case study
Figure: 1
                             Standards

                                                                  Test vectors


                            Architecture




                                               IP Cores                 Control




                                         DSP                     Signal Chains
                                                                                             Test
                                                                                             And
                                                                                          Integrate
                                      FPGA                       Signal Chains



                                               IP Cores            Interface Control




                PA worked with Catapult to devise the most effective solution. The requirements
                included fast development, high throughput, flexibility for performance and upgrade
                and effective interfaces to the higher layers of the test system and to the target
                unit-under-test.


                PA carried out a 6 week design study, aiming to plan an effective architecture,
                which could meet all these requirements and could deliver a program with minimum
                project risk and optimised costs.


                Architecture
                The selected architecture uses a mixture of DSP and FPGA, built within a µTCA
                chassis. The µTCA approach gives great flexibility and granularity, permitting later
                system enhancements and easy field maintenance. The DSP FPGA split reflects the
                nature of the LTE system. Intensive front end signal processing ( FFT, iDFT, Turbo etc)
                is handled in the FPGA while the DSP runs upper PHY functions, and all the control
                plane activities.


                The architecture presents Catapult with the greatest flexibility, both in the system build
                (where extra cards can be used to increase capacity) and in the development process
                (where functional testing is simplified by the distributed approach).


                Development Program
                PA’s development program used a small dedicated team of communications professionals
                specialising in the rapid development of complex systems. The team shared design
                decisions and worked to minimise development risk and maximise productivity, through
                agile development methods and a highly parallel set of development tasks.
“ PA’s role in the development of our LTE test system has been a great help in
                         meeting our overall objectives. Their approach to fast-track development has
                         been outstanding, and has delivered an LTE PHY right on time.”
                         Kalyan Sundhar,
                         Catapult’s VP Engineering




                                                                                 Reset from FiNE(TBC)                                                   On-board LEDs

                                     FPGA Top Level
              On-board
             oscillator(s)                                                                                                                                                                                  D/L (Rx) Signal Chain Wrapper

                                                                                                                                                                                                              D/L (Rx) Signal Chain
                                               Clock                                                                                                     Debug LED
                                                                                                             Reset Control
                                             Generation                                                                                                    driver




                                                   PLL Locked
                                                                                                                                                                                                                                                                                       Common         Memory
                                                                                                                                                                                                                 Input Buffer         Output Buffer   IRQ I/O
                                                                                                                                                                                                                                                                                      Register File   Interface



                                             Async. Serial (debug messaging )
                             RS232




                                                                                                                                                                                                                                                                                                                                                     DDR2
                                                                                                                                                                                                                                                                                                                                 DDR2
                              Phy
           RS-232
           header




                                                                                                                                                                                                                                                                                                                                                     Bank 0
                                                                                                                                                                                                                                                                                                                                Controller


                                          Interface/Control Wrapper


                                                                                                                                                                                                                                                                                                                             Version Block
                                                                                                                                                                                                                                                                                                                             (auto-updated)
                                                                                                                                                                                                                                                                System Interconnect
                                                                    Doorbell
                                                                     Slave




                                                                                     Doorbell
                                                                                                                                                                  Nios Subsystem




                                                                                      IRQ

                                                                                                                                                                                                                                                                                                       Register File
                                                                                                                                  System Interconnect
                                                                    Sys. Mnt.




                                                                                                                                                                                                                                                                                                                            Test Mux. Cfg.
                                                                     Slave




           Backplane 4x sRIO
                                                   sRIO Endpoint




                                                                                                                                                                                                                                                                                                                            Resets
                                                                                                                                                                Register
                                                                                                                                                                                               Decode




                                                                                                                                                                 File
                                                                                  Fast System Interconnect
                                                                    IO Write




                                                                                                                                                                                   Control
                                                                     Master




                                                                                                                    Message                                      Ext.
                                                                                                                     Queue                                      Bridge



                                                                                                                                                                                   I/O Write
                                                                    IO Read
                                                                     Master




                                                                                                                                                                                               Decode/Mux




                                                                                                                                                                                   I/O Read


LA Breakout Mezzanine
                                                                                                                                                                                                                                                                                                                                                     DDR2
                                                                                                                                                                                                                                                                                                                            DDR2 Controller
                                                                                                                                                                                                                                                                                                                                                     Bank 1
  Mictor




                         Mezzanine
           Mezzanine




                         Connector
           Connector




                                                                                                                                                                                                                                                                                       Common         Memory
                                                                                                                                                                                                                 Input Buffer         Output Buffer   IRQ I/O
                                                                                                                                                                                                                                                                                      Register File   Interface
                                                                   Test Multiplexer                                           Config.
  Mictor




                                                                                                                                                                                                              U/L (Tx) Signal Chain




                                                                    Test Nodes                                                                                                                              U/L (Tx) Signal Chain Wrapper


                                                                                                                                                                                                                                                                                                                       Signal Chain FPGA Top Level
                                      Key                                                                                                                                                                                                                                                                                    ETS -08 -0102 -D_A 1
                                                       Avalon MM Data Plane(fast)                                               Avalon MM Control Plane(slow)




                                                                                                                        The work was able to draw on key supporting IP elements from leading silicon vendors
                                                                                                                        – Freescale and Altera. The Freescale 8144 processor provides a high performance
                                                                                                                        system, with quad-core DSPs delivering 16,000 16-bit MMACS per device. The Altera
                                                                                                                        EP2S130 offers a super high density array, supported by key IP blocks suitable for the
                                                                                                                        OFDM environment.


                                                                                                                        The program has gone from start to a customer-delivered operational PHY in less than
                                                                                                                        10 months. PA has provided Catapult with access to early versions of the system in order
                                                                                                                        to allow the system integration to proceed in parallel. Joint integration has taken place,
                                                                                                                        using common test vectors, and leading to a reliable, well understood platform. PA has
                                                                                                                        helped transfer PHY level knowledge to Catapult to enable design evolution.
“PA’s assistance has been vital for Catapult to deliver
 our LTE Test solution to customers on time. PA has
 shown excellent understanding of LTE technology
 and been responsive to our needs.”
 James Rankin,
 Catapult’s LTE Product manger




Standards and functions
The work has tracked the LTE standards, with upgrades to account for 3GPP
Release 8 May, June, September and December 2008 documents (an upgrade to
version 8.5 is in development). The code has been enhanced to provide various
                                                                                       Corporate headquarters
levels of instrumentation and control, to allow additional modes of operation of the   123 Buckingham Palace Road
final test system.                                                                     London SW1W 9SR
                                                                                       United Kingdom
                                                                                       Tel:    +44 20 7730 9000
Benefits for Catapult                                                                  Fax: +44 20 7333 5050
                                                                                       E-mail: info@paconsulting.com
The work has allowed Catapult to make a major move into a new and fast moving
market sector. The PA team has injected a breadth of knowledge of LTE and its          Cambridge Technology
                                                                                       Centre
operation and has enabled the Catapult team to concentrate on core business
                                                                                       Melbourn
– the higher layer testing methodology, built upon their proven DCT2000 test system.   Herts SG8 6DP
                                                                                       Tel:   +44 1763 261222
                                                                                       Fax: +44 1763 260023
                                                                                       Contact: John O’Neill

                                                                                       www.paconsulting.com

                                                                                       PA Consulting Group is a
                                                                                       leading management, systems
                                                                                       and technology consulting firm,
                                                                                       operating worldwide in more
                                                                                       than 35 countries.

                                                                                       For more information on
                                                                                       PA’s wireless offering,
                                                                                       please visit
                                                                                       www.paconsulting.com/
                                                                                       wireless

                                                                                       Principal national offices in
                                                                                       Argentina, China, Denmark,
                                                                                       Germany, India, Ireland,
                                                                                       Malaysia, The Netherlands,
                                                                                       New Zealand, Norway,
                                                                                       Sweden, United Arab Emirates,
                                                                                       United Kingdom, United States

DCT2000 and the Catapult logo are registered trademarks
                                                                                       © PA Knowledge Limited 009.
of Catapult Communications Corporation.                                                  All rights reserved.
                                                                                       00667-20

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PA Develops an LTE PHY for Catapult

  • 1. An LTE PHY for Catapult Communications Catapult Communications is a leader in the field of Network Test Equipment. Catapult’s products are used around the world to test developments and implementations of advanced digital communications systems. Catapult’s latest product is the patent-pending LTE User Equipment (UE) Simulator, the t600 platform, equipped with the LTE UE Sector Card Sets, that work as a peripheral platform to the Catapult DCT2000®. This platform uses a Physical Layer interface to connect to the target eNode B. Case study
  • 2. Figure: 1 Standards Test vectors Architecture IP Cores Control DSP Signal Chains Test And Integrate FPGA Signal Chains IP Cores Interface Control PA worked with Catapult to devise the most effective solution. The requirements included fast development, high throughput, flexibility for performance and upgrade and effective interfaces to the higher layers of the test system and to the target unit-under-test. PA carried out a 6 week design study, aiming to plan an effective architecture, which could meet all these requirements and could deliver a program with minimum project risk and optimised costs. Architecture The selected architecture uses a mixture of DSP and FPGA, built within a µTCA chassis. The µTCA approach gives great flexibility and granularity, permitting later system enhancements and easy field maintenance. The DSP FPGA split reflects the nature of the LTE system. Intensive front end signal processing ( FFT, iDFT, Turbo etc) is handled in the FPGA while the DSP runs upper PHY functions, and all the control plane activities. The architecture presents Catapult with the greatest flexibility, both in the system build (where extra cards can be used to increase capacity) and in the development process (where functional testing is simplified by the distributed approach). Development Program PA’s development program used a small dedicated team of communications professionals specialising in the rapid development of complex systems. The team shared design decisions and worked to minimise development risk and maximise productivity, through agile development methods and a highly parallel set of development tasks.
  • 3. “ PA’s role in the development of our LTE test system has been a great help in meeting our overall objectives. Their approach to fast-track development has been outstanding, and has delivered an LTE PHY right on time.” Kalyan Sundhar, Catapult’s VP Engineering Reset from FiNE(TBC) On-board LEDs FPGA Top Level On-board oscillator(s) D/L (Rx) Signal Chain Wrapper D/L (Rx) Signal Chain Clock Debug LED Reset Control Generation driver PLL Locked Common Memory Input Buffer Output Buffer IRQ I/O Register File Interface Async. Serial (debug messaging ) RS232 DDR2 DDR2 Phy RS-232 header Bank 0 Controller Interface/Control Wrapper Version Block (auto-updated) System Interconnect Doorbell Slave Doorbell Nios Subsystem IRQ Register File System Interconnect Sys. Mnt. Test Mux. Cfg. Slave Backplane 4x sRIO sRIO Endpoint Resets Register Decode File Fast System Interconnect IO Write Control Master Message Ext. Queue Bridge I/O Write IO Read Master Decode/Mux I/O Read LA Breakout Mezzanine DDR2 DDR2 Controller Bank 1 Mictor Mezzanine Mezzanine Connector Connector Common Memory Input Buffer Output Buffer IRQ I/O Register File Interface Test Multiplexer Config. Mictor U/L (Tx) Signal Chain Test Nodes U/L (Tx) Signal Chain Wrapper Signal Chain FPGA Top Level Key ETS -08 -0102 -D_A 1 Avalon MM Data Plane(fast) Avalon MM Control Plane(slow) The work was able to draw on key supporting IP elements from leading silicon vendors – Freescale and Altera. The Freescale 8144 processor provides a high performance system, with quad-core DSPs delivering 16,000 16-bit MMACS per device. The Altera EP2S130 offers a super high density array, supported by key IP blocks suitable for the OFDM environment. The program has gone from start to a customer-delivered operational PHY in less than 10 months. PA has provided Catapult with access to early versions of the system in order to allow the system integration to proceed in parallel. Joint integration has taken place, using common test vectors, and leading to a reliable, well understood platform. PA has helped transfer PHY level knowledge to Catapult to enable design evolution.
  • 4. “PA’s assistance has been vital for Catapult to deliver our LTE Test solution to customers on time. PA has shown excellent understanding of LTE technology and been responsive to our needs.” James Rankin, Catapult’s LTE Product manger Standards and functions The work has tracked the LTE standards, with upgrades to account for 3GPP Release 8 May, June, September and December 2008 documents (an upgrade to version 8.5 is in development). The code has been enhanced to provide various Corporate headquarters levels of instrumentation and control, to allow additional modes of operation of the 123 Buckingham Palace Road final test system. London SW1W 9SR United Kingdom Tel: +44 20 7730 9000 Benefits for Catapult Fax: +44 20 7333 5050 E-mail: info@paconsulting.com The work has allowed Catapult to make a major move into a new and fast moving market sector. The PA team has injected a breadth of knowledge of LTE and its Cambridge Technology Centre operation and has enabled the Catapult team to concentrate on core business Melbourn – the higher layer testing methodology, built upon their proven DCT2000 test system. Herts SG8 6DP Tel: +44 1763 261222 Fax: +44 1763 260023 Contact: John O’Neill www.paconsulting.com PA Consulting Group is a leading management, systems and technology consulting firm, operating worldwide in more than 35 countries. For more information on PA’s wireless offering, please visit www.paconsulting.com/ wireless Principal national offices in Argentina, China, Denmark, Germany, India, Ireland, Malaysia, The Netherlands, New Zealand, Norway, Sweden, United Arab Emirates, United Kingdom, United States DCT2000 and the Catapult logo are registered trademarks © PA Knowledge Limited 009. of Catapult Communications Corporation. All rights reserved. 00667-20