Enea Linux Base Station Platform FTF ChinaEneaSoftware
Enea Linux provide a high performance implementation targeting both macro/micro cells and small cells that are based on Freescale QorIQ and StarCore devices as well as the new OorIQ Qonverge SoC series platforms (BSC, B series, and G series). The Enea Linux Base Station Platform provides a superior foundation for base station equipment manufacturers to add the LTE/HSPA protocols of their choice. The unique value of the Enea Linux Base Station Platform offering over others is in the underlying implementation that features many innovations for performance and scalability: a) a novel Linux Light-weight Threading (LWT) model and interrupt handling that offers 10x the performance of Linux pthreads and real-time preemption patch in Linux user space, and b) Enea PAX - Packet Acceleration Foundation, that offers superior packet processing performance with exceptional configuration and programmability.
Re usable continuous-time analog sva assertions - slidesRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
Enea Linux Base Station Platform FTF ChinaEneaSoftware
Enea Linux provide a high performance implementation targeting both macro/micro cells and small cells that are based on Freescale QorIQ and StarCore devices as well as the new OorIQ Qonverge SoC series platforms (BSC, B series, and G series). The Enea Linux Base Station Platform provides a superior foundation for base station equipment manufacturers to add the LTE/HSPA protocols of their choice. The unique value of the Enea Linux Base Station Platform offering over others is in the underlying implementation that features many innovations for performance and scalability: a) a novel Linux Light-weight Threading (LWT) model and interrupt handling that offers 10x the performance of Linux pthreads and real-time preemption patch in Linux user space, and b) Enea PAX - Packet Acceleration Foundation, that offers superior packet processing performance with exceptional configuration and programmability.
Re usable continuous-time analog sva assertions - slidesRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
Abstract: Design verification is an essential step in the development of any product. It ensures that the product as designed is the same as the product as intended. Software simulation is the common approach for validating hardware design unfortunately, it will take hours together to execute. Difficulties in validation arise due to the complexity of the design and also due to the lack of on chip observability. One common solution to this problem is to instrument the prototype using trace-buffers to record a subset of internal signals into on-chip memory for subsequent analysis. In the proposed system, an example circuit is implemented to perform the tracing operation and various trace buffers are designed to record the different stages of internal signal states. The resulting signal states are to be stored, like a error outputs. Low power methodologies are also implemented to achieve low power consumption. Thus the errors are separately stored in the memory for analyzing the signals. This might be used for changes in the logic wherever needed. Thus this tracing is performed to monitor signal states of an FPGA.
https://www.corelis.com/education/tutorials/jtag-tutorial/what-is-jtag/
JTAG allows for the testing and programming of digital and analog circuits, including microprocessors, memory devices, and other digital and mixed-signal components.
#JTAG
One of the key benefits of JTAG is that it provides access to the internal circuitry of a device without the need for additional hardware such as a test probe or emulator. This is possible because JTAG uses a series of test access ports (TAPs) that are built into a device's boundary-scan architecture.
IRJET- A Review- FPGA based Architectures for Image Capturing Consequently Pr...
PA Develops an LTE PHY for Catapult
1. An LTE PHY for Catapult
Communications
Catapult Communications is a leader in the field of Network Test Equipment.
Catapult’s products are used around the world to test developments and
implementations of advanced digital communications systems. Catapult’s latest
product is the patent-pending LTE User Equipment (UE) Simulator, the t600
platform, equipped with the LTE UE Sector Card Sets, that work as a peripheral
platform to the Catapult DCT2000®. This platform uses a Physical Layer
interface to connect to the target eNode B.
Case study
2. Figure: 1
Standards
Test vectors
Architecture
IP Cores Control
DSP Signal Chains
Test
And
Integrate
FPGA Signal Chains
IP Cores Interface Control
PA worked with Catapult to devise the most effective solution. The requirements
included fast development, high throughput, flexibility for performance and upgrade
and effective interfaces to the higher layers of the test system and to the target
unit-under-test.
PA carried out a 6 week design study, aiming to plan an effective architecture,
which could meet all these requirements and could deliver a program with minimum
project risk and optimised costs.
Architecture
The selected architecture uses a mixture of DSP and FPGA, built within a µTCA
chassis. The µTCA approach gives great flexibility and granularity, permitting later
system enhancements and easy field maintenance. The DSP FPGA split reflects the
nature of the LTE system. Intensive front end signal processing ( FFT, iDFT, Turbo etc)
is handled in the FPGA while the DSP runs upper PHY functions, and all the control
plane activities.
The architecture presents Catapult with the greatest flexibility, both in the system build
(where extra cards can be used to increase capacity) and in the development process
(where functional testing is simplified by the distributed approach).
Development Program
PA’s development program used a small dedicated team of communications professionals
specialising in the rapid development of complex systems. The team shared design
decisions and worked to minimise development risk and maximise productivity, through
agile development methods and a highly parallel set of development tasks.
3. “ PA’s role in the development of our LTE test system has been a great help in
meeting our overall objectives. Their approach to fast-track development has
been outstanding, and has delivered an LTE PHY right on time.”
Kalyan Sundhar,
Catapult’s VP Engineering
Reset from FiNE(TBC) On-board LEDs
FPGA Top Level
On-board
oscillator(s) D/L (Rx) Signal Chain Wrapper
D/L (Rx) Signal Chain
Clock Debug LED
Reset Control
Generation driver
PLL Locked
Common Memory
Input Buffer Output Buffer IRQ I/O
Register File Interface
Async. Serial (debug messaging )
RS232
DDR2
DDR2
Phy
RS-232
header
Bank 0
Controller
Interface/Control Wrapper
Version Block
(auto-updated)
System Interconnect
Doorbell
Slave
Doorbell
Nios Subsystem
IRQ
Register File
System Interconnect
Sys. Mnt.
Test Mux. Cfg.
Slave
Backplane 4x sRIO
sRIO Endpoint
Resets
Register
Decode
File
Fast System Interconnect
IO Write
Control
Master
Message Ext.
Queue Bridge
I/O Write
IO Read
Master
Decode/Mux
I/O Read
LA Breakout Mezzanine
DDR2
DDR2 Controller
Bank 1
Mictor
Mezzanine
Mezzanine
Connector
Connector
Common Memory
Input Buffer Output Buffer IRQ I/O
Register File Interface
Test Multiplexer Config.
Mictor
U/L (Tx) Signal Chain
Test Nodes U/L (Tx) Signal Chain Wrapper
Signal Chain FPGA Top Level
Key ETS -08 -0102 -D_A 1
Avalon MM Data Plane(fast) Avalon MM Control Plane(slow)
The work was able to draw on key supporting IP elements from leading silicon vendors
– Freescale and Altera. The Freescale 8144 processor provides a high performance
system, with quad-core DSPs delivering 16,000 16-bit MMACS per device. The Altera
EP2S130 offers a super high density array, supported by key IP blocks suitable for the
OFDM environment.
The program has gone from start to a customer-delivered operational PHY in less than
10 months. PA has provided Catapult with access to early versions of the system in order
to allow the system integration to proceed in parallel. Joint integration has taken place,
using common test vectors, and leading to a reliable, well understood platform. PA has
helped transfer PHY level knowledge to Catapult to enable design evolution.