This document describes the architectural features and peripheral functions of the PIC16F873 microcontroller. It discusses the microcontroller core, which uses a Harvard architecture with separate program and data memory. It then describes the peripheral features including timers, I/O ports, serial communication interfaces, and analog-to-digital converter. Diagrams are included showing the memory map, pin configuration, and block diagrams of timers and serial communication modules. The document provides a detailed overview of the capabilities and operation of the PIC16F873 microcontroller.
This very short document does not contain enough substantive information to summarize in 3 sentences or less. It contains only a few words that do not provide any clear meaning or context.
This document provides an overview of a webinar on digital signal processing. It introduces the presenter, Dr. Steve Mackay, and provides instructions for interacting during the webinar. It then gives brief biographical information about Dr. Mackay. The remainder of the document outlines key topics to be covered, including definitions of digital and analog signals, applications of DSP, sampling theory, and analog to digital conversion. Diagrams are provided to illustrate various DSP concepts and systems.
A PLL consists of a phase detector, filter, voltage controlled oscillator (VCO), and optional divider. The phase detector compares the phase of the input signal to the VCO output signal and generates an error voltage. The filter smooths the error voltage which is fed to the VCO. The VCO then adjusts its output frequency according to the error voltage to minimize the phase difference between its output and the input signal. An optional divider may be included to scale the VCO output frequency before feeding it back to the phase detector for comparison to the input signal. In this way, the PLL is able to lock its output phase to the input phase or some multiple of the input phase.
Digital Signal Processing Lab Manual ECE studentsUR11EC098
This document describes a MATLAB program to perform operations on discrete-time signals. It discusses amplitude manipulation operations like amplification, attenuation, and amplitude reversal. Time manipulation operations covered include time shifting and time reversal. It also describes adding and multiplying two discrete signals. The program takes user input, performs the selected operations, and plots the output waveforms to verify results.
Ec8491 CT - Unit 1 - Single Sideband Suppressed Carrier (SSB-SC)NimithaSoman
This document discusses amplitude modulation and single sideband modulation. It provides details on:
1) Phase relationships between waveforms, including in-phase and out-of-phase signals.
2) The mathematical representations of an AM wave and how it is generated by modulating a carrier signal with a message signal.
3) How single sideband suppression carrier (SSB-SC) is derived from the power distribution of an AM wave and the frequency spectrum and phasor diagram of an SSB-SC signal.
4) Different methods for generating an SSB signal including filter methods, phase discrimination/phase shift methods, and Weaver's method. Advantages and disadvantages of each approach are covered.
Digital signal processing is a specialized microprocessor with its architecture optimized for operational needs of digital signal processing
Application's of DSP like STFT and Wavelet transform has been explained in detail with images.
This document discusses the Foster-Seeley phase discriminator, which is a type of frequency discriminator used in FM receivers. It operates by comparing the phase difference between primary and secondary voltages in a transformer tuned to the center frequency. When the input frequency matches the center frequency, the phase difference is 90 degrees and the output is zero. If the input frequency increases or decreases from center, the phase difference changes and a positive or negative output voltage is produced, making it useful for demodulating FM signals. The Foster-Seeley discriminator provides good linearity but requires a transformer and limiter before it.
This very short document does not contain enough substantive information to summarize in 3 sentences or less. It contains only a few words that do not provide any clear meaning or context.
This document provides an overview of a webinar on digital signal processing. It introduces the presenter, Dr. Steve Mackay, and provides instructions for interacting during the webinar. It then gives brief biographical information about Dr. Mackay. The remainder of the document outlines key topics to be covered, including definitions of digital and analog signals, applications of DSP, sampling theory, and analog to digital conversion. Diagrams are provided to illustrate various DSP concepts and systems.
A PLL consists of a phase detector, filter, voltage controlled oscillator (VCO), and optional divider. The phase detector compares the phase of the input signal to the VCO output signal and generates an error voltage. The filter smooths the error voltage which is fed to the VCO. The VCO then adjusts its output frequency according to the error voltage to minimize the phase difference between its output and the input signal. An optional divider may be included to scale the VCO output frequency before feeding it back to the phase detector for comparison to the input signal. In this way, the PLL is able to lock its output phase to the input phase or some multiple of the input phase.
Digital Signal Processing Lab Manual ECE studentsUR11EC098
This document describes a MATLAB program to perform operations on discrete-time signals. It discusses amplitude manipulation operations like amplification, attenuation, and amplitude reversal. Time manipulation operations covered include time shifting and time reversal. It also describes adding and multiplying two discrete signals. The program takes user input, performs the selected operations, and plots the output waveforms to verify results.
Ec8491 CT - Unit 1 - Single Sideband Suppressed Carrier (SSB-SC)NimithaSoman
This document discusses amplitude modulation and single sideband modulation. It provides details on:
1) Phase relationships between waveforms, including in-phase and out-of-phase signals.
2) The mathematical representations of an AM wave and how it is generated by modulating a carrier signal with a message signal.
3) How single sideband suppression carrier (SSB-SC) is derived from the power distribution of an AM wave and the frequency spectrum and phasor diagram of an SSB-SC signal.
4) Different methods for generating an SSB signal including filter methods, phase discrimination/phase shift methods, and Weaver's method. Advantages and disadvantages of each approach are covered.
Digital signal processing is a specialized microprocessor with its architecture optimized for operational needs of digital signal processing
Application's of DSP like STFT and Wavelet transform has been explained in detail with images.
This document discusses the Foster-Seeley phase discriminator, which is a type of frequency discriminator used in FM receivers. It operates by comparing the phase difference between primary and secondary voltages in a transformer tuned to the center frequency. When the input frequency matches the center frequency, the phase difference is 90 degrees and the output is zero. If the input frequency increases or decreases from center, the phase difference changes and a positive or negative output voltage is produced, making it useful for demodulating FM signals. The Foster-Seeley discriminator provides good linearity but requires a transformer and limiter before it.
Describes Signal Processing in Radar Systems,
For comments please contact me at solo.hermelin@gmail.com.
For more presentations on different subjects visit my website at http://solohermelin.com.
I recommend to see the presentation on my website under RADAR Folder, Signal Processing Subfolder.
This document discusses the history and types of radio receivers. It describes how the earliest radio receiver was created in 1896 by Alexander Popov and was based on Maxwell's discovery of electromagnetic waves. There are three main types of receivers discussed - crystal radios, tuned radio frequency receivers, and superheterodyne receivers. Crystal radios require no power source beyond the radio waves themselves, while tuned radio frequency receivers have individually tuned amplifier stages and superheterodyne receivers mix signals to extract an intermediate frequency. The document also covers frequency ranges, sensitivity, selectivity and how radio waves propagate.
The operational amplifier (op-amp) is an integrated circuit that can provide voltage gain and be used as a signal amplifier or comparator. It has high input resistance, virtually infinite voltage gain, and two inputs - inverting and non-inverting - and one output. Common op-amp configurations include the inverting amplifier, non-inverting amplifier, summing amplifier, and comparator. The op-amp is a versatile active component used in various circuit applications.
Digital frequency meters can measure frequencies from 10 Hz to 12.5 MHz with sensitivities as low as 100 mV rms. They contain input amplifiers, pulse-forming circuits, and cascaded ring counting units to count input pulses and display the frequency digitally. Errors may occur due to quantization effects, time base inaccuracies, and trigger noise. Applications include frequency counting, precision radar measurements, and transducer-based physical measurements like speed, pressure, temperature and more.
The document discusses several types of specialized oscilloscopes:
1. Delayed time base oscilloscopes allow studying all parts of a pulse waveform by delaying the signal to the vertical plates. This ensures no part of the waveform is lost.
2. Analog storage oscilloscopes can retain an image for longer periods through mesh or phosphor storage techniques, allowing viewing of very low frequency waveforms.
3. Sampling oscilloscopes use a staircase-ramp generator to take samples that are displayed as the beam moves across the screen. Synchronization ensures sampling is timed with the input signal frequency.
4. Digital storage oscilloscopes digitize the input signal using an analog-to-
This document discusses an RFID-based e-passport system. It describes how e-passports contain an integrated RFID chip that stores the same data visible on the passport, including a unique identification number. This allows border agents to verify passport information quickly by scanning the chip without physically examining the document. The objectives are to analyze advantages of e-passports, recommend improvements to existing passports, and design an RFID passport system prototype.
Bipolar junction transistor : Biasing and AC AnalysisTahmina Zebin
1. The document discusses various transistor amplifier circuit designs and analysis techniques, including biasing circuits like base bias, voltage divider bias, and emitter feedback bias.
2. It introduces the small-signal h-parameter transistor model that represents the transistor under AC conditions and defines terms like small-signal current gain and output conductance.
3. The document provides examples of calculating Q-points, load lines, and biasing component values for different transistor amplifier circuits.
The document discusses programming the 8051 microcontroller. It can be programmed using low-level assembly language or high-level languages like C. Assembly language code is faster but more difficult to write and less portable, while C code is easier but slower. The document provides examples of adding two numbers in both C and assembly. It also discusses the 8051 instruction set, addressing modes, subroutines, and arithmetic operations.
1. The document discusses digital signal processing and z-transforms. It provides examples of calculating z-transforms for different sequences, including exponential sequences, sums of sequences, and finite length sequences.
2. It also covers properties of the region of convergence for z-transforms, and methods for calculating the inverse z-transform, including inspection of z-transform pairs and using partial fraction expansions.
3. The examples help illustrate how to use z-transforms to analyze discrete-time signals and systems.
This document discusses digital filter design methods. It introduces IIR and FIR filters and their design techniques. The key methods covered are:
1. IIR filter design using impulse invariance, which samples the impulse response of an analog filter to obtain the discrete-time filter.
2. IIR filter design using bilinear transformation, which maps the continuous s-domain to the discrete z-domain to avoid aliasing.
3. FIR filter design using frequency sampling, which designs a linear phase FIR filter by sampling the desired frequency response and taking the inverse DFT.
Nyquist criterion for distortion less baseband binary channelPriyangaKR1
binary transmission system
From design point of view – frequency response of the channel and transmitted pulse shape are specified; the frequency response of the transmit and receive filters has to be determined so as to reconstruct [bk]
This document provides an overview of signals and systems. It defines key terms like signal, system, continuous and discrete time signals, analog and digital signals, periodic and aperiodic signals. It also discusses different types of signals like deterministic and probabilistic signals, energy and power signals. The document then classifies systems as linear/nonlinear, time-invariant/variant, causal/non-causal, and with/without memory. It provides examples of different signals and properties of signals like magnitude scaling, time shifting, reflection and scaling. Overall, the document introduces fundamental concepts in signals and systems.
Analog Electronics interview and viva questions.pdfEngineering Funda
1. The document contains 50 questions and answers related to analog electronics viva questions covering topics like operational amplifiers, integrated circuits, sample and hold circuits, and more.
2. It provides definitions and explanations of key terms like input offset voltage, common mode rejection ratio, slew rate, and open and closed loop configurations of op-amps.
3. The questions are asked by Engineering Funda YouTube channel professor Hitesh Dholakiya and cover concepts tested in analog electronics viva exams.
The document summarizes the key functions of the telemetry, tracking and command (TT&C) subsystem of a satellite. It discusses how TT&C provides vital communication between the satellite and ground stations by (1) monitoring the satellite's status and measurements through telemetry, (2) sending commands from the ground to control satellite functions, and (3) tracking the satellite's location through antenna positioning and Doppler effect measurements. The TT&C subsystem receives commands from and provides data to the satellite's command and data handling system and performs autonomous operations like antenna pointing and fault recovery.
This document discusses vestigial sideband (VSB) modulation. VSB modulation is a compromise between single sideband (SSB) and double sideband suppressed carrier (DSB-SC) modulation that overcomes some of the drawbacks of SSB. In VSB, one sideband and a vestige of the other sideband are transmitted together, requiring less bandwidth than DSB but more than SSB. VSB modulation is commonly used for television signal transmission to reduce the bandwidth requirement compared to DSB.
Double Side band Suppressed carrier (DSB-SC) Modulation and Demodulation.SAiFul IslAm
This document describes an experiment on double sideband suppressed carrier (DSB-SC) modulation and demodulation performed by electrical engineering students at the University of Asia Pacific. The objectives were to observe DSB-SC modulation using an MC1496 modulator and examine synchronous demodulation of DSB-SC signals. The experiment involved generating a message signal, carrier signal, and DSB-SC modulated signal. A balanced modulator was used to produce the DSB-SC signal. Synchronous demodulation using a balanced multiplier, low-pass filter, and same carrier signal as the modulator recovered the original message signal from the DSB-SC signal. The students observed input and output waveforms and discussed the circuit connections and results
Signals can be classified as continuous-time or discrete-time. Continuous-time signals have a value for all points in time, while discrete-time signals have values only at specific sample points. Common elementary signals include unit step, unit impulse, sinusoidal, and exponential functions. Signals can be further classified based on properties like periodicity, even/odd symmetry, and energy/power. Operations like time shifting, scaling, and inversion can be performed on signals. Discrete-time signals are often obtained by sampling continuous-time signals.
This document contains a question bank with two mark questions and answers related to signals and systems. Some key topics covered include:
- Definitions of continuous and discrete time signals like unit step, unit impulse, ramp functions.
- Classifications of signals as periodic, aperiodic, even, odd, energy and power.
- Properties of Fourier series and transforms including Dirichlet conditions, time shifting property, Parseval's theorem.
- Definitions of causal, non-causal, static and dynamic systems.
- Calculations of Fourier and Laplace transforms of basic signals like impulse, step functions.
So in summary, this document provides a review of fundamental concepts in signals and systems along with practice
AN INTEGRATED FOUR-PORT DC-DC CONVERTER-CEI0080Vivek Venugopal
This document proposes a novel four-port DC/DC converter topology for renewable energy applications. The proposed topology adds two switches and two diodes to a traditional half-bridge topology to interface two power sources, one bidirectional storage port, and one isolated load port. Zero-voltage switching is achieved for all four main switches. Three ports can be tightly regulated through independent duty cycles while the fourth is unregulated to maintain power balance. Experimental results confirm independent control over three processing paths with low component count and losses.
The document provides information on the PIC16F877 microcontroller. It discusses the microcontroller's features such as 8KB of flash memory, 368 bytes of RAM, timers, interrupts, I/O ports, and 10-bit A/D conversion. It describes the microcontroller's architecture including the CPU, memory organization into flash, RAM and EEPROM, serial communication protocols, and instruction set. The document also covers addressing modes, special function registers, and timer and port functionality.
Describes Signal Processing in Radar Systems,
For comments please contact me at solo.hermelin@gmail.com.
For more presentations on different subjects visit my website at http://solohermelin.com.
I recommend to see the presentation on my website under RADAR Folder, Signal Processing Subfolder.
This document discusses the history and types of radio receivers. It describes how the earliest radio receiver was created in 1896 by Alexander Popov and was based on Maxwell's discovery of electromagnetic waves. There are three main types of receivers discussed - crystal radios, tuned radio frequency receivers, and superheterodyne receivers. Crystal radios require no power source beyond the radio waves themselves, while tuned radio frequency receivers have individually tuned amplifier stages and superheterodyne receivers mix signals to extract an intermediate frequency. The document also covers frequency ranges, sensitivity, selectivity and how radio waves propagate.
The operational amplifier (op-amp) is an integrated circuit that can provide voltage gain and be used as a signal amplifier or comparator. It has high input resistance, virtually infinite voltage gain, and two inputs - inverting and non-inverting - and one output. Common op-amp configurations include the inverting amplifier, non-inverting amplifier, summing amplifier, and comparator. The op-amp is a versatile active component used in various circuit applications.
Digital frequency meters can measure frequencies from 10 Hz to 12.5 MHz with sensitivities as low as 100 mV rms. They contain input amplifiers, pulse-forming circuits, and cascaded ring counting units to count input pulses and display the frequency digitally. Errors may occur due to quantization effects, time base inaccuracies, and trigger noise. Applications include frequency counting, precision radar measurements, and transducer-based physical measurements like speed, pressure, temperature and more.
The document discusses several types of specialized oscilloscopes:
1. Delayed time base oscilloscopes allow studying all parts of a pulse waveform by delaying the signal to the vertical plates. This ensures no part of the waveform is lost.
2. Analog storage oscilloscopes can retain an image for longer periods through mesh or phosphor storage techniques, allowing viewing of very low frequency waveforms.
3. Sampling oscilloscopes use a staircase-ramp generator to take samples that are displayed as the beam moves across the screen. Synchronization ensures sampling is timed with the input signal frequency.
4. Digital storage oscilloscopes digitize the input signal using an analog-to-
This document discusses an RFID-based e-passport system. It describes how e-passports contain an integrated RFID chip that stores the same data visible on the passport, including a unique identification number. This allows border agents to verify passport information quickly by scanning the chip without physically examining the document. The objectives are to analyze advantages of e-passports, recommend improvements to existing passports, and design an RFID passport system prototype.
Bipolar junction transistor : Biasing and AC AnalysisTahmina Zebin
1. The document discusses various transistor amplifier circuit designs and analysis techniques, including biasing circuits like base bias, voltage divider bias, and emitter feedback bias.
2. It introduces the small-signal h-parameter transistor model that represents the transistor under AC conditions and defines terms like small-signal current gain and output conductance.
3. The document provides examples of calculating Q-points, load lines, and biasing component values for different transistor amplifier circuits.
The document discusses programming the 8051 microcontroller. It can be programmed using low-level assembly language or high-level languages like C. Assembly language code is faster but more difficult to write and less portable, while C code is easier but slower. The document provides examples of adding two numbers in both C and assembly. It also discusses the 8051 instruction set, addressing modes, subroutines, and arithmetic operations.
1. The document discusses digital signal processing and z-transforms. It provides examples of calculating z-transforms for different sequences, including exponential sequences, sums of sequences, and finite length sequences.
2. It also covers properties of the region of convergence for z-transforms, and methods for calculating the inverse z-transform, including inspection of z-transform pairs and using partial fraction expansions.
3. The examples help illustrate how to use z-transforms to analyze discrete-time signals and systems.
This document discusses digital filter design methods. It introduces IIR and FIR filters and their design techniques. The key methods covered are:
1. IIR filter design using impulse invariance, which samples the impulse response of an analog filter to obtain the discrete-time filter.
2. IIR filter design using bilinear transformation, which maps the continuous s-domain to the discrete z-domain to avoid aliasing.
3. FIR filter design using frequency sampling, which designs a linear phase FIR filter by sampling the desired frequency response and taking the inverse DFT.
Nyquist criterion for distortion less baseband binary channelPriyangaKR1
binary transmission system
From design point of view – frequency response of the channel and transmitted pulse shape are specified; the frequency response of the transmit and receive filters has to be determined so as to reconstruct [bk]
This document provides an overview of signals and systems. It defines key terms like signal, system, continuous and discrete time signals, analog and digital signals, periodic and aperiodic signals. It also discusses different types of signals like deterministic and probabilistic signals, energy and power signals. The document then classifies systems as linear/nonlinear, time-invariant/variant, causal/non-causal, and with/without memory. It provides examples of different signals and properties of signals like magnitude scaling, time shifting, reflection and scaling. Overall, the document introduces fundamental concepts in signals and systems.
Analog Electronics interview and viva questions.pdfEngineering Funda
1. The document contains 50 questions and answers related to analog electronics viva questions covering topics like operational amplifiers, integrated circuits, sample and hold circuits, and more.
2. It provides definitions and explanations of key terms like input offset voltage, common mode rejection ratio, slew rate, and open and closed loop configurations of op-amps.
3. The questions are asked by Engineering Funda YouTube channel professor Hitesh Dholakiya and cover concepts tested in analog electronics viva exams.
The document summarizes the key functions of the telemetry, tracking and command (TT&C) subsystem of a satellite. It discusses how TT&C provides vital communication between the satellite and ground stations by (1) monitoring the satellite's status and measurements through telemetry, (2) sending commands from the ground to control satellite functions, and (3) tracking the satellite's location through antenna positioning and Doppler effect measurements. The TT&C subsystem receives commands from and provides data to the satellite's command and data handling system and performs autonomous operations like antenna pointing and fault recovery.
This document discusses vestigial sideband (VSB) modulation. VSB modulation is a compromise between single sideband (SSB) and double sideband suppressed carrier (DSB-SC) modulation that overcomes some of the drawbacks of SSB. In VSB, one sideband and a vestige of the other sideband are transmitted together, requiring less bandwidth than DSB but more than SSB. VSB modulation is commonly used for television signal transmission to reduce the bandwidth requirement compared to DSB.
Double Side band Suppressed carrier (DSB-SC) Modulation and Demodulation.SAiFul IslAm
This document describes an experiment on double sideband suppressed carrier (DSB-SC) modulation and demodulation performed by electrical engineering students at the University of Asia Pacific. The objectives were to observe DSB-SC modulation using an MC1496 modulator and examine synchronous demodulation of DSB-SC signals. The experiment involved generating a message signal, carrier signal, and DSB-SC modulated signal. A balanced modulator was used to produce the DSB-SC signal. Synchronous demodulation using a balanced multiplier, low-pass filter, and same carrier signal as the modulator recovered the original message signal from the DSB-SC signal. The students observed input and output waveforms and discussed the circuit connections and results
Signals can be classified as continuous-time or discrete-time. Continuous-time signals have a value for all points in time, while discrete-time signals have values only at specific sample points. Common elementary signals include unit step, unit impulse, sinusoidal, and exponential functions. Signals can be further classified based on properties like periodicity, even/odd symmetry, and energy/power. Operations like time shifting, scaling, and inversion can be performed on signals. Discrete-time signals are often obtained by sampling continuous-time signals.
This document contains a question bank with two mark questions and answers related to signals and systems. Some key topics covered include:
- Definitions of continuous and discrete time signals like unit step, unit impulse, ramp functions.
- Classifications of signals as periodic, aperiodic, even, odd, energy and power.
- Properties of Fourier series and transforms including Dirichlet conditions, time shifting property, Parseval's theorem.
- Definitions of causal, non-causal, static and dynamic systems.
- Calculations of Fourier and Laplace transforms of basic signals like impulse, step functions.
So in summary, this document provides a review of fundamental concepts in signals and systems along with practice
AN INTEGRATED FOUR-PORT DC-DC CONVERTER-CEI0080Vivek Venugopal
This document proposes a novel four-port DC/DC converter topology for renewable energy applications. The proposed topology adds two switches and two diodes to a traditional half-bridge topology to interface two power sources, one bidirectional storage port, and one isolated load port. Zero-voltage switching is achieved for all four main switches. Three ports can be tightly regulated through independent duty cycles while the fourth is unregulated to maintain power balance. Experimental results confirm independent control over three processing paths with low component count and losses.
The document provides information on the PIC16F877 microcontroller. It discusses the microcontroller's features such as 8KB of flash memory, 368 bytes of RAM, timers, interrupts, I/O ports, and 10-bit A/D conversion. It describes the microcontroller's architecture including the CPU, memory organization into flash, RAM and EEPROM, serial communication protocols, and instruction set. The document also covers addressing modes, special function registers, and timer and port functionality.
Chp4 introduction to the pic microcontroller copymkazree
The document provides an introduction to the PIC microcontroller, including:
1) It describes the basic components and architecture of microcontrollers compared to microprocessors.
2) It outlines the history and features of the popular PIC microcontroller family from Microchip Technology, including the PIC16F84 model.
3) It explains the core components of the PIC16F84 including ports, memory organization, clock generator, and the central processing unit.
The document discusses the PIC microcontroller architecture. It begins by explaining what PIC stands for and how PIC microcontrollers have become important in industrial automation and embedded applications. It then provides a brief history of PIC development. The document goes on to describe the different categories of PIC microcontrollers based on internal architecture, including baseline, mid-range, enhanced mid-range, and PIC18. It also discusses the core features of PIC microcontrollers like instruction set, register file architecture, and interrupt logic. Finally, it explains some key architectural features like Harvard architecture and reduced instruction set that enable fast execution speeds.
The document discusses the syllabus for the course EE6008 - Microcontroller Based System Design. It covers 5 units: (1) Introduction to PIC Microcontroller architecture; (2) Interrupts and timers on PIC microcontrollers; (3) Interfacing peripherals using I2C bus, analog to digital converters, and UART; (4) Introduction to ARM processor architecture; (5) ARM organization including pipeline stages and instruction set. The objectives are to introduce microcontroller architectures and teach how to use interrupts, timers, and peripheral devices for data communication.
This document provides an overview of the peripheral interface controller (PIC) microcontroller. It discusses the PIC's Harvard architecture, instruction set, memory organization, I/O ports, timers, and other features. Specifically, it describes the PIC16F877 microcontroller, covering its program memory, data memory banks, registers, instruction set categories, timer modules including Timer 0 and its prescaler, and I/O ports including PORTA and its configuration.
The document provides an introduction to the PIC microcontroller including its origins, architecture, and key features. It discusses the PIC16F877A microcontroller in detail including its register file map, pin configuration, status register, and difference compared to the 8051 microcontroller. Examples of writing assembly language code and C code for blinking an LED are also provided.
EE6008 MCBSD - Introduction to PIC Micro controller pavihari
This document outlines the syllabus for the course EE6008 Microcontroller Based System Design. It covers 5 units:
1. Introduction to PIC microcontrollers including architecture of PIC16C6x and PIC16C7x families.
2. Interrupts and timers in PIC microcontrollers including external interrupts, timer programming.
3. Peripherals and interfacing including I2C, serial EEPROM, ADC, UART, LCD interfacing.
4. Introduction to ARM processor architecture including programmer's model, development tools, memory hierarchy.
5. ARM organization including pipeline organization, instruction execution, instruction set, coprocessor interface.
This document outlines the syllabus for the course EE6008 Microcontroller Based System Design. It covers 5 units:
1. Introduction to PIC microcontrollers including architecture of PIC16C6x and PIC16C7x families.
2. Interrupts and timers in PIC microcontrollers including external interrupts, timer programming.
3. Peripherals and interfacing including I2C, serial EEPROM, ADC, UART, LCD interfacing.
4. Introduction to ARM processor architecture including programmer's model, development tools, memory hierarchy.
5. ARM organization including pipeline, instruction set, coprocessor interface, embedded applications.
The
This document provides details about the MSP430x5xx microcontroller including its block diagram, CPU architecture, memory map, I/O ports, interrupts, clock system, low power modes, watchdog timer and more. Key aspects include its 16-bit RISC CPU, various clock signals, flash memory up to 512KB, RAM up to 66KB, 8 I/O ports, analog to digital converter, timers, real-time clock, and low power modes down to 0.1uA. Example code is provided to configure ports for output and LED interfacing.
The document discusses different addressing modes of the 8051 microcontroller. It describes five addressing modes: immediate, register, direct, indirect, and index addressing modes. Immediate addressing uses a constant in the operand field. Register addressing accesses operands stored in registers. Direct addressing specifies the operand with an 8-bit address. Indirect addressing specifies a register containing the operand address. Index addressing accesses a look-up table using the accumulator and base register sum as the address.
The document discusses the PIC16F877A microcontroller. It describes the essential elements as having a 8K flash program memory, 368 bytes of data RAM, 256-byte EEPROM, 5 I/O ports, a 10-bit analog-to-digital converter, timers, and interrupts. The pinout and internal architecture are also summarized, including the CPU, memory types, clock, ports, timers, and analog-to-digital converter. The basic elements of the microcontroller are outlined as the clock, ALU, accumulator, RAM memory types, and permanent memories.
The document describes the features of an AVR 8-bit microcontroller, including its RISC architecture, memory capabilities, I/O ports, timers, USB and peripheral features. It has 8/16/32KB of flash memory, 512/512/1024 bytes of EEPROM and SRAM, and 22 programmable I/O lines. It includes analog and digital features such as timers, USART, SPI and a USB controller.
PIC Introduction and explained in detailedAnkita Tiwari
The document provides an introduction to the PIC microcontroller. It discusses what a microcontroller is, compares microcontrollers to general purpose microprocessors, and briefly outlines the history of the PIC microcontroller. It then describes features of the PIC16F84 microcontroller including its clock generator, reset function, ports, central processing unit, and memory organization including flash memory, RAM, and ROM. It also covers the timer and prescalar functions.
PIC 16F877- features, architecture, functional pin description, program memory, and data memory organization, STATUS register, OPTION REG register, Power Control Register (PCON), Data EEPROM, and FLASH Program Memory.
A microcontroller is a single-chip microprocessor system consisting of a CPU, memory, and input/output ports. It can be considered a complete computer on a single chip. The 8051 was an early microcontroller developed by Intel for use in embedded systems. It had 4KB of program memory, 128 bytes of data memory, timers, counters, and I/O ports. The 8051 has separate memory spaces for program and data memory and its CPU, registers, timers and I/O ports allow it to monitor and control external devices.
An embedded system is a specialized computer system that is part of a larger mechanical or electrical system. It performs predefined tasks, unlike a general purpose computer. The document discusses embedded systems and provides examples like refrigerators and mobile phones. It also describes microprocessors, microcontrollers, and the 8051 microcontroller architecture in detail. Applications of embedded systems mentioned include signal processing, distributed control, and small systems.
The document provides an overview of the key features and architecture of NXP Semiconductors' LPC213x microcontroller family. The LPC213x MCUs are based on an ARM7TDMI-S CPU with on-chip flash memory and RAM. They include features such as GPIO ports, UARTs, I2C interfaces, SPI, PWM, ADC, DAC, RTC, and watchdog timer. The MCUs also support in-system programming, debugging via EmbeddedICE, and instruction tracing with an embedded trace macrocell.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...University of Maribor
Slides from talk presenting:
Aleš Zamuda: Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapter and Networking.
Presentation at IcETRAN 2024 session:
"Inter-Society Networking Panel GRSS/MTT-S/CIS
Panel Session: Promoting Connection and Cooperation"
IEEE Slovenia GRSS
IEEE Serbia and Montenegro MTT-S
IEEE Slovenia CIS
11TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTING ENGINEERING
3-6 June 2024, Niš, Serbia
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
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ARCHITECTURAL FEATURES OF 16F873 PIC MICRO CONTROLLER
2.1 ARCHITECTURE OF PIC 16F873 MICROCONTROLLER
The internal logic design of a device is called its architecture. The Microcontroller architecture determines
how and what various operations are performed. The architecture of the PIC 16F873 Microcontroller is shown
in Figure 2.1.
Figure 2.1 Block Diagram of PIC 16F873 Microcontroller
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The architectural features of PIC 16F873 Microcontroller are given below
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program branches, which are two cycle
• Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory
(RAM), Up to 256 x 8 bytes of EEPROM data memory
• Pinout compatible to the PIC 16C73B/74B/76/77
• Interrupt capability (up'to 14 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM technology
• Fully static design
• In-Circuit Serial Programming a (ICSP) via two pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 mA typical @ 3V, 32 kHz -< 1 mA typical standby current
❖ Peripheral Features
• TimerO: 8-bit timer/counter with 8-bit prescaler
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• Timer 1: 16-bit timer/counter with prescaler can be incremented during sleep Via
external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler
and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. Resolution is 12.5 ns
- Compare is 16-bit, max. Resolution is 200 ns
- PWM max. Resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPIa (Master Mode) and I2Ca (Master/Slave)
• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection
Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls
❖ PIC 16F873 Microcontroller Pin Configuration
The PIC 16F873 Microcontroller is a 28 pin DIP. The Pin diagram
contains the abbreviated names of the signals for each pin. It is important to note that many of the pins are
used for more than one function. Programming functions or physical pin connections determine the use of any
multifunction pins. The system designer decides which of these functions is to be used and designs the
hardware and software affecting that pin accordingly.
Figure 2.2 Pin Diagram of PIC 16F873 Microcontroller
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2.3 MEMORY ORGANIZATION
There are three memory blocks in PIC 16F873 Microcontroller [13]. The Program Memory and Data Memory
have separate buses so that concurrent access can occur.
2.3.1 Program Memory Organization
The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory
space. The PIC 16F873 device has 4K x 14 words of FLASH program memory. Accessing a location above
the physically implemented address will cause a wraparound. The reset vector is at OOOOh and the interrupt
vector is at 0004h.
The PIC 16F873 Program memory Map and stack is shown in Figure 2.3.
Figure 2.3 PIC16F873 Program Memory Map And Stack
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2.3.2 Data Memory Organization
The data memory is partitioned into multiple banks, which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>) and RPO (STATUS<5>) are the bank select bits. These
bits are represented in the Table 2.2.
Table 2.2 Bank Select Bits
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
Static RAM. All implemented banks contain Special Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another.
2.3.3 Special Function Registers
Special Function Registers [14] are special elements of RAM, their purpose predefined by the manufacturer.
Each of these registers is named and controls a certain subsystem of MCU. For example: by writing zeros and
ones to the SFR register which controls an I/O port, each of these pins can be designated as input or output
(each register bit corresponds to one of the port pins).
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the
desired operation of the device. These registers are implemented as static RAM. The Special Function
Registers can be classified into two sets; core (CPU) and peripheral.
Status Register
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for
data memory. The STATUS register can be the destination for any instruction, as with any other register. If
the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to
these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO
and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination
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may be different than intended. It is recommended, that only BCF, BSF, SWAPF and MOVWF instructions
are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the
STATUS register.
❖ OptionReg Register
The OPTION_REG Register is a readable and writable register, which contains various control bits to
configure the TMRO presealer/WDT postscaler (single assignable register known also as the prescaler), the
External INT Interrupt, TMRO and the weak pull-ups on PORTB.
❖ PIE1 Register
The PIE1 register contains the individual enable bits for the peripheral interrupts.
❖ PIR1 Register
The PIR1 register contains the individual flag bits for the peripheral interrupts.
❖ PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
❖ PIR2 Register
The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
❖ PCON Register
The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watch-dog Reset (WDT) and an external MCLR Reset.
2.4 I/O PORTS
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
There are three ports in PIC 16F873 Microcontroller. They are Port A, Port B and Port C.
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□ PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in
a hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output.
□ PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in
a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output.
□ PORTC and the TRISC Register
r
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in
a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output.
PORTC pins have Schmitt Trigger input buffers.
2.5 TIMERS
Majority of programs utilizes these miniature electronic "stopwatches". Commonly, timers are 8 or 16-bit
registers whose value automatically increases upon an impulse. If timer is stimulated by an internal MCU
oscillator, it can be used for measuring time between two occurrences (register value at the start of measuring
= Tl, register value at the end of measuring = T2, elapsed time = T2-Tl). If timer is triggered by impulses
from an external source, instrument behaves like a counter. In both cases, filling the register resets the counter
and the occurrence is recorded in a particular bit of SFR register (Overflow flag). This makes possible to
measure longer time periods. Also, if enabled, this flag can cause an interrupt for breaking the program and
carrying out a designated routine.
2.5.1 Timer 0 Module
The Timer0 module timer/counter has the following features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
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• Internal or external clock select
• Interrupt on overflow from FFh to OOh
• Edge select for external clock
Timer mode is selected by clearing bit TOCS (OPTION REG<5>). In timer mode, the TimerO module will
increment every instruction cycle (without prescaler). If the TMRO register is written, the increment is
inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value
to the TMRO register. Counter mode is selected by setting bit TOCS (OPTION REG<5>). In counter mode,
TimerO will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is
determined by the TimerO Source Edge Select bit TOSE (OPTION_REG<4>). Clearing bit TOSE selects the
rising edge. The prescaler is mutually exclusively shared between the TimerO module and the watchdog
timer. The prescaler is not readable or writable
2.5.2 Timer1 Module
The Timerl module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which
are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from OOOOh to FFFFh
and rolls over to OOOOh. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in
interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1
interrupt enable bit TMR1IE (PIE1<0>). Timerl can operate in one of two modes:
• As a timer
* As a counter
The operating mode is determined by the clock select bit, TMR1CS (T1C0N<1>). In timer mode, Timer 1
increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock
input. Timer 1 can be enabled/disabled by setting/clearing control bit TMRION (T1CON<0>). Timer 1 also
has an internal “reset input”. This reset can be generated by either of the two CCP modules counter mode is
selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin
RC1/T10SI/CCP2, when bit T10SCEN is set, or on pin RCO/TIOSO/TICKI, when bit T10SCEN is cleared.
Timerl may operate in asynchronous or synchronous mode depending on the setting of the TMR1CS bit.
2.6 ADDRESSABLE UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART [15] can be
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configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be configured as a half duplex synchronous system that can
communicate with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also
has a multi- processor communication capability using 9-bit address detection.
USART Asynchronous Mode
In this mode, the USART uses standard non-retum-tozero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives
the LSB first. The USART’s transmitter and receiver are functionally independent, but use the same data
format and baud rate. The baud rate generator produces a clock either xl6 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous
mode is selected by clearing bit SYNC (TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 2.4. The heart of the transmitter is to transmit
(serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG.
The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has
been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be
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enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine
if the TSR register is empty. Transmission is enabled by setting enable bit TXEN (TXSTA<5>).
Figure 2-4 USART Transmit Block Diagram
Steps to follow when setting up an Asynchronous Transmission:
• Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.
• If interrupts are desired, then get enable bit TXIE.
• If 9-bit transmission is desired, then set transmit bit TX9.
• Enable the transmission by setting bit TXEN, which will also set bit TXIF.
• If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.
• Load data to the TXREG register (starts transmission).
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 2.5.The data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually a high speed shifter operating at xl6 times the baud
rate, whereas the main receive serial shifter operates at the bit rate or at FOSC.Once asynchronous mode is
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selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is to receive
(serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the
RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual
interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIEl<5>).Flag bit RCIF is a read only
bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e. it is a two deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the
detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR
(RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve
the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the
receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the
RCREG register are inhibited, so it is essential to clear error bit OERR if it is set. Framing error bit FERR
(RCSTA<2>) is set if a stop bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same
way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore it is
essential for the user to read the RCSTA register before reading RCREG register in order not to lose the old
FERR and RX9D information.
Figure 2-5 USART Receiver Block Diagram
Steps to follow when setting up an Asynchronous Reception:
• Initialize the SPBRG register for the appropriate baud rate. If a high- speed baud rate is desired, set bit
BRGH.
• Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.
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• If interrupts are desired, then set enable bit RCIE.
• If 9-bit reception is desired, then set bit RX9.
• Enable the reception by setting bit CREN.
• Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit
RCIE is set.
• Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during
reception.
• Read the 8-bit received data by reading the RCREG register.
• If any error occurred, clear the error by clearing enable bit CREN.
2.7 ANALOG TO DIGITAL CONVERTER
The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices.
The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the
converter. The converter then generates a digital result of this analog level via successive approximation. The A/D
conversion of the analog input signal results in a corresponding 10-bit digital number. The A/D module has
high and low voltage reference input that is software selectable to some combination of VDD, VSS, RA2 or
RA3.The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To
operate in sleep, the A/D clock must be derived from the A/D’s internal RC oscillator.
The A/D module has four registers. These registers are;
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control RegisterO (ADCONO)
• A/D Control Registerl (ADCON1)
The ADCONO register controls the operation of the A/D module. The ADCON1 register configures the
functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be the voltage
reference) or as digital I/O.The ADRESH: ADRESL registers contain the 10-bit result of the A/D conversion.
When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit
(ADCONO<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module
is shown in Figure 2.6.After the A/D module has been configured as desired, the selected channel must be
acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits
selected as inputs.
The following steps should be followed for doing an A/D conversion:
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> Configure the A/D module:
• Configure analog pins / voltage reference /and digital I/O (ADCON1)
• Select A/D input channel (ADCONO)
• Select A/D conversion clock (ADCONO)
• Turn on A/D module (ADCONO)
> Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
> Wait the required acquisition time.
> Start conversion:
• Set GO/DONE bit (ADCONO)
> Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
> Read A/D Result register pair (ADRESH: ADRESL), clear bit ADIF if required.
> For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is required before next acquisition starts.
>
Figure 2-6 A/D Block Diagram
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2.8. WATCH DOG TIMER
The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external
components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been
stopped. The block diagram is shown in Figure 2.7.
During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device
is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation
(Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer
time-out. The WDT can be permanently disabled by clearing configuration bit WDTE. Values for the WDT
prescaler may be assigned using the OPTION REG register.
Figure 2.7 WATCHDOG TIMER BLOCK DIAGRAM