The document discusses the discrete wavelet transform (DWT) and different approaches for implementing it, including separable and non-separable lifting. It compares the performance of separable and non-separable lifting implementations on CPU, GPU, and pixel shaders. Non-separable lifting outperforms other approaches by fully utilizing parallelism within hardware. The document also outlines future work exploring different CPU architectures.

2. Discrete Wavelet Transform (DWT)
L
H
=
G1
(o)
G1
(e)
G0
(o)
G0
(e)
L
H
L
H
=
k
1 U(k)
0 1
1 0
P(k) 1
L
H

3. 2-D DWT
x = LL HL LH HH
T
y = LL HL LH HH
T

4. Existing Approach: Separable Convolution
y = NV
NH
x

5. Existing Approach: Separable Lifting
TH
P
SH
U
TV
P SV
U
y = SV
U SH
U TV
P TH
P x

6. Our Approach: Non-Separable Lifting
TH
P0
TV
P0
SH
U0
SV
U0
TP1
SU1
y = SV
U0
SH
U0
SU1
TV
P0
TH
P0
TP1
x

7. Architectures
pixel shader OpenCL/CUDA CPU
input/output off chip off chip off chip
intermediate results off chip on chip on chip
— in registers no yes no
on chip memory no 32–96 KiB 3–35 MiB
concurrent threads thousands thousands 2–112
4-tuples / thread 1 1–4 thousands
view global block-based block-based
block size global 642 5122

8. Results
CDF 9/7 Wavelet
0
10
20
30
40
50
60
70
80
90
100kpel 1Mpel 10Mpel 100Mpel
GB/s
OpenCL (AMD 6970)
0
5
10
15
20
25
30
35
100kpel 1Mpel 10Mpel 100Mpel
GB/s
Pixel Shader (NVIDIA Titan X)
separable lifting
separable polyconvolution
separable convolution
non-separable lifting
non-separable polyconvolution
non-separable convolution

9. Future Work
CPU
blade055 2 sockets × 28 cores = 56 CPUs
Intel(R) Xeon(R) CPU E5-2680 v4 @ 2.40GHz
cache: 32k/256k/35M
vidte 2 sockets × 12 cores = 24 CPUs
Intel(R) Xeon(R) CPU X5680 @ 3.33GHz
cache: 32k/256k/12M
UV2000 14 sockets × 8 cores = 112 cores
Intel(R) Xeon(R) CPU E5-4627 v2 @ 3.30GHz
cache: 32k/256k/16M