This document discusses optimizing discrete wavelet transforms for CPU performance. It covers techniques like loop fusion, removing prologs and epilogs, leveraging CPU cache, SIMD vectorization, and parallelization. Benchmark results show these optimizations can achieve up to an 11x speedup over the separable diagonal implementation for a 10 megapixel image on an Intel Core2 Quad CPU. Future work areas discussed include merging multiple levels and transforms.

1. Wavelets @ CPU
David Barina
April 15, 2014
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2. Wavelet
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3. Discrete Wavelet Transform
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4. Lifting
α
β
γ
δ
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5. 2-D DWT
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6. 2-D Separability
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7. What have I done?
loop fusion
removed prologs/epilogs
influence of CPU cache
SIMD-vectorization
parallelization
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8. Loop Fusion
read
write
F
F
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9. Removed Prologs and Epilogs
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10. Influence of CPU Cache
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11. SIMD Vectorization
4 × 4 6 × 2
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12. Image Processing and Buffers
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13. Parallelization
prolog
overlay
overlay
segment
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14. Results
Intel Core2 Quad @ 2.00 GHz
10 Mpx
CDF 9/7, 1 level, in-place
approach best algorithm time/px speed-up
separable diag. 17.23 ns 1.0×
single-loop diag. 2 × 2 9.55 ns 1.8×
core diag. 2 × 2 8.79 ns 2.0×
super-core vert. 4 × 4 5.33 ns 3.2×
parallel (4) vert. 4 × 4 1.55 ns 11.1×
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15. Future Work
merge several levels
merge forward and inverse cores
another wavelets
combine with EAW
another platforms (ARM, GPU, FPGA)
another transforms
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16. Example (AMD Opteron)
1.0ns
10.0ns
100.0ns
1.0k 10.0k 100.0k 1.0M 10.0M 100.0M
time/pixel
pixels
naive vertical
naive diagonal
single-loop vertical
single-loop diagonal
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