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QUANTUM LOGIC
SYNTHESIS
Srikanth Bitra
(10881A0451)
Under guiedence of C.Padmini
ECE dept.
Contents






Introduction
Differences between traditional and quantum circuits
Reversible computation
Reversible gates








NOT
C-NOT
Toffoli
RSWAP
Fredkin

Synthesis frame works




RMRLS
DDS
RMDDS
Features of quantum computer:





Super position
Interference
Entanglement
Measurement
Quantum vs Classical
Quantum Computation
 Bijective or Reversible
 Input and output vectors have same bit-width
 No information loss
Classical Computation
 Irreversible
 Different input and output bit-width
 Loss of information
Need for reversibility


Fundamental physics dictates that energy
must be dissipated when information is
erased, in the amount KT ln2 per bit erased,
where K is Boltzmann constant(k=1.38x1023JK-1) and T is absolute temperature in K
NOT
C-NOT (Feymann gate)
CCNOT (Toffoli) gate
Fredkin(CSWAP)

Logic:p=a, q=if(a=1) then c else b, r=if(a=1) then b else c
Synthesis methods of quantum
circuits





QBC synthesis
Reed muller reversible logic synthesis
Decision diagram synthesis
RMRLS + DDS  RMDDS
Reed Muller Reversible Logic
Synthesis(RMRLS)
Any Boolean function can be described by an
exclusive-OR sum-of-products (ESOP) expression
ex: for a boolean expression y= a+b’c
SOP=a+b’c
ESOP=a a’b’c
Two types of expressions:
PPRM :All variables are un-complemented
PPRM=abc ac bc
a c
FPRM:Either x or x’ appear throughout
FPRM=a’b’c a’
1

Reed Muller Reversible Logic
Synthesis (cont..)



Synthesis flow
Find factors for any outptut a0 without literal a (target)






Build a node in a search tree, where:





#PPRM terms is reduced by Toffoli gate
Create a child node

Insert the node into Priority Queue (PQ)





EX: a0 = a bc 1 ac
Valid factors :bc,1
Target : a

Sort Priority queue
Priority α # PPRM terms eliminated

Pop the queue ,repeat above steps
Decision Diagram Synthesis









Boolean functions are represented by a DD
(Decision Diagrams)
DD:acyclic graph G=(V, E) where
decompositions are applied to each node v ϵ V
Shannon decomposition(S) : f=xi’.fxi=0
xi.fxi=1
Positive Davio decomposition(pD): f=xi’.fxi=0
xi.fxi=2
Negative Davio decomposition(nD): f=xi’.fxi=1
xi.fxi=2
 fxi=0 and fxi=1


f

=f

are co-factors w.r.t. xi’ and xi
f
Decision Diagram Synthesis
(DDS)





Synthesis flow
Build DD(Decision Diagrams)
Depth first search
Map each gate to Toffoli gate
Note:
DDS method automatically transforms an
irreversible specification into reversible
f1

f2

a

0

1

f3

Low(f1)

a

0

1
high(f2)

b

0

1

Low(f3)

high(f2)
0
a
Low(f1)
b
high(f3)
Low(f3)

high(f3)

f1

f2
high(f2)

a

0

1

a

0

1

f3

Low(f1)

high(f2)

b

0
Low(f3)

1

0
a
Low(f1)
b
high(f3)
Low(f3)

high(f3)

f2

f1

a

0

1

Low(f1)

f3

0

a

high(f2)

a

0
Low(f3)

1

1
high(f3)

high(f2)
0
a
Low(f1)
b
high(f3)
Low(f3)

g
f1
g
g
g
g
f2
RMRLS vs DDS
RMRLS

DDS

Pros

Fewer qubits(lines)
Low quantum cost

Low synthesis time
Able to synthesize large
circuits
Can synthesize
irreversible specifications

Cons

High synthesis time
Only able to synthesize small circuits

Large no. of garbage
outputs
Reed-Muller Decision Diagram
Synthesis (RMDSS)






Hybrid of RMRLS and DDS
A flexible and efficient reversible circuit
synthesizer
Qubits can be traded off for QC
User defined time limit
User
constriants
Applications of quantum gates






Efficient white light LED’s
Processor’s designed for complex scientific
calculations
Artificial intelligence
cryptography
Acknowledge


Susmita Sur-Kolay (Indian Statistical Institute)
References






D. P. Di Vincenzo, “Quantum Computation,”
Science, 270, 1995, pp. 255-256.
K. Iwama, Y. Kambayashi, S. Yamashita,
“Transformation Rules for Designing CNOTBased Quantum Circuits,” Design Automation
Conference,2002, pp.419-424.
P. A. M. Dirac, The Principles of Quantum
Mechanics, Oxford University Press, 1st
Edition, 1930.
Quantum logic synthesis (srikanth)
Quantum logic synthesis (srikanth)

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Quantum logic synthesis (srikanth)