The document discusses signal integrity simulation for high-speed SFP+ serial links. It begins with an overview of the challenges of high-speed transmission and the need for simulation. It then covers: 1) The IBIS-AMI model structure and configuration options for simulating transmitters and receivers. 2) The simulation setup created in ADS to optimize equalization settings for a specific SFP+ interface design. 3) The results of simulations at 10.3125Gbps and 16Gbps, showing larger eye openings at the lower data rate. 4) Additional transmitter simulation results, indicating better eye openings when optimizing de-emphasis levels and voltage amplitudes.

1. 
Abstract—Designing a high-speed serial link transmission
line for SFP+ interface is challenging due to the high data rates
up to 16 Gbps. The data recovery from a received serial data
stream is negatively impact by channel loss, reflection, crosstalk,
etc. To ensure the quality of the layout design, signal integrity
(SI) simulation is required to give the designer some confidence
before the data sent out for printed board fabrication. In this
paper, the work for signal integrity simulation for the high-
speed SFP+ interface serial link is present. The simulation setup
for the serial link differential signals required TX and RX IBIS-
AMI model and the passive channel model S-parameter data
will be discussed. The RX and TX test bench will be created to
optimize the equalization and pre-emphasis setting using
Advanced Design System (ADS) simulation tool from Keysight.
The result of the received data will be discussed. The optimized
eye diagram generated in this study shows the quality of the
SFP+ interface serial link design.
Keywords — ADS, Advanced Design System; AMI,
algorithmic modeling interface; Gbps, gigabit per second; IBIS,
input/output buffer information specification; RX, Receiver;
SERDES, SFP+, enhanced small form-factor pluggable; SI,
signal integrity; TX, Transmitter.
I. INTRODUCTION
Small form-factor pluggable (SFP) is a compact, hot-
pluggable network interface optical module used to converts
the serial electrical signals to serial optical signal and vice
versa for telecommunication and data communication
application. SFP+ is an enhanced version of the SFP that
supports data rates up to 16 Gbps. The SFP+ module form
factor is 30% smaller than the SFP optical module. It uses
less power, requires fewer components, support module
stacking, and is less expensive than XFP module.
Each SFP+ module houses an optical transmitter and
receiver. One end of the module is SERDES framer interface
(SFI) serial interconnect, which handles differential signals
up to 10 Gbps. The other hand is an optical connection that
complies the 10GbE and 8GFC standards. The data recovery
from a received serial data stream negatively impacted by
channel loss, reflection, crosstalk, etc. Complicated channel
condition at more than 10 Gbps raise the important of serial-
link signal integrity simulation as critical requirement in
printed board design.
A classic time-domain transient simulation has reached at
stage where simulation time take intolerably long even with
fastest workstations. IBIS-AMI is a modelling standard for
transceiver to enable fast and accurate simulation of the
multi-gigabit serial-links. It starts with analyzing the analog
network and generating the impulse response characteristics
of the transmitter and receiver analog buffers, the packages
and the channel between RX and TX.
Fig. 1 shows the basic structure of the data transmission
between transceiver and receiver of a system.
Fig. 1: Basic structure of data transmission.
From Fig. 1, the TX model is linear time invariant (LTI)
and can be use in both time-domain and statistical simulation
modes. The TX model contains the signal driver with swing
and pre-emphasis controls. The input to the transmitter
model is equivalent to the signal after the chip’s clock data
recovery (CDR). The RX model only supported in time-
domain simulation modes. The RX model applied
equalization (EQ) to and slices the signal received from the
channel. The output at the RX represents the input to the
chip’s clock data recovery (CDR). At the output, user will
use BER or eye diagram to analyses the quality of the signal
of the transmission lines.
The paper is organized as follows. In section II, this paper
will discuss the IBIS-AMI model structure and configuration
related to the selected component IC that is use in this study.
In section III, will look into the methodology of the study on
how the experiment is conducted using ADS simulation tools.
In section IV, will discuss the simulation result and analysis
of the eye diagram and which setup will get a better result.
Finally, will concludes the findings and discuss what is next.
II. RESEARCH SUMMARY
The most important things in signal integrity simulation
is how good the model and topology are representing the
simulation items and knowing what to aspect from the
experiments. First thing first is to understand the capabilities
and limitation of the IBIS-AMI model.
IBIS-AMI model is supporting both time-domain
superposition (bit-by-bit mode) and statistical mode. This
improving simulation run time while preserving the accuracy
of transient convolution simulation and characterizing the
complex digital signal processing functions found in multi-
Overview of Signal Integrity Simulation for
SFP+ Interface Serial Links with Advanced
Design System (ADS)
Mohd Farizul B. Azman (CID) Nor Azila Bt. Hamid (CID) Azmi B. Yahya
Wireless & System Technology Wireless & System Technology Wireless & System Technology
Mimos Berhad Mimos Berhad Mimos Berhad
Kuala Lumpur, Malaysia Kuala Lumpur, Malaysia Kuala Lumpur, Malaysia
farizul.azman@mimos.my azila.hamid@mimos.my azmiya@mimos.my
978-1-7281-5033-8/20/$31.00 ©2020 IEEE 68
Authorized licensed use limited to: University of Edinburgh. Downloaded on June 15,2020 at 07:09:26 UTC from IEEE Xplore. Restrictions apply.

2. gigabit transceiver such as equalization and clock data
recovery (CDR).
Fig. 2: End-to-End Channel in Multi-Gigabit System
Fig. 2 shows end-to-end channel in multi-gigabit system.
The passive channel group is composed of various elements
such as transmission lines, vias, and connector are modeled
in s-parameter. The analog channel group is the analog buffer
that act as front end to interface to the channel directly and
modeled in IBIS. The TX EQ and RX EQ/CDR blocks are
equalization circuits. They are modeled in AMI. The AMI
model actually works with IBIS to complete the both TX and
RX path from latch to latch, instead from pad to pad.
The main quantitative measure of signal integrity are eye
height and eye width of an eye plot diagram. From that bit-
error-rate (BER) or other plot such as bath tub curve can be
derived. The eye plot diagram is formed by folding many bits
in time domain with waveform representing the response of
these bit sequences.
IBIS-AMI model is an interface realized in three
functions compiled into executable file .dll for windows or .so
for linux operating system. The functions are AMI_Init(),
AMI_Close() and AMI_GetWave(). AMI_Init() function
must be implemented. Since waveform lengthy bit sequence
will be broken into small chunks and analysis accordingly,
there are some data structure maybe use many times. In such
scenario, the common “initialization” should be done in this
function. AMI_Close() function also must be implemented.
It clean up and release the memory allocated back to the
operating system. AMI_GetWave() function is optional to
implement. If the channel is Non-Linear Time Interval
(NLTI), direct synthesis to get BER is not possible. In that
case, the waveform of lengthy bit sequence is needed.
AMI_GetWave() function’s implementation provides such a
mechanism to compute and convert the input bit sequence
into their corresponding response.
There are two modes of AMI operation that is statistical
mode and time-domain (bit-by-bit) mode. If the
AMI_GetWave() function is not implemented, the model will
only be able to run statistical mode. Meaning the passive
channel must Linear Time Interval (LTI). If the GetWave
function is implemented, the model is also run in time-
domain mode that allow Non-Linear Time Interval (NLTI).
Fig. 3: Statistical Mode Operations
Fig. 3 shows the statistical mode operations. In this mode,
the channel is LTI that means that the waveform from
different bit sequences maybe constructed from single bit’s
impulse response using superposition. With the time-domain
impulse response of the passive channel, TX and RX models
can perform convolution on such single pulse. Once
simulator receive this from RX model, it can perform peak
distortion analysis like superposition to get the BER or eye
diagram directly.
Fig. 4: Time-domain Mode Operation
Fig. 4 shows the time-domain (bit-to-bit) mode operation.
In this mode, the channel is NLTI and no waveform
superposition should be done. Thus, a digital bit sequence
must be formed. This sequence may or may not be broken
into smaller chunks then convolved with passive channel
portion’s impulse response. The results are then called via
TX and RX AMI_GetWave() function to form actual time-
domain response of the full channel. Simulator will then fold
the waveform to compute the BER and others parameter.
IBIS-AMI operations above can be configure with IBIS
[Reserved Parameter], IBIS [Model Specific] for RX and
IBIS [Model Specific] for TX. IBIS [Reserved Parameter] is
a general configuration which containing some model files
such as:
1. Init_Returns_Impulse - Indicate that the model
AMI_Init() function can return a filtered respond.
2. GetWave_Exists - Indicate that the model supports
the AMI_GetWave() function.
IBIS [Model Specific] for RX configuration containing
some model files such as:
1. EQ_Level - A parameter to select EQ_Level based on
normal mode or DWDM mode and based on CTLEAdapt
selection mode.
2. DWDM_mode - A parameter selection to enable or
disable DWDM mode for EQ_Level.
3. Rx_config - A parameter to set the output of RX to
either post or pre-slice waveform.
4. DFEtab value - A parameter that defines DFE tab
gains.
5. DFEAdapt - A parameter to enable or disable the
DFEA adaption.
6. CTLEAdapt - A parameter to enable or disable the
CTLE adaption.
7. EOM_window - A parameter to control the number of
bits used for eye measurements.
IBIS [Model Specific] for TX configuration containing
some model files such as:
1. DE and DE_range - These two parameter combined
are used to set the output de-emphasis level.
2. VOD - To set output peak-to-peak differential
amplitude.
3. Tstonefile - Touchstone s-parameter file used by the
simulator to represent the TX analog front-end, including
termination. It depend on the VOD setting above.
69
Authorized licensed use limited to: University of Edinburgh. Downloaded on June 15,2020 at 07:09:26 UTC from IEEE Xplore. Restrictions apply.

3. 4. Gain - The parameter that able to set the gain value
for this function.
The TX and RX IBIS-AMI models configuration maybe
different from different vendors. Thus, their combination
also set the limits on how the models can be use. IBIS-AMI
model provider usually will prepare a user guide on how to
setup and configure the model for simulation.
For connector such as SFP+ module, sometimes the
vendor only provide the package’s s-parameter data with
some electrical information such as the operation frequency
range or edge rate without IBIS-AMI model information.
Without it, a generic TX and RX model for high-speed serial-
link can be used for the purpose of simulation to generate the
eye diagram for analysis.
III. METHODOLOGY
In this paper, we study a signal integrity post-simulation
works for multi-gigabit serial-link system consists of fiber
optic SFP+ module connector PN: 1888247-1 from TE
Connectivity and retime IC PN: DS125DF111 with DFE: 9.8
– 12.5 Gbps from Texas Instrument. IBIS-AMI model is
available for DS125DF111 device only. For SPF+ module, a
generic model will be use in the study. Both devices provide
package s-parameter data that representing the behavior of
the packages over frequency.
A layout design that represent the serial-link differential
lines connection between both devices provided in ODB++
format. The data will be import into SiPi function in ADS
simulation tool. Then, the printed circuit board stack-up and
vias information need to be add correctly. The stack-up
consists of the printed circuit board layering structure,
thickness and material information used in the design. Fig. 5
and 6 shows the serial-link connection for RX and TX on
ADS tool. With the setup, 3D Electromagnetic (EM) solver
simulation executed on both layout (25°C, DC to 20 GHz)
and the channel s-parameter for the transmission lines
generated. Generated s-parameter data then will be used for
RX and TX simulation topology that will be discuss later.
Fig. 5: RX connections on ADS tool.
Fig. 6: TX connections on ADS tool.
The TX and RX models need to be use in separate test
bench to optimize the equalization and pre-emphasis setting
as shown in Fig. 7 and 8.
Fig. 7: RX Test Bench Setup
Fig. 8: TX Test Bench Setup
For RX test bench, DS125DF111 will equalize and retime
the data transmitted by the FSP+ module connector. Due to
that, it is not necessary to speed numerous simulation cycles
optimizing the eye at retime output. For TX test bench,
numerous model-specific parameter will be tested to optimize
the eye diagram opening by controlling the VOD, DE and
DE_Range value based on user guides table setup.
IV. RESULT AND DISCUSSION
The experiment consists of two stages that is a 3D
Electromagnetic (EM) Solver Simulation for TX and RX
differential nets and a Signal Integrity Simulation for TX and
RX Topology. The following is the experiment result and
discussion details for this works.
A. 3D Electromagnetic (EM) Solver Simulation for RX
a) Differential net name: SFP_RX0_P and
SFP_RX0_N.
b) Simulation conditions: 25°C & DC to 20GHz.
c) Generated s-parameter & symbol:
70
Authorized licensed use limited to: University of Edinburgh. Downloaded on June 15,2020 at 07:09:26 UTC from IEEE Xplore. Restrictions apply.

4. Fig. 9: Generated RX symbol
d) Fig. 10 shows the return loss and insertion loss
result.
Fig. 10: RX Return Loss & Insertion Loss
B. 3D Electromagnetic (EM) Solver Simulation for TX
e) Differential net name: SFP_TX0_P and
SFP_TX0_N.
f) Simulation conditions: 25°C & DC to 20GHz.
g) Generated s-parameter & symbol:
Fig. 11: Generated TX symbol
h) Fig. 12 shows the return loss and insertion loss
result.
Fig. 12: TX Return Loss & Insertion Loss
The generated s-parameter results show the behavior of
the passive channel from DC to 20GHz. Generated symbol
will be use in the TX and RX topology for signal integrity
simulation of the high-speed serial link system.
C. RX Test Bench
This experiment will use the topology setup as shown in
Fig. 7. The test 1 is operated at 10.3125Gbps and the test 2
operates at 16Gbps as shown in Fig. 13 and Fig. 14 below.
Fig. 13: RX Test 1 at 10.3125Gbps
Fig. 14: RX Test 2 at 16Gbps
The result shows that the eye-opening at 10.3125 GHz
is larger than 16GHZ. The voltage at 10.3125 GHz is 0.7V
compared to 0.6V at 16GHz. The eye opening is considered
large enough and will be further equalize and re-timer by
DS125DF111 chip.
D. TX Test Bench
This experiment will use the topology setup as shown in
Fig. 8.
Fig. 15: Simulation Results Test at 10.3125Gbps
Fig. 15 shows the test at 10.3125Gbps. This graph
shows that at the eye-opening can be optimize with the
setting of de-equalization (DE) and voltage on demand
(VOD).
71
Authorized licensed use limited to: University of Edinburgh. Downloaded on June 15,2020 at 07:09:26 UTC from IEEE Xplore. Restrictions apply.

5. Fig. 16: Simulation Results Test at 16Gbps
Fig. 16 shows the test at 16Gbps. The DE and VOD
setting not able to optimize the eye-opening since the retimer
IC specification is only at 9.8 to 12.5Gbps even though FSP+
standard can go to 16Gbps.
Fig. 17: Simulation Results Test at 10.3125Gbps – Variable
at DE
Fig. 17 shows the test result at 10.3125Gbps and the
VOD value is fixed. The eye-opening at DE=0 is larger
compare to DE=3 and DE=7.
Fig. 18: Simulation Results Test at 10.3125Gbps – Variable
at VOD
Fig. 18 shows the test result at 10.3125Gbps and the DE
value is fixed. The eye-opening at VOD=6 (1.2V) is larger
compare to VOD=0 (600mV) and VOD=4 (1.0V).
V. CONCLUSION
This study shows the overview of signal integrity
simulation and analysis of the SFP+ interface serial-link
using ADS simulation tool from Keysight. It shows that the
understanding of IBIS-AMI is important to optimize the eye-
opening results. In this study, the configuration of IBIS-AMI
could get the optimized eye-diagram at DE=0 (0dB) gain,
VOD=6 (1.2V) and DE_range=0 at TX. While at RX, not
much equalization needed, the default setting given a large
enough eye-diagram result.
The setting of equalization at transmitter and receiver can
help to get better signal at multi-gigabit serial-link based on
the vendor IBIS-AMI. Another factor is the package and
passive channel behavior also is an important factor for a
good signal quality. This can be seen in this simulation where
the behavior of the package and the passive channel
properties are taken into consideration in the topology setup.
The right modeling technique and topology setup is also
very important to be consider in signal integrity simulation.
For future, this study can continue with power-aware signal
integrity where the effect of Power Integrity will be
considered.
ACKNOWLEDGMENT
The author would like to thank the staff members that
involve with the project and as a result this paper can be
realized.
REFERENCES
[1] Bob Sullivan, Michael Rose, and Jason Boh, “Simulating High-
Speed Serial Channels with IBIS-AMI Models”, Application Note: Keysight
Technologies, October 9, 2018.
[2] Harry Fu, Romi Mayder, and Ian Zhuang, “Multi-Gigabit Serial
Link Simulation with Xilinx 7 Series FPGA GTX Transceiver IBIS-AMI
Models” White Paper: 7 Series FPGA, September 28, 2012.
[3] Jinsong Hu and Runjing Zhou, “High-Speed SFP+ Signal Integrity
Simulation and Measurement”, Journal of Communication and Computer,
vol. 11, pp. 371-377, 2014.
[4] EDA Expert in Signal, Power Integrity and Simulation (SPISim)
(2015). IBIS Model: IBIS AMI Modeling Flow. Retrieved from
http://www.spisim.com/blog/ibis-model-ibis-ami-modeling-flow/
[5] Mike Peng Li, (2007), “Jitter, Noise, and Signal Integrity at High-
Speed”, Prentice Hall, Boston, MA, Pearson Education Inc.,
[6] David R. Stauffer, et. al, (2008), “High Speed Serdes Devices and
Applications”, Springer, Ney York, NY, Springer Science+Business Media.
72
Authorized licensed use limited to: University of Edinburgh. Downloaded on June 15,2020 at 07:09:26 UTC from IEEE Xplore. Restrictions apply.