OFDM based baseband Receiver

1
Chapter 1
Introduction
1.1 Introduction
Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier modulation
technique that has gained considerable attention for the past few years. It is a special case of
frequency division multiplexing (FDM). OFDM has been widely adopted by many new and
emerging broadband wireless/wire-line digital communication systems for its robustness
against inter symbol interference (ISI) and inter carrier interference (ICI) and its high spectral
efficiency.
1.2 OFDM
OFDM is the combination of both modulation and multiplexing. It is known that
modulation is the process of changing of carrier frequency, phase or amplitude or
combination according to the data signal and multiplexing is a method of sharing the
bandwidth with other independent data channels. Generally multiplexing refers to
independent signals, those produced by different sources but coming to OFDM multiplexing
refers to independent signals but these independent signals are a subset of the one main
signal. In OFDM the signal itself is first split into independent channels, modulated by data
and then re-multiplexed to create the OFDM signal.
In OFDM high speed input data stream is converted into several low speed parallel
data streams and are modulated using a large number of closely spaced orthogonal frequency
subcarriers. The main concept in OFDM is orthogonality of the sub-carriers. As these
subcarriers are orthogonal, they do not interfere with each other. The orthogonality of these
subcarriers allows simultaneous transmission of modulated data on a large number of sub-
carriers in a tight frequency space without interference from each other. In essence this is
similar to CDMA, where orthogonal codes are used to make data sequences independent,
which allows many independent users to transmit the data in same space successfully.

2
1.2.1 Advantages and Applications of OFDM
The primary advantage of OFDM over single-carrier modulation schemes is its ability
to cope with severe channel conditions without any complex equalization filters. It is robust
against attenuation of high frequencies in a long copper wire, inter carrier interference and
frequency selective fading due to multipath propagation. Channel equalization in OFDM
system is simplified because OFDM uses many slowly modulated narrow band signals rather
than using one rapidly modulated wideband signal. The low symbol rate in OFDM makes the
use of a guard interval between symbols affordable, making it possible to eliminate inter
symbol interference (ISI).
This is the main advantage of OFDM over FDM. In FDM the data is transmitted over
several carriers which are far apart from each other. The useful data bands are separated by
guard bands to avoid the inter carrier interference (ICI) causing inefficient spectrum
utilization. The usage of guard bands is eliminated in OFDM using the closely spaced
orthogonal subcarriers and the spectrum efficiency is increased. As the subcarriers are
orthogonal to each other they do not interfere with each other.
OFDM is more immune to selective channel fading than single carrier modulation
techniques since it divides the total channel into number of narrowband sub channels, where
the frequency selective fading to broad OFDM signal becomes the flat fading to the
corresponding sub channels. The channel estimation and equalization in OFDM is much
simpler than CDMA or any spread spectrum techniques[13], since it divides total bandwidth
into number of sub channels.
OFDM[12] is widely used in different applications such as Digital Audio
Broadcasting (DAB), Digital Video Broadcasting (DVB), 4G Mobile Communications,
Digital Subscriber Line (DSL) Internet Access, Wireless Local Area Network (WLAN)
called as Wi-Fi based on IEEE 802.11a specifications, power line networks.
Any communication technique has its own advantages and disadvantages. Like that
OFDM is also having some disadvantages such as high peak to average power ratio (PAPR),
requirement of high synchronism accuracy. Due to high peak to average power ratio, OFDM
system requires high linear power amplifiers otherwise the peaks will be distorted. There are
different techniques to reduce the PAPR such as windowing, scrambling etc. Even for a small
frequency offset the orthogonality among subcarriers is lost, causing the inter carrier

3
interference, and the information modulated on these subcarriers is corrupted or lost. So to
eliminate the frequency offsets, frequency offset estimation and correction techniques should
be used making the OFDM receiver more complex.
1.2.2 OFDM RelatedTechnologies
Single Input and Single Output (SISO) OFDM is the one in which only one
transmitting antenna and one receiving antenna are used for transmission. If multiple
transmitting and receiving antennas are used for transmission then it is called Multiple Input
Multiple Output (MIMO) OFDM. MIMO-OFDM uses space time codes to ensure that the
signals transmitted over the different antennas are orthogonal to each other. Orthogonal
Frequency Division Multiple Access (OFDMA) is the combination of OFDM with Time
Division Multiple Access (TDMA), in which number of time slots are allotted for different
users. Multi-Carrier Code Division Multiple Access (MC-CDMA)[14] is multi user version
of OFDM with the combination of CDMA. Coded OFDM (COFDM) is a form of OFDM in
which error correction coding is incorporated into the OFDM signal. OFDM with CDMA
will be the future scope for the need of higher data rates for transferring high definition
videos and audios, online gaming, entertainment etc.
1.3 Literature Survey on Implementation of OFDM System
As OFDM is an emerging technology, many scholars are working on it and they
implemented OFDM system using different software and hardware. OFDM system can be
simulated using the softwares MATLAB, VHDL, VERYLOG, and C++ and it can be
implemented on hardware such as ASICs, DSPs, FPGAs, and combination of DSP, FPGA.
M Jose Canet, Felip Vicedo, Vicenc Almenar, and Javier Valls [1] designed an
intermediate frequency (IF) Transceiver for OFDM Based WLAN with 64 point FFT and 16
samples in cyclic prefix. In this 52 subcarriers are used in which 48 for data and 4 pilots and
QAM is used as mapping technique. The transmitted signal at 20 MHz is up converted to 45
MHz and at the receiver down converted back. They also implemented the carrier frequency
offset estimation and correction using preambles. But in the present project IF used is 14

4
MHz. Christoph Sonntag [2] implemented a basic 802.11a OFDM transceiver as part of
Software Defined Radio (SDR) in software domain using C++. In this OFDM transceiver is
developed with 64 point FFT and used 52 subcarriers in which 48 are for data transmission
and 4 for pilot data transmission. In this system, up conversion and down conversion are not
implemented. The designed system is intended to implement on embedded system hardware
platform but not actually implemented on hardware. But in the present project hardware
implementation on Spartan-3 FPGA is done.
Khaled Sobaihi, Akram Hammoudeh, and David Scammell [3] Implemented an
OFDM Transceiver for a 60GHz Wireless Mobile Radio System on FPGA. They used 16
QAM for mapping and 64 point IFFT for modulation and upconverted the baseband
transmitted signal of 10 MHz to 62.4 GHz with intermediate frequency of 2.4 GHz, but they
did not consider the pilots and cyclic prefix. Lenin Gopal, Daniel Wong Sing Tze, and Nur
Zawanah Ishak [4] designed an FPGA Based OFDM Transceiver for DVB-T Standard. They
used QPSK for symbol mapping and 4096 point FFT for OFDM modulation and did not
consider the pilots and cyclic prefix. The implementation is done using Altium Designer
software and the IFFT/FFT modules were implemented using Altera’s FFT Mega Core
function. The design is implemented on Altera Cyclone III device but in the present project
the design is implemented on Spartan-3 FPGA.
Yin-Tsung Hwang, Sung-Jun Tsai, and Yi-Yo Chen [5] Designed and Implemented
an Optical OFDM Baseband Receiver in FPGA. The designed receiver consists of 64 point
FFT and 64 QAM for symbol demapping. They used 48 sub carriers for data, 4 for pilots and
12 are DC & null subcarriers. The cyclic prefix of 8 samples is used for symbol timing and
frequency synchronization. Shaminder kaur and Rajesh Mehra [6] implemented OFDM
Transceiver using FFT algorithm on Vertex-2 Pro FPGA. In their design, they used 512 point
FFT, and QAM modulator. Michael Mefenza and Christophe Bobda [7] developed a
subcarrier index modulation for OFDM transceiver. In this system, they used 4-QAM for
symbol mapping and demapping, 256 point FFT/IFFT for modulation and demodulation. But
the pilots and cyclic prefix are not used in the design. But in the present project pilot insertion
and cyclic prefix insertion are considered and QPSK is used for symbol mapping.

5
Akash Mecwan and Dhaval Shah [8] implemented an OFDM Transceiver on Vertex-5
FPGA as per the specifications of IEEE 802.11g for 54 Mbps data rate applications. The
design consists of serial to parallel conversion, 64-QAM for symbol mapping, 64 point IFFT
for modulation, 64 point FFT for demodulation, 64 DQAM for symbol demapping and
parallel to serial converter. P. Sadhasivam and Dr. M. Manikandan [9] designed and analysis
an OFDM transceiver with novel architecture on FPGA. For encoding and decoding, 4 QAM
is used and for modulation and demodulation 64 point IFFT/FFT are used. The cyclic prefix
is used but pilots are not used in the implementation but in the present project pilots and
cyclic prefix are considered while designing.
Nasreen Mev and Brig R.M. Khaire [10] developed an OFDM transmitter and
receiver using FPGA. The system is designed using 64 point FFT and used all subcarriers for
data transmission and used a cyclic prefix of 8 samples and used Reed Solomon code and
convolution code for channel coding. Tirumala Rao and Mohith [11] implemented an OFDM
transmitter and receiver for reconfigurable platforms. They have developed codes in VHDL
using Xilinx ISE and Modelsim and implanted it on Spartan-3E FPGA using ChipScope
tools. The system consists of only QPSK symbol mapper and demapper, 8 bit serial to
parallel and 8 bit parallel to serial converter and 8 point FFT and IFFT. But pilots and cyclic
prefix are not used in their design.
After studying the research work done by different scholars, an improved OFDM
based baseband receiver with high reliability and low complexity is designed as per the
industrial requirements which pertains to 802.11a. In the design of system pilots and cyclic
prefix are considered and down converter is also designed to down convert the IF signal at 14
MHz to baseband signal centered at DC with a bandwidth of 10.5 MHz. For the OFDM
signal demodulation 64 point FFT is used, and in total 64 subcarriers, 48 subcarriers are used
for data transmission, 8 are used for pilots and 8 are DC & null subcarriers. The length of the
cyclic prefix used is 8 samples and QPSK demodulator is used as symbol demapper.

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1.4 Focus on Present Project
For industrial requirements the software simulation is not sufficient, it requires both
software and hardware implementation. As per the industrial requirements the OFDM based
baseband receiver has to be implemented on FPGA with high reliability and low complexity
using the Xilinx IP Cores.
It is proposed to study and simulate the various blocks associated with OFDM based
baseband receiver, namely digital down converter which is integration of mixer, low pass
filter and down sampler, followed by cyclic prefix remover, 64 point FFT block which
includes 64 bit serial to parallel converter and 64 bit parallel to serial converter, pilot
extractor, and symbol demapper with reference to block diagram on software using VHDL
coding. In this project, it is also proposed to implement the above mentioned blocks on
hardware such as FPGA.
The prime on the project is on simulation and development of blocks of OFDM based
baseband receiver consists of digital down converter which is an integration of mixer, low
pass filter and down sampler, followed by cyclic prefix remover, 64 point FFT block which
includes 64 bit serial to parallel converter and 64 bit parallel to serial converter, pilot
remover, and QPSK symbol demapper excluding RF section, synchronization block, channel
estimation and channel equalization blocks, and integration of these blocks, hardware
implementation of OFDM based baseband receiver and evaluation of performance of the
blocks individually as well as after integration to make OFDM based baseband receiver.
First the feasibility of implementation of OFDM system is checked using simulation
in MATLAB 7.10. After successful simulation results all the blocks of OFDM based
baseband receiver which are mentioned above are simulated in VHDL using Xilinx ISE
Design Suite 13.2 software. After successful simulation results of individual blocks, they are
integrated to make OFDM based baseband receiver and is implemented on Spartan-3 FPGA
using ChipScope Pro Tool. The digital to analog converter (DAC5682Z) is configured to the
FPGA and the output of the DAC is fed to spectrum analyzer (HP8593E). The spectrum
outputs of different signals at different stages of OFDM based baseband receiver are
observed. The designed OFDM based baseband receiver is tested using OFDM based
baseband transmitter designed in the lab and the outputs are observed in ChipScope tool.

7
This model is the proposed engineering model of OFDM based baseband receiver and
it pertains to IEEE 802.11a with the specifications as per the industry requirements. The
specifications are as given below.
Specifications of the project
Data rate of OFDM symbol with cyclic prefix 10.5 Mbps
Data rate of OFDM symbol after removal of cyclic prefix 9.333 Mbps
Data rate of demodulated signal with pilots 9.333 Mbps
Data rate of demodulated signal after removal of pilots 7 Mbps
Output data rate after demapping 14 Mbps
Total no. of subcarriers of OFDM 64
No. of user data subcarriers 48
No. of pilot subcarriers 8
No. of null subcarriers 8
No. of samples in OFDM symbol with cyclic prefix 72
No. of samples in cyclic prefix 8
No. of samples in OFDM symbol after removal of cyclic prefix 64
Bandwidth of the OFDM signal 10.5 MHz
Subcarrier spacing 164.0625 KHz
Carrier frequency 14 MHz
Mapping technique QPSK

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1.5 Thesis Organization
The thesis is organized in 8 Chapters as follows. In Chapter-1, Introduction to OFDM,
advantages and applications of OFDM, OFDM related technologies, literature survey on
implementation of OFDM transceiver, focus on the present project will be studied. Basic
concepts of OFDM and OFDM Receiver, feasibility of design of OFDM system, and blocks
which have to be simulated and implemented will be discussed in Chapter-2. Chapter-3 deals
with concept, design and implementation of digital down converter which includes digital
mixer, low pass filter, and down sampler. In Chapter-4, use of concept of cyclic prefix,
reason for use of FFT in OFDM demodulation and the implementation of CP remover and
FFT will be explained.
Chapter-5 analyzes different channel estimation techniques, QPSK modulation &
demodulation and design and implementation of pilot extractor and symbol demapper.
Chapter-6 gives the details of integration of designed modules, tools used for hardware
implementation, and problems occurred in hardware implementation and their solutions.
Chapter-7 explains the process of OFDM synchronization and different carrier frequency
offset estimation techniques and MATLAB simulation of ML estimation, modified Van de
Beek algorithm, Schmidl and Cox algorithm. Chapter-8 discusses about the results of
different tests conducted for evaluation of performance of designed modules and conclusion
of the project.

9
Chapter 2
OFDM Based Baseband Receiver
2.1 Introduction
To design an OFDM receiver, it is important to know the concepts, principles,
characteristics of OFDM and the basic blocks used in OFDM system. After getting the proper
knowledge on OFDM system, the basic OFDM system is designed in MATLAB Simulation
and its feasibility is tested for different SNR values. All of these will be discussed in this
Chapter. Also the OFDM based baseband receiver blocks which are designed in this project
are also studied.
2.2 Basic Principle of OFDM
In frequency division multiplexing (FDM), the data is modulated using number of
carriers far apart from each other, and there is no relationship among these carriers. The
useful data bands are separated by guard bands to avoid the inter carrier interference (ICI).
But the usage of guard bands causes inefficient spectrum utilization. The spectrum of FDM
signal is as shown in the Fig. 2.1.
Fig. 2.1 Spectrum of FDM signal
Coming to OFDM the data is transmitted over number of closely spaced orthogonal
subcarriers. As the subcarriers are closely spaced and overlapped with each other, the
efficiency of spectrum utilization is high. Even though the subcarriers are closely spaced,
f1 f2 f3
Guard bands
Useful databands

10
they do not interfere with each other because of orthogonality among them. The orthogonality
is a principle that any two orthogonal signals do not interfere with each other. Two signals
are said to be orthogonal if and only if area under the product of the two is zero.
Mathematically the condition for orthogonality is expressed as follows. Two time domain
signals x1(t), x2(t) are said to be orthogonal, if and only if they satisfy the following
condition.
𝐥𝐢𝐦
𝑻→∞
𝟏
𝟐𝑻
∫ 𝒙 𝟏( 𝒕). 𝒙 𝟐
∗
(𝒕)
𝑻
−𝑻
𝒅𝒕 = 𝟎
The spectrum of the OFDM signal is as shown in the Fig. 2.2. The peak of one
subcarrier coincides with the valley of other subcarriers, thus they do not interfere with each
other, even though they are overlapped.
Fig. 2.2 Frequency domain representation of orthogonal signals
In general all the sinusoidal signals, complex exponential signals with the frequencies
as the integer multiples of a fundamental frequency are orthogonal signals because they
follow the orthogonal condition.

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Let x1(t) = sin(2**m*t/T) and x2(t) = sin(2**n*t/T) are two sinusoidal signals with
frequencies as the integer multiples of a fundamental frequency (f0=1/T). (where m, n are two
integers.) Then
∫ 𝒙 𝟏( 𝒕). 𝒙 𝟐
∗ ( 𝒕)
𝑻
−𝑻
𝒅𝒕 = ∫ 𝒔𝒊𝒏 (𝟐 ∗ 𝝅 ∗ 𝒎 ∗
𝒕
𝑻
) . 𝒔𝒊𝒏∗
(𝟐 ∗ 𝝅 ∗ 𝒏 ∗
𝒕
𝑻
)
𝑻
−𝑻
𝒅𝒕
= 𝟐 ∫ 𝒔𝒊𝒏 (𝟐 ∗ 𝝅 ∗ 𝒎 ∗
𝒕
𝑻
) . 𝒔𝒊𝒏 (𝟐 ∗ 𝝅 ∗ 𝒏 ∗
𝒕
𝑻
)
𝑻
𝟎
𝒅𝒕
= 𝟐 ∫
𝟏
𝟐
[𝒄𝒐𝒔 (𝟐 ∗ 𝝅 ∗ ( 𝒎 − 𝒏) ∗
𝒕
𝑻
) − 𝒄𝒐𝒔 (𝟐 ∗ 𝝅 ∗ ( 𝒎 + 𝒏) ∗
𝒕
𝑻
)]
𝑻
𝟎
𝒅𝒕
If m=n0 then
= ∫ [𝟏 − 𝒄𝒐𝒔 (𝟒 ∗ 𝝅 ∗ 𝒏 ∗
𝒕
𝑻
)]
𝑻
𝟎
𝒅𝒕
= [𝒕 −
𝑻
( 𝟒 ∗ 𝝅 ∗ 𝒏)
𝒔𝒊𝒏 (𝟒 ∗ 𝝅 ∗ 𝒏 ∗
𝒕
𝑻
)]
𝟎
𝑻
= [𝑻 −
𝒔𝒊𝒏( 𝟒 ∗ 𝝅 ∗ 𝒏)
( 𝟒 ∗ 𝝅 ∗ 𝒏)
] = 𝑻
If mn then
= ∫ [𝒄𝒐𝒔 (𝟐 ∗ 𝝅 ∗ ( 𝒎 − 𝒏) ∗
𝒕
𝑻
) − 𝒄𝒐𝒔 (𝟐 ∗ 𝝅 ∗ ( 𝒎 + 𝒏) ∗
𝒕
𝑻
)]
𝑻
𝟎
𝒅𝒕
= [
𝒔𝒊𝒏(𝟐 ∗ 𝝅 ∗ (𝒎 − 𝒏) ∗
𝒕
𝑻
)
𝟐 ∗ 𝝅 ∗ (𝒎 − 𝒏)
−
𝒔𝒊𝒏 (𝟐 ∗ 𝝅 ∗ ( 𝒎 + 𝒏) ∗
𝒕
𝑻
)
𝟐 ∗ 𝝅 ∗ ( 𝒎 + 𝒏)
]
𝟎
𝑻
= [
𝒔𝒊𝒏(𝟐 ∗ 𝝅 ∗ (𝒎 − 𝒏))
𝟐 ∗ 𝝅 ∗ (𝒎 − 𝒏)
−
𝒔𝒊𝒏(𝟐 ∗ 𝝅 ∗ ( 𝒎 + 𝒏))
𝟐 ∗ 𝝅 ∗ ( 𝒎 + 𝒏)
]
= 𝟎

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Hence it is proved that any two sinusoidal signals that are having frequencies as
integer multiples of a fundamental frequency are orthogonal. Similarly orthogonality of
complex exponential signals can be proved. So the time domain representation of orthogonal
signals is as shown in the Fig. 2.3.
Fig. 2.3 Time domain representation of sinusoidal orthogonal signals
2.3 Basic Architecture of OFDM
In basic OFDM, the input serial data stream is converted into N parallel data streams.
Each data stream is modulated using one of the orthogonal complex subcarriers 𝑒 𝑗𝑤 𝑛 𝑡
where
n=0,1,2,..,N-1. Then these modulated N parallel data streams are multiplexed to get the
OFDM signal. This OFDM signal is passed through the channel, and at the receiver the
OFDM signal is multiplied with the orthogonal complex subcarriers 𝑒−𝑗𝑤 𝑛 𝑡
where
n=0,1,2,..,N-1 to get the N parallel data streams. The parallel data streams are passed through
the parallel to serial converter to get the output data. The basic architecture of the OFDM
model is shown in Fig. 2.4.

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Fig. 2.4 Basic architecture of OFDM Model
The generation of these orthogonal subcarriers is a difficult task and modulating the
data using these subcarriers is a complex process, if the N value is large. Because it requires
N local oscillators and the carriers generated must be stable at the orthogonal frequencies.
Even the small change in the carrier frequencies causes the loss of orthogonality among the
subcarriers. If this method is used for the subcarriers generation the complexity of OFDM
system is very high. Fortunately Discrete Fourier Transform (DFT) coefficients are
orthogonal. Applying DFT to a signal is equivalent to modulating it with N orthogonal
subcarriers. Thus the complexity of OFDM system is reduced by using FFT/IFFT for
generation of orthogonal subcarriers.
2.4 Introduction to Cyclic Prefix
In wireless channel, due to multipath propagation and fading the broadening of
symbol occurs. The broadening of the symbols causes the interference of one symbol with the
next symbol. This is called as inter symbol interference (ISI). Due to ISI the start of the
symbol will be lost.
Due to Doppler Effect, the frequency of subcarriers changes, which will cause the loss
of orthogonality among the subcarriers. As these subcarriers are closely spaced and if the
Data outData in
Serial
to
Parallel
Sum
𝒆𝒋𝒘 𝟎 𝒕
𝒆𝒋𝒘 𝟏 𝒕
𝒆𝒋𝒘 𝑵−𝟏 𝒕
....
Channel
𝒆−𝒋𝒘 𝟎 𝒕
𝒆−𝒋𝒘 𝟏 𝒕
....
Parallel
to
serial
𝒆−𝒋𝒘 𝑵−𝟏 𝒕

14
orthogonality is lost, the subcarriers will interfere with each other. This is called as inter
carrier interference (ICI). Due to ICI the information in the subcarriers is lost/ corrupted.
To avoid the inter symbol interference (ISI) and inter carrier interference (ICI), cyclic
extensions (cyclic prefix, cyclic postfix) are used. Normally cyclic prefix is used. Cyclic
prefix is the addition of a part of the tail of OFDM symbol at the start of the OFDM symbol.
The inter symbol interference (ISI) due to symbol spreading is shown in Fig. 2.5 and cyclic
prefix extension used to avoid the inter symbol interference (ISI) is shown in Fig. 2.6.
Fig. 2.5 Inter Symbol Interference due to Symbol Broadening
Fig. 2.6 Cyclic Prefix is inserted to avoid Inter Symbol Interference
2.5 Introduction to Pilots
In wireless medium, the channel characteristics are both time varying and frequency
varying. If the OFDM signal is transmitted into this channel, it undergoes channel effects. To
recover the original transmitted data from the received signal, the channel effects have to be
equalized. For this, first the channel characteristics have to be estimated. Using this estimated
Cyclic prefix
Transmitted symbol length
Receivedsymbol length
Guard band
InterSymbol Interference
Transmittedsymbol length
Receivedsymbollength

15
channel characteristics, the channel equalization is done. There are number of methods for
the channel estimation, mainly they are divided into two groups.
i. Non data aided channel estimation
ii. Data aided channel estimation
In non data aided channel estimation, no additional data is transmitted along the user
data, the channel estimation is done using the channel statistics and some of the transmitted
signal properties. For this channel estimation long data records are required, hence it is not
applicable to fast fading channel. For fast fading channels, data aided channel estimation
techniques are used. In data aided channel estimation techniques, training symbols or pilot
data bits are inserted into the user data bits which are known prior to the receiver. As the pilot
bits are known prior to receiver, it is easy to estimate the channel characteristics.
2.6 Basic Blocks of OFDM System
As basic principle of OFDM, basic architecture of OFDM system, introduction to
cyclic prefix, introduction to pilots are studied briefly, now it is easy to understand the basic
block diagram of OFDM system. The basic block diagram of the OFDM system is shown in
the Fig. 2.7.
Fig. 2.7 Basic block diagram of the OFDM system
Output
data
ADC RF-Rx
Module
Timing &
Frequency
Synchronizer
S/P
Cyclic
Prefix
Remover
Symbol
Demapper
Channel
Equalizer
Pilot
Extractor
P/S FFT
Channel
Estimator
Input
data
Symbol
Mapper
Pilot
Inserter
DAC RF-Tx
Module
S/ P IFFT P/ S
Cyclic
Prefix
Inserter
Symbol
Shaping

16
The first block in the transmitter of OFDM system is symbol mapper. It is used to
map the digital data bits to amplitude and phase values and placed at correct locations in the
frequency spectrum. The pilot insertion block, inserts the pilot bits into the actual user data
for channel estimation at the receiver. Then the serial data is converted into parallel data
using serial to parallel converter. This parallel data is fed to IFFT block to convert the
frequency domain data into time domain data. The output of the IFFT block is a parallel time
domain data, it is fed to parallel to serial converter to get the serial data. The cyclic prefix
insertion block adds the cyclic prefix to the OFDM symbols to avoid ISI and ICI. The cyclic
prefix is also used to find the start of the OFDM symbol at the receiver. These OFDM
symbols are given to digital to analog converter (DAC) to get the analog baseband OFDM
signal. This analog OFDM signal is up converted and transmitted into wireless radio channel
using radio frequency transmitter (RF-Tx) module.
Coming to the receiver part of the OFDM system, first the received OFDM signal is
down converted using the radio frequency receiver (RF-Rx) module and it is converted into
digital format using the analog to digital converter (ADC).
In synchronization block, frame synchronization, carrier frequency and phase offset
estimation, clock frequency offset and delay estimation are done. The synchronization block
in receiver is the heart of the OFDM system. Then OFDM symbols are fed to the cyclic prefix
remover for removal of cyclic prefix. The serial to parallel converter converts the serial data
into N parallel data streams. The parallel data is fed to FFT block for demodulation. The FFT
block converts the time domain signal into frequency domain signal. The output parallel data
is converted into serial data using the parallel to serial converter.
The pilot extractor extract the pilot bits from user data, pilot bits are fed to channel
estimator for channel estimation and user data is fed to channel equalizer. The estimated
channel characteristics are used to equalize the user data. The output of the equalizer is actual
user data that is in frequency domain with amplitude and phase. Symbol Demapper takes the
complex data and gives the corresponding digital data bits.

17
2.7 Testing of Feasibility of Implementation of OFDM System Using MATLAB
Simulation
In this project, first the feasibility of implementation of OFDM model is tested in
MATLAB Simulation using MATLAB 7.10. Additive White Gaussian Noise (AWGN)
channel is used to transmit the OFDM signal. By varying the signal to noise ratio (SNR), the
performance of the model is tested. It gives zero bit error rate (BER), up to -15dBm SNR. For
SNR -16dBm, it is giving 0.01 BER. The MATLAB simulation of OFDM system is shown in
Fig. 2.8 and BER performance for given SNR values are shown in the Figs. 2.9 and 2.10.
Fig. 2.8 OFDM Model with AWGN channel
Fig. 2.9 Input and Output data streams with BER=0% when the SNR = -11dBm

18
Fig. 2.10 Input and Output data streams with BER=0.9% when the SNR = -16dBm
2.8 Focused blocks of OFDM BasedBaseband Receiver
In this project, OFDM baseband receiver modules which are necessary for ideal case
transmission are focused. All the blocks are designed in digital domain using VHDL coding
in FPGA. Focused blocks are shown in the Fig. 2.11 with continuous outline and dashed
outline blocks. Continuous outline blocks are designed and implemented, and dashed outline
blocks are not implemented in this project.
Fig. 2.11 Basic block diagram of OFDM receiver
The output of the transmitter in digital format is taken as the input to the designed
receiver. The output of is in digital form and the designed receiver modules also in digital
domain, hence there is no need of radio frequency receiver module and ADC. The output of
the transmitter is taken directly without passing through any channel hence there is no need
of synchronization, channel estimation and channel equalization blocks. The remaining
blocks of OFDM based baseband receiver namely digital down converter which is an
Output
data
ADCRF-Rx
Module
Timing &
Frequency
Synchronizer
S/P
Cyclic
Prefix
Remover
Symbol
Demapper
Channel
Equalizer
Pilot
Extractor
P/SFFT
Channel
Estimator
Digital
Down
Converter

19
integration of mixer, low pass filter and down sampler, followed by cyclic prefix remover, 64
point FFT block which includes 64 bit serial to parallel converter and 64 bit parallel to serial
converter, pilot remover, and QPSK symbol demapper are simulated in VHDL using Xilinx
ISE Design Suite 13.2. After successful simulation, all modules are integrated to make
OFDM based baseband receiver and implemented on Spartan-3 FPGA using ChipScope Pro
Tool.
2.9 Result
The feasibility of implementation of OFDM based baseband receiver is tested using
MATLAB simulation. The system gives zero BER up to -15 dBm SNR and results are
satisfactory.
In the following Chapter, about the first module of the designed OFDM based
baseband receiver i.e. digital down converter (DDC) will be studied. The concept and
development of sub blocks of digital down converter namely mixer, low pass filter and down
sampler, and their implementation in FPGA will be studied.

20
Chapter 3
Digital Down Conversion in OFDM
3.1 Introduction
Nowadays up conversion and down conversion are doing in digital domain for its
reliability of digital systems. In this project also the down converter is designed and
implemented in digital domain. The sub blocks of digital down converter (DDC), their
functioning and how they are designed /implemented in this project will be studied in this
Chapter.
3.2 Digital Down Converter
DDC converts a bandpass signal centered at an intermediate frequency to a baseband
signal centered at dc frequency. It also down samples the signal to lower sampling rate for the
low speed devices which have to process the signal. As the received signal is the up
converted OFDM signal centered at the carrier frequency of 14 MHz with the sampling rate
of 84 Mbps, the down converter is used to convert this signal to baseband signal centered at
zero frequency and a lower sampling rate of 10.5 Mbps.
Down converter is the combination of following modules.
i. Mixer
ii. Low Pass Filter
iii. Down Sampler
The mixer is used to change the frequency band of the signal and low pass filter is
used to eliminate the higher frequencies. The down sampler resamples the signal with low
sampling rate. The block diagram of digital down converter is shown in Fig. 3.1.
Fig. 3.1 Block diagram of digital down converter
Low Pass
Filter
Down
Sampler
Data in Data out
LO
Mixer
Local
Oscillaor

21
3.2.1 Mixer
Mixer is the one which is used to shift signals from one frequency range to another. It
multiplies the locally generated carrier signal to the input signal such that the spectrum of the
input signal will shift by the frequency of locally generated carrier. If the input signal
frequency is f and the locally generated carrier signal frequency is fc, the frequency of the
output signal is ±f±fc. In any wireless communication system, the signal has to be up
converted for transmission and at the receiver the received signal is down converted. Hence
mixers are used at both transmitter and receiver.
Let x(t) is a baseband signal centered at dc with a bandwidth of fm MHz. Let
cos(2πfct) is the carrier signal that used to up convert signal x(t). The output of the
transmitter is the up converted signal x(t)cos(2πfct) which is centered at the carrier frequency
fc. At the receiver the local oscillator generates the similar carrier cos(2πfct+ 𝜑) where 𝜑 is
the phase shift between the carriers used at the transmitter and at the receiver. The mixer is
used to down convert the received signal, then
Received signal is x(t)cos(2πfct).
Output of mixer is 𝒙( 𝒕) 𝐜𝐨𝐬( 𝟐𝝅𝒇 𝒄 𝒕)∗ 𝐜𝐨𝐬(𝟐𝝅𝒇 𝒄 𝒕 + 𝝋)
= 𝒙( 𝒕)[
𝟏
𝟐
( 𝐜𝐨𝐬( 𝟒𝝅𝒇 𝒄 𝒕 + 𝝋) + 𝐜𝐨𝐬( 𝟐𝝅𝒇 𝒄 𝒕 + 𝝋 − 𝟐𝝅𝒇 𝒄 𝒕))]
= 𝒙( 𝒕)[
𝟏
𝟐
( 𝐜𝐨𝐬( 𝟒𝝅𝒇 𝒄 𝒕 + 𝝋) + 𝐜𝐨𝐬( 𝝋))]
=
𝟏
𝟐
𝒙( 𝒕) 𝐜𝐨𝐬( 𝝋) +
𝟏
𝟐
𝒙( 𝒕) 𝐜𝐨𝐬( 𝟒𝝅𝒇 𝒄 𝒕 + 𝝋)
If there is no phase offset i.e. 𝜑 = 0 then the mixer output is
=
𝟏
𝟐
𝒙( 𝒕) +
𝟏
𝟐
𝒙( 𝒕) 𝐜𝐨𝐬( 𝟒𝝅𝒇 𝒄 𝒕)
If there is no phase offset or a constant phase offset 𝜑 presents between the
transmitted carrier and locally generated carrier, then the signal can be reconstructed without
any distortion. If the phase offset is varying then the signal will be distorted. The spectrums

22
of the baseband signal, transmitted signal and the mixer output are shown in the following
Figs. 3.2, 3.3 and 3.4, considered there is no frequency offset and phase offset.
Fig. 3.2 Spectrum of a baseband signal x(t)
Fig. 3.3 Spectrum of transmitted signal 𝑥(𝑡)cos(2𝜋𝑓𝑐 𝑡)
Fig. 3.4 Spectrum of mixer output
0 fm-fm
X(f)
1
0-fc-fc-fm
𝟏
𝟐
[ 𝐗(𝐟𝐜+ 𝐟) + 𝐗(−𝐟𝐜+ 𝐟)]
-fc+fm fc-fm fc+fmfc
𝟏
𝟐
0-fm
𝟏
𝟐
[𝐗(𝐟)+
𝟏
𝟐
[𝐗( 𝟐𝐟𝐜 + 𝐟) + 𝐗(−𝟐𝐟𝐜+ 𝐟)]
fm 2fc-fm 2fc+fm2fc
𝟏
𝟐
-2fc-fm -2fc+fm-2fc

23
If there is a frequency offset between transmitter carrier and the locally generated
carrier at the receiver, then what will happen? Let cos(2π(fc+∆f)t) is the locally generated
carrier at the receiver, where ∆f is the frequency offset between transmitter carrier and the
locally generated carrier at the receiver. Then the mixer output will be
𝒙( 𝒕) 𝐜𝐨𝐬( 𝟐𝝅𝒇 𝒄 𝒕)∗ 𝐜𝐨𝐬(𝟐𝝅(𝒇 𝒄 + ∆𝐟)𝒕)
= 𝒙( 𝒕)
𝟏
𝟐
[ 𝐜𝐨𝐬( 𝟐𝝅(𝒇 𝒄 + ∆𝐟)𝒕− 𝟐𝝅𝒇 𝒄 𝒕)+ 𝐜𝐨𝐬( 𝟐𝝅(𝒇 𝒄 + ∆𝐟) 𝒕 + 𝟐𝝅𝒇 𝒄 𝒕)]
=
𝟏
𝟐
𝒙( 𝒕)[ 𝐜𝐨𝐬( 𝟐𝝅∆𝐟𝒕) + 𝐜𝐨𝐬((𝟒𝝅𝒇 𝒄 + ∆𝐟) 𝒕)]
=
𝟏
𝟐
𝒙( 𝒕) 𝐜𝐨𝐬( 𝟐𝝅∆𝐟𝒕) +
𝟏
𝟐
𝒙( 𝒕) 𝐜𝐨𝐬((𝟒𝝅𝒇 𝒄 + ∆𝐟) 𝒕)
Even if there is a constant frequency offset ∆f between transmitter carrier and the
locally generated carrier at the receiver, as time progresses the multiplication factor
𝐜𝐨𝐬( 𝟐𝝅∆𝐟𝒕)changes. Thus it leads to signal distortion or rotation of signal constellation.
Hence in any receiver there is carrier frequency estimator for the proper demodulation and
reconstruction of the original signal.
3.2.1.1Implementation of Mixer
In this project, the received signal is centered at a carrier frequency of 14 MHz. So for
down conversion of the received signal, it is mixed with the similar carrier which is
generated locally. Here it is assumed that there is no frequency offset and phase offset exists
between the carrier used at the transmitter for up conversion and the carrier generated at the
receiver for down conversion. The carrier is generated using the carrier generator program in
VHDL coding. The carrier is a sinusoidal signal with a frequency of 14 MHz and a sampling
frequency of 84 MHz.
Mixer is nothing but a multiplier hence it is implemented using Multiplier IP Core.
Hence the generated carrier is multiplied to the received signal using Multiplier IP Core.
This Multiplier IP Core[20] generates fixed point parallel multipliers and constant
coefficient multipliers for 2’s complement signed and unsigned data. This will accept inputs
ranging from 1 to 64 bits wide and it gives the outputs ranging from 1 to 128 bit wide with
any portion of the full product selectable. It provides configurable latency for all multiplier
variants but it advices to use the optimum latency for the given input data widths. It can be

24
implemented using Look Up Table (LUT)s and it requires more than 50 LUTs but the speed
of optimization is not possible. Hence it is implemented using 18X18 multipliers. By using
these multipliers either speed or the area can be optimized.
In this project, the width of the received signal samples is 16 bits and the width of the
locally generated carrier samples is 4 bits, hence the width of the output is 20 bits and
optimum pipeline stages required is 2 stages i.e. latency is 2 clock cycles. The pin diagram
of multiplier is shown in the Fig. 3.5 and the ports of multiplier are described in the
following Table. 3.1.
Fig. 3.5 Multiplier I/O port diagram
Signal Direction Description
A[N-1:0] Input A operand input bus, N bit wide
B[M-1:0] Input B operand input bus, M bit wide
Clk Input Rising-edge clock input
CE Input Active high clock enable
SCLR Input Active high synchronous clear
P[X:Y] Output Product output – bit X down to bit Y
Table. 3.1 Pin description of multiplier
Using carrier generator program and multiplier, the mixer is implemented
successfully. The input and the output spectrums of the mixer are shown in the following
Figs. 3.6, 3.7 and 3.8. The results are satisfactory, as they are expected outputs.
Multiplier
A
[
B
Product
Clk
CE
SCLR

25
Fig. 3.6 Spectrum of Received OFDM signal without pilots and cyclic prefix, centered at
carrier frequency of 14MHz with a bandwidth of 7MHz and having level -52dBm
Fig. 3.7 Spectrum of Received OFDM signal with pilots and cyclic prefix, centered at
carrier frequency of 14MHz with a bandwidth of 10.5MHz and having level -54dBm (This
received OFDM signal is given as the input to the mixer)

26
Fig. 3.8 Spectrum of output of mixer, having multiple OFDM spectrums each with a
bandwidth of 10.5MHz and having level -50dBm
3.2.2 Low Pass Filter
The output of the mixer contains multiple spectrums centered at frequencies n*fc
where n=0,±1, ±2, ±3... and fc is the carrier frequency. Only the spectrum which is centered
at dc is required and remaining spectrums have to be eliminated. Low pass filter (LPF) is
used for the elimination of unwanted higher frequency components.
Let x(t) is a signal having multiple spectral components and h(t) is the filter impulse
response then the output of the filter is the convolution of input signal with the filter impulse
response. The output of filter y(t) is the convolution of the input signal and filter impulse
response. The convolution in time domain is equivalent to multiplication in frequency
domain. Hence the output of the filter in frequency domain is the product of input signal in
frequency domain and filter response in frequency domain.
Let X(w), H(w) and Y(w) are the frequency domain representations of x(t), h(t) and
y(t) respectively. Then the output of the filter y(t) in time domain and Y(w) in frequency
domain are given the following equations.

27
In time domain, the output of the filter is 𝑦( 𝑡) = 𝑥( 𝑡) ∗ ℎ(𝑡)
In frequency domain, the output of the filter is 𝑌( 𝑤) = 𝑋( 𝑤) 𝐻(𝑤)
The frequency responses of input signal, filter impulse response and output of filter
are shown in the following Figs. 3.9, 3.10 and 3.11 respectively.
Fig. 3.9 Frequency response of signal x(t)
Fig. 3.10 Frequency response of filter
Fig. 3.11 Frequency response of output of filter
frequency
0-fc-fc-fm
𝐗(𝐟)
-fc+fm fc-fm fc+fmfc
1
0 fc-fc
H(f)
frequency
0 fm-fm
Y(f)
1
frequency

28
3.2.2.1 RaisedCosine Filter
Raised cosine filter is used frequently for symbol shaping in digital communication
systems for its ability to immune inter symbol interference (ISI). It is called as raised cosine
filter because the non-zero portion of frequency spectrum of this function is look like a cosine
function raised above. RC filter is an implementation of low pass filter. The mathematical
representation of frequency response of RC filter is given as
The impulse response of the RC filter is given by the following equation
As seen in the above equations, RC filter is characterized by two values. They are
i. Roll of Factor ( 𝛽)
ii. Time period of symbol (T)
Roll of factor ( 𝛽) is a measure of the excess bandwidth of the RC filter i.e. the bandwidth
expanded beyond the actual bandwidth of the signal. If ∆f is the excess bandwidth, then roll
of factor is given by
𝛽 =
∆𝑓
(
1
2𝑇
)
=
∆𝑓
(
𝑅 𝑠
2
)
= 2𝑇∆𝑓
Where 𝑅 𝑠 =
1
𝑇
is the symbol/bit rate of the input signal. The value of 𝛽 varies from 0 to
1. As 𝛽 increases, the ripple level in time domain decreases. The excess bandwidth of the
𝒉( 𝒕) = 𝒔𝒊𝒏𝒄 (
𝒕
𝑻
)
𝒄𝒐𝒔(
𝝅𝜷𝒕
𝑻
)
𝟏 −
𝟒𝜷 𝟐 𝒕 𝟐
𝑻 𝟐
𝑇, | 𝒇| ≤
𝟏 − 𝜷
𝟐𝑻
0, 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
𝑯(𝒇) =
𝟎 ≤ 𝜷 ≤ 𝟏
𝑻
𝟐
[ 𝟏 + 𝒄𝒐𝒔 (
𝝅𝑻
𝜷
[| 𝒇| −
𝟏 − 𝜷
𝟐𝑻
])] ,
𝟏 − 𝜷
𝟐𝑻
< | 𝒇| ≤
𝟏 + 𝜷
𝟐𝑻

29
filter can be reduced, only by the expense of an elongated impulse response. As 𝛽 approaches
zero, the frequency spectrum becomes rectangular function. The variation of frequency
spectrum of the RC filter for different values of 𝛽 is shown in the following Fig. 3.12.
Fig. 3.12 Variation of RC filter frequency spectrum for different values of 𝛽
The bandwidth of the output of the RC filter is given by
For preserving the symbol shape the excess bandwidth is required. If the 𝛽 value
decreases the bandwidth reduces but the ripple level in time domain increases.
3.2.2.2 Designof RaisedCosine Filter
In this project, Raised Cosine (RC) filter is used as low pass filter. In the transmitter
RC filter is used for the symbol shaping. Hence in receiver also RC filter is preferred for the
function of low pass filtering.
𝐵𝑊 =
1
2
𝑅 𝑠( 𝛽 + 1)

30
Using Filter Design & Analysis (FDA) Tool in MATLAB, fixed point filter
coefficients are generated for the given specifications of the RC filter. These fixed point
coefficients are given to the FIR Compiler in Xilinx ISE Simulator as coe file. The FIR
compiler[21] provides a common interface for users to generate highly parameterizable, area
efficient high performance FIR filters utilizing either Multiply Accumulate (MAC) or
Distributed Arithmetic (DA) architectures. It supports up to 256 sets of coefficients, with 2 to
2048 coefficients for each set. But in this project only one set of 100 coefficients are used.
The specifications of the designed RC filter are
Cutoff frequency - 5.25MHz (symmetry)
Clock frequency - 84 MHz
Window - hamming window
Roll of factor - 0.25
Number of taps - 100
The frequency response of the RC filter is shown in the following Fig. 3.13.
Fig. 3.13 Frequency response of the RC filter with symmetric cutoff of 5.25MHz and
having a roll of factor 0.25 with 100 taps

31
The input and output spectrums of the RC filter are shown in the following Figs. 3.14,
3.15 and 3.16. The output of the filter is satisfactory with 50 dBm suppression of higher
frequency components.
Fig. 3.14 Spectrum of input of filter, having multiple OFDM spectrums each with a
bandwidth of 10.5MHz and having level -50dBm
Fig. 3.15 Spectrum of filtered output of OFDM signal with pilots and cyclic prefix,
centered at DC carrier with 10.5MHz bandwidth and having level -21dBm

32
Fig. 3.16 Spectrum of filtered output of OFDM signal without pilots and CP, centered at
DC with 7MHz bandwidth and having level -27dBm
3.2.3 Down Sampler
The down sampler is the one which resample the signal at a lower sampling rate for
the processing of the signal by low data rate devices. In this project, the received signal is
sampled at a high sampling rate of 84 Mbps. But the actual data rate is 10.5 Mbps. That
means 8 consecutive samples have only one bit information. The modules such as cyclic
prefix remover, FFT process the direct data bits only, they cannot operate on up sampled
version of the signal. Hence a down sampler is used to reduce the sampling rate from 84
Mbps to actual data rate of 10.5 Mbps.
In this project the down sampler is implemented using First In First Out (FIFO) IP
Core. FIFO IP core can be operated by using either independent clocks or common clocks
for writing into FIFO and reading out from FIFO. FIFO is fully configurable using Xilinx
Core generator[22]. It supports sample depths up to 4,194,304 words each with widths from
1 to 1024 bits. It gives options selectable memory type such as block RAM, distributed
RAM, shift register or built in FIFO. It provides configurable handshake signals. Full, empty

33
status flags can be programmed or set by user defined constants or dedicated input ports. The
pin diagram of the FIFO is shown in the following Fig. 3.17.
Fig. 3.17 I/O port diagram of FIFO
By using independent clocks, 84 Mbps clock for writing data into FIFO and 10.5
Mbps clock for reading data from FIFO, the down sampler is implemented. The write enable
and read enable signals are controlled such the output is the one sample in middle of the
consecutive 8 samples.
Specifications of the down sampler are
 Write clock - 84Mbps
 Read clock - 10.5Mbps
 Buffer length - 1024 samples
 Read latency – 1 clock cycle
Thus down sampler is implemented using the FIFO core generator. The outputs
generated are at a rate of 10.5 Mbps. The spectrums of input and output are same i.e. the
information in the signal is not changed or the signal is not distorted. That means the down
sampler is implemented successfully.
FIFO
wr_clk
wr_data_count
full
wr_ack
overflow
din
wr_en
rd_clk
rd_en
rd_data_count
dout
empty
valid
underflow

34
3.3 Result
The spectrum of output of the mixer is the multiple spectrums of the input signal. The
output of the mixer is given to the RC filter. It suppresses all other frequency components by
50 dBm other than the spectrum of the signal that is centered at zero frequency. Filtered
signal is fed to down sampler. The output of the filter is at a data rate of 10.5 Mbps and the
spectrums of input and output signal are same. The spectrum of outputs of these modules tells
that the components are designed properly and are working satisfactorily.
The output of the down sampler is the OFDM signal with cyclic prefix. Hence the
cyclic prefix has to be removed and demodulated using FFT. In the next Chapter cyclic prefix
removal and demodulation of OFDM using FFT are studied.

35
Chapter 4
Cyclic Prefix Removal and Demodulation of OFDM using FFT
4.1 Introduction
The cyclic prefix is used to avoid ISI and ICI, so at the receiver it has to be removed.
After removal of cyclic prefix the OFDM signal is demodulated using FFT. In this Chapter
the how the cyclic prefix avoid ISI and ICI, how the cyclic prefix remover is implemented
will be studied. And also will study about why FFT is used for demodulation of OFDM and
how it is designed.
4.2 Concept of Cyclic Prefix
In wireless channel the transmitted signal travels in different directions in multiple
paths. Such wireless channels are called multipath wireless channels. At the receiver the
received signal is the sum of direct signal and the signals that are reflected from different
objects such as buildings, vehicles, trees, mountings and other structures. Due to different
path lengths, the same signal reaches the receiver at different time instants making the
spreading of the symbol in time domain. Delay spread is the arrival time difference between
the direct signal and the last multipath signal.
Due to this symbol spread, each symbol interferes with its adjacent symbols causing
inter symbol interference (ISI). Inter symbol interference causes the loss of information in
starting of the symbols. The phase information of samples in the start of the OFDM is
important because it tells about the carrier frequency offset. For proper demodulation of
OFDM signal, the information in the start of the symbol is required.
To avoid the inter symbol interference, the guard intervals are used. The period of the
guard interval should be greater than the delay spread. In these guard intervals cyclic
extensions are used for frame synchronization at the receiver.

36
The cyclic extensions (either prefix or postfix) are used for the symmetry of symbol
which is useful in finding the start of the symbols. In cyclic prefix a part of the OFDM
symbol from the tail of the OFDM symbol is added in front of the OFDM symbol. In cyclic
postfix a part of the OFDM symbol from the start of the OFDM symbol is added to the end of
the OFDM symbol. Generally cyclic prefix is used, for the detection of the start of the OFDM
symbol.
In order to the cyclic prefix to be effective, the length of the cyclic prefix must be
greater than or at least equal to delay spread. Generally the length of the cyclic prefix is taken
as 1/8th or 1/4th of the OFDM symbol length. Prefixing the end of the symbol to the beginning
makes the linear convolution symbol with the channel as the circular convolution. The cyclic
prefix insertion is shown in the following Fig. 4.1.
4.2.1
Fig. 4.1 OFDM symbols with cyclic prefix insertion
4.2.1 Mathematical model of OFDM signal with cyclic prefix
Let N be the number of subcarriers in the given OFDM system. The data symbol is given by
Inverse Discrete Fourier Transform (IDFT) of the data symbol gives the OFDM
symbol. Let X’(n) is the nth subcarrier of the OFDM symbol and it is given by the following
equation.
𝒅 = [ 𝒅 𝟎, 𝒅 𝟏, 𝒅 𝟐, … . 𝒅 𝑵−𝟏] 𝑻
Cyclic
Prefix
Cyclic
PrefixSymbol S0 Symbol S1
Guard
Interval
Fade
Interval
Symbol Period
CyclicPrefix Insertion

37
The OFDM symbol is given by
After insertion of cyclic prefix, the OFDM symbol is given as follows. Here L is the
length of the cyclic prefix.
Let the length of the channel impulse response is also equal to L, then the impulse
response of the channel is given by
Let y be the OFDM symbol, after convolution with the channel impulse response.
Then the OFDM symbol after convolution is given in following equation, where y(m) shows
the sample of the OFDM symbol.
The linear convolution becomes circular convolution, as x(m-l) = x’(m-l mod N) due
to the insertion of cyclic prefix. Frequency spectrum of OFDM symbol after convolution is
product of actual spectrum of OFDM symbol and the spectrum of channel impulse response.
𝑿′ = [ 𝒙( 𝟎), 𝒙( 𝟏), 𝒙( 𝟐),…. 𝒙( 𝑵 − 𝟏)] 𝑻
𝒉 = [ 𝒉 𝟎, 𝒉 𝟏, 𝒉 𝟐,… . 𝒉 𝑳−𝟏] 𝑻
𝒚( 𝒎) = ∑ 𝒉(𝒍)𝒙(𝒎− 𝒍)
𝑳−𝟏
𝒍=𝟎
; 𝑳 − 𝟏 ≤ 𝒎 ≤ 𝑵 − 𝟏
𝒀( 𝒌) = 𝑿(𝒌)𝑯(𝒌)
𝑿 = [ 𝒙( 𝑵 − 𝑳 + 𝟏), 𝒙( 𝑵 − 𝑳 + 𝟐),… . 𝒙( 𝑵 − 𝟐), 𝒙( 𝑵 − 𝟏), 𝒙( 𝟎), 𝒙( 𝟏), 𝒙( 𝟐),… . 𝒙( 𝑵 − 𝟏)] 𝑻
𝑿′(𝒏) = ∑ 𝒅(𝒏)𝒆
𝒋𝒘𝒏𝒌
𝑵
𝑵−𝟏
𝒌=𝟎
; 𝟎 ≤ 𝒏 ≤ 𝑵 − 𝟏

38
4.2.2 Use of Cyclic Prefix in Finding the Start of the OFDM Symbol
The autocorrelation of the received signal gives peaks at the start of the OFDM
symbol, because of the similarity between the cyclic prefix inserted and the end of the OFDM
symbol. The following Fig. 4.2 shows the autocorrelation of the received OFDM signal
having cyclic prefix. The peaks in the autocorrelation function give the start of the OFDM
symbols.
Fig. 4.2 Autocorrelation of received OFDM signal (peaks show the start of OFDM symbols)
4.2.3 Implementation of Cyclic Prefix Remover
In this project, the length of the total OFDM symbol is 72 in which 64 samples
correspond to actual data and 8 samples correspond to cyclic prefix. The input data to the
cyclic prefix remover is having 72 samples per symbol and the output is having 64 samples
per symbol. So to maintain the frame rate two independent clocks of the clock frequency ratio
72:64 i.e. 9:8 are used for input data writing and output data reading such that both the input
and output of cyclic prefix remover are continuous data streams.
Hence the CP remover is implemented using FIFO, because FIFO supports different
data rates for writing data into it and for reading data from it. The cyclic prefix is
implemented by using FIFO with 10.5 Mbps clock for writing the input data into FIFO and
9.333 Mbps clock for reading output data from FIFO. When the cyclic prefix samples are
presented at the input of the cyclic prefix remover, the write enable of the FIFO is disabled

39
such that those samples are ignored, and when the actual data samples are presented at the
input of the cyclic prefix remover write enable of the FIFO is enabled such that those samples
are write into the FIFO. While read enable is enabled after some samples are stored in the
FIFO and it is continuously enabled such that all the samples stored in FIFO are continuously
read from the FIFO. The following Fig. 4.3 shows the port diagram of FIFO.
Fig. 4.3 I/O port diagram of FIFO
Specifications of the Cyclic Prefix remover are
 Write clock – 10.5Mbps
 Read clock – 9.333Mbps
 Buffer length – 1024 samples
 Read latency – 1 clock cycle
FIFO
wr_clk
wr_data_count
full
wr_ack
overflow
din
wr_en
rd_clk
rd_en
rd_data_count
dout
empty
valid
underflow

40
4.3 FFT
Fast Fourier Transform (FFT) is an algorithm to find the Discrete Fourier Transform
(DFT) with less number of computations. DFT converts time (space) domain into frequency
domain. Let x(n), n=0, 1,…N-1 are N complex numbers then DFT of x is given by x(k),
(where X(k), k=0, 1,…N-1 are N complex DFT coefficients)
The computation of DFT by evaluating definition directly takes O(N2) arithmetical
operations, while FFT can compute the DFT and produces the same result in only O(N log N)
arithmetical operations. FFT is more accurate and much faster than the evolution of DFT
definition directly.
FFT is a divide and conquer algorithm that recursively breaks down a transform of
size N into two pieces of size N/2 at each step, along with O(N) multiplications by the
complex roots of unity traditionally called as twiddle factors (𝑾 𝑵
𝒏𝒌
). The twiddle factor is
given by
4.3.1 Computation of DFT using DIT and DIF Algorithms
FFT computes the DFT inlog2 𝑁 number of stages with small computing structures
called butterflies. It computes DFT in two ways one is Decimation In Time (DIT) and the
other is Decimation In Frequency (DIF). The butterflies for DIT and DIF algorithms are
shown in the following Figs. 4.4(a) and 4.4(b).
𝑾 𝑵
𝒏𝒌
= 𝒆
−𝒋𝒘𝒏𝒌
𝑵
𝑿(𝒌) = ∑ 𝒙(𝒏)𝒆
−𝒋𝒘𝒏𝒌
𝑵
𝑵−𝟏
𝒏=𝟎
; 𝟎 ≤ 𝒌 ≤ 𝑵 − 𝟏

41
Fig. 4.4 Butterfly structures used in (a) DIT algorithm, (b) DIF algorithm
The radix-2 algorithm rearranges the discrete Fourier transform (DFT) equation into
two parts, one is computation of the even-numbered discrete-frequency indices X(2k) and
other is computation of the odd-numbered indices X(2k+1), where k=0, 1,2,…(N/2)-1. This
conversion of the full DFT into a series of shorter DFTs with a simple preprocessing step
gives the FFT.
The following Figs. 4.5 and 4.6 show the DIT and DIF signal flow for computation of
DFT of a complex numbers x(n), n=0,1,2,..N-1 for N=8. The computation consists of
log2(N)= log2(8)= 3 stages. Each stage consists of N/2= 8/2= 4 butterflies, but the number of
groups in each stage changes. The computational complexity of DIF or DIT is (N/2)log2N
complex multiplications and N log2N complex additions. In DIF algorithm the input is in
normal order and the output is in bit reversal order. Where as in DIT algorithm the input is in
bit reversal order and the output is in normal order.
A
B
A
WBW
A+WB
-1 A-WB
(a)
A
B
A+B
-1 A-B
A+B
W(A-B)W
(b)

42
Fig. 4.5 The DIT signal flow for computation of DFT when N=8
Fig. 4.6 The DIF signal flow for computation of DFT when N=8

43
4.3.2 Reasonfor usage of FFT in OFDM Receiverfor Demodulation
The generation of orthogonal carriers using number of local oscillators is not a simple
task. Even if there is a small change in frequency the orthogonality of subcarriers is lost. And
the usage multiple local oscillators and making sure that they stable at the orthogonal
frequencies makes the OFDM system more complex. Fortunately the DFT basis functions are
orthogonality i.e. any two coefficients (twiddle factors) of DFT are orthogonal. This is the
basic property of the DFT that makes it, to use in generation of orthogonal frequency carriers
in OFDM. As DFT is implemented simply by FFT, FFT is used in OFDM system. The
orthogonality of the twiddle factors is shown in the following equation.
In transmitter, the digital data bits are mapped to amplitude and phase values and
placed at correct locations in frequency spectrum. This signal has to be modulated using
number of orthogonal subcarriers and it is in frequency domain. As IFFT converts the
frequency domain signal to time domain signal, IFFT is used to modulate this signal.
At the receiver, the received signal is in time domain so FFT is used to demodulate
the signal. FFT converts the time domain signal into frequency domain signal. After
demodulation the amplitude and phase of the subcarriers are mapped and demodulated to
digital data bits.
4.3.3 Features of FFT IP Core
In this project, FFT block is implemented using the FFT IP Core. FFT IP core[23]
computes N-point forward or inverse DFT where N = 2m, m= 3 to 16. It provides run time
configurable forward and inverse complex FFT. It accepts data and phase factor precision of
8 to 34 bits. The total memory is on chip using either block RAM or distributed RAM. The
input data must be in natural order and the output data can be in either natural or bit reversal
order. It provides three arithmetical options for computation of FFT.
∑ 𝑾 𝑵
𝒏𝒌′
𝑾 𝑵
𝒏𝒌
= 𝑵𝜹 𝑵(𝒌 − 𝒌′
)
𝑵−𝟏
𝒏=𝟎

44
 Full precision unscaled arithmetic
 Scaled fixed point (user has to provide scaling schedule)
 Block floating point (run time adjusted scaling)
Four architecture options are available in FFT IP core. They are
i. Pipelined, Streaming I/O Architecture
ii. Radix-4, Burst I/O Architecture
iii. Radix-2, Burst I/O Architecture
iv. Radix-2 Lite, Burst I/O Architecture
Pipelined streaming I/O architecture allows continuous data processing, where as
remaining all for burst mode operation. Pipelined and streaming I/O architecture loads and
processes data simultaneously, where as remaining all loads and processes data separately.
The transform time of pipelined streaming I/O architecture is less than all the remaining
architectures.
4.3.4 Pipelined, Streaming I/O Architecture of FFT IP Core
In this project the FFT IP core is operated in pipelined streaming I/O architecture
because the input is continuous data stream. The pipelined streaming I/O pipelines several
Radix-2 butterfly processing engines for continuous data processing. Each butterfly
processing engine has its own memory banks to store the input and intermediate data. The
core has the ability to simultaneously perform transform calculation on the current frame of
data, load input data for the next frame of data, and upload the results of the previous frame
of the data. The user can continuously stream in data and, after the calculation latency, can
continuously upload the results.
In the scaled fixed-point mode, the data is scaled after every pair of Radix-2 stages.
The input data should be in natural order, the output data can either be in bit reversed order or
in natural order. If natural order output data is selected then additional memory resources
either block RAM or distributed RAM are utilized. The block diagram of pipelined streaming
I/O architecture is shown in the following Fig. 4.7.

45
Fig. 4.7 Pipelined, Streaming I/O Architecture of FFT IP core
4.3.5 Port Definitions of FFT IP Core
Following Fig. 4.8 shows the schematic structure of the FFT IP Core.
Fig. 4.8 FFT IP Core schematic symbol in pipelined, streaming I/O architecture
xn_im
start
fwd_inv_we
xn_re
FFT
xk_re
xk_im
xn_index
xk_index
clk
scale_sch_we
rfs
fwd_inv
rfd
dv
done
edone
busy
cpv
scale_sch
cp_len
cp_len_we
Memory
Radix-2
Butterfly
Memory
Radix-2
Butterfly
Stage (logN) -2
Group (logN)/2
Output
Shuffling
OutputData
Stage (logN)-1
Memory
Radix-2
Butterfly
Memory
Radix-2
Butterfly
Stage 0 Stage 1
Group 0
Memory
Radix-2
Butterfly
Memory
Radix-2
Butterfly
Stage 2 Stage 3
Group 1
InputData

46
Following Table. 4.1 shows the core pinout for the single channel FFT IP Core in
pipelined, streaming I/O architecture.
port name Port Width Direction Description
xn_re bxn Input Input data bus: Real component
xn_im bxn Input Input data bus: Imaginary component
start 1 Input FFT start signal (active high): Start is asserted
to begin the data loading and transform
calculation
fwd_inv 1 Input Control signal, If FWD_INV=1 then forward
transform is computed. If FWD_INV=0 then
reverse transform is computed.
fwd_inv_we 1 Input Right enable for FWD_INV. It is active high.
scale_sch
2 x ceil(
𝑁
2
)
for pipelined
streaming
I/O
Input For pipelined streaming I/O a scaling schedule
is specified with two bits for every pair of
Radix-2 stages, starting at the two LSBs. This
is available only with scaled arithmetic.
scale_sch_we 1 Input Write enable for scale_sch (active high): This
is available only with scaled arithmetic.
cp_len
log2 𝑁
Input Cyclic prefix length: It specifies the number of
samples from the end of the transform that are
appended in front of the transform. It available
only with cyclic prefix insertion.
cp_len_we 1 Input Write enable for cp_len (active high): It
available only with cyclic prefix insertion.
ce 1 Input Clock enable(active high): Optional port
clk 1 Input Rising-edge clock
xk_re bxk Output Output data bus: real component in two’s
complement or floating point format.

47
xk_im bxk Output Output data bus: imaginary component in
two’s complement or floating point format.
xn_index Log2
N Output Index of input data
xk_index Log2
N Output Index of output data
rfd 1 Output Ready for data (active high): during the data
load operation it is high.
busy 1 Output Core activity indicator (active high). When
core is computing the transform, it goes high.
dv 1 Output Data valid (active high). When the output data
is valid, this signal goes high.
edone 1 Output Early done strobe (active high). It goes high
for one clock cycle prior to done going high.
done 1 Output FFT complete strobe (active high). When the
transform calculation completed it goes high
for one clock cycle.
ovflo 1 Output Arithmetic overflow indicator (active high).
While any value in the data frame during
result unloading overflowed then it goes high.
cpv 1 Output Cyclic prefix valid (active high). This signal is
high when valid cyclic prefix data is presented
at the output.
rfs 1 Output Ready for start (active high). This signal goes
high when core is ready to accept an assertion
on the start signal to begin data loading.
Table. 4.1 Ports/pins of the FFT IP core in pipelined, streaming I/O architecture

48
4.3.6 Implementation of FFT using FFT IP Core
The 64 point FFT is implemented using FFT IP Core in Pipelined, Streaming I/O
Architecture where it accepts continuous data stream. The output of the cyclic prefix remover
is the continuous OFDM signal of 64 subcarriers coming with a rate of 9.333 Mbps. This
signal is taken as the input to the designed 64 point FFT module. So the signal is
demodulated by FFT using FFT IP core with the following specifications.
Clock – 9.333 Mbps,
Transform length – 64,
Cycles required of computation of transform – 275 clock cycles,
Latency – 1.1 us.
The following Figs. 4.8 and 4.9 show the spectrums of input and output signals of the
64 point FFT module. Input is the OFDM signal of 64 subcarriers coming with a rate of 9.333
Mbps, having level of -50 dBm and the output is the demodulated data with pilots with the
data rate of 9.333Mbps and having a level of -27 dBm.
Fig. 4.9 Spectrum OFDM signal with pilots, centered at DC with 9.333MHz bandwidth and
having level -50dBm

49
Fig. 4.10 Spectrum of demodulated data with pilots having number of frequency
components at 7 MHz, 9.33 MHz and their harmonics
4.4 Result
The performance of cyclic prefix remover which is implemented using FIFO is tested
using the 64 point FFT block with cyclic prefix insertion and the 64 point FFT block without
cyclic prefix insertion. The input data to the cyclic prefix remover is having 72 samples per
symbol and the output is having 64 samples per symbol. So to maintain the frame rate two
independent clocks of the clock frequency ratio 72:64 i.e. 9:8 are used for input data writing
and output data reading. Hence both the input and output of cyclic prefix remover are
continuous data streams. The same test data sequence is applied as input to both the 64 point
FFT block with cyclic prefix insertion and the 64 point FFT block without cyclic prefix
insertion, and the output of the 64 point FFT block with cyclic prefix insertion is fed to cyclic
prefix remover and the output of the cyclic prefix remover is compared with the output of 64
point FFT block without cyclic prefix insertion. Here the 64 point FFT with cyclic prefix
insertion inserts the 8 samples of the tail of the symbol in front of the symbol. The cyclic
prefix remover removes these 8 samples of the cyclic prefix. It is observed that the output of
cyclic prefix remover is in excellent agreement with the output of the 64 point FFT block

50
without cyclic prefix insertion. That means the designed cyclic prefix remover is work ing
properly. The following Fig. 4.11 shows the BER performance of the designed cyclic prefix
remover.
Fig. 4.11 VHDL simulation result of testing of cyclic prefix remover and is giving zero BER
The working of 64 point FFT block is tested using 64 point IFFT block. The output of
the 64 point IFFT block is fed as input to 64 point FFT block. The designed FFT block
accepts the serial data input and it gives the serial data output i.e. the designed 64 point FFT
block includes both 64 bit serial to parallel converter and 64 bit parallel to serial converter.
The 64 point IFFT block which is used for testing the 64 point FFT block is also includes
both 64 bit serial to parallel converter and 64 bit parallel to serial converter. The random data
at different data rates is given as test sequence to the input of the IFFT block. The output of
the FFT block is compared with the delayed version of the input of the IFFT block. In all
cases the zero BER is observed i.e. the output of the FFT block is excellently matched with
the input of the IFFT block. So it is proved that the designed FFT block is functioning well.
The fallowing Fig. 4.12 shows the BER performance of the designed FFT block.

51
Fig. 4.12 VHDL Simulation result of testing of 64 point designed FFT block with 64 point
IFFT block and is giving zero BER
After demodulation of OFDM signal, the demodulated signal is in frequency domain
and it is having pilots. These pilots have to be extracted for the channel estimation and the
user data bits have to be mapped to digital data bits. So in the next Chapter pilot extraction
and symbol demapping will be studied.

52
Chapter 5
Pilot Extractor and QPSK Symbol Demapper
5.1 Introduction
Pilots are those which are transmitted along the actual signal for supervision,
equalization, and reference purposes. In OFDM system the pilots are used for channel
estimation. In this Chapter, the channel estimation using the pilots, design of pilot extractor,
concept of QPSK and symbol demapping, implementation of symbol demapper using QPSK
demodulator will be discussed.
5.2 Channel Estimation
In any communication system the received signal is not same as the transmitted
signal. The transmitted signal undergoes channel effects while it is passing through the
channel. So the received signal is modeled as the convolution of transmitted signal and
channel impulse response by considering the channel as a filter. Hence the channel
characteristics (channel impulse response) have to be estimated to reconstruct the original
transmitted signal.
Coming to wireless channel, it is a multipath fading channel. A multipath channel is
the one in which the transmitted signal is travelled in different direction in multiple paths. At
the receiver the received signal is the sum of the signals coming from different directions as
the reflection from the different objects such as buildings, mountings, trees, etc.
If a signal passing through a channel undergoes fading effect then that channel is
called fading channel. Fading is variation of signal strength depending on frequency, time
etc. Frequency selective fading occurs, if coherence bandwidth of the channel is less than the
bandwidth of the signal. In frequency selective fading some of the frequency components of
the signal are suppressed. Flat fading occurs, if the coherence bandwidth of the channel is
greater than the bandwidth of the signal. In flat fading the all frequency components signal
undergo same attenuation.

53
The advantage of OFDM is that the frequency selective fading becomes flat fading for
the subcarriers, as the total bandwidth of the signal is divided into number of sub bands. So
channel estimation becomes simpler than any other single carrier modulation techniques.
5.2.1 Different Techniques for Channel Estimation
For coherent detection of information symbols, the channel state information has to be
found accurately and promptly. There are number of techniques for channel estimation.
Broadly they are divided into three groups. They are
i. Non data aided channel estimation
ii. Data aided channel estimation
iii. Semi data aided channel estimation
i. Non Data Aided Channel Estimation
In non data aided channel estimation, no additional data is transmitted along the user
data for the channel estimation. The channel state information is estimated using some of
transmitted signal properties and statistical information of channel. It requires the long data
records for estimation channel characteristics. It is applicable only to slow fading channels. It
is not applicable to fast fading channels. It is also known as blind channel estimation. The
advantage of this technique is, there is no overhead loss but the estimation is poor.
ii. Data Aided Channel Estimation
It is also known as training/pilot based channel estimation. In this technique, training
symbols or pilot bits that are known prior to the receiver are multiplexed with the user data
bits for the channel estimation[18]. This is the better technique for the channel estimation
because it requires no long data records for the channel estimation. It can be applicable to the
fast time varying channels also. It is complex to implement, but the estimation is reliable.

54
iii. Semi Data Aided Channel Estimation
It is the combination of the both non data aided and data aided channel estimation
techniques. It is also known as semi blind channel estimation technique. In this technique, the
channel characteristics are estimated using training symbols/ pilot bits, some of the
transmitted signal characteristics/properties and statistical information of channel.
5.2.2 Pilot based Channel Estimation
Depending on the channel characteristics such as fast fading, slow fading the
arrangement of pilots is changed. The fast fading channel is the one for which the
characteristics are changing within the duration of one symbol. The slow fading channel is
the one for which the characteristics are constant over the period a few symbols.
a. Fast Fading Channel
In fast fading channel the channel characteristics are varying very fast (within the
period of the OFDM symbol), so the channel characteristics have to be estimated for every
OFDM symbol. So in every OFDM symbol the pilots must be inserted. Generally even
subcarriers are used for insertion of pilots. For getting the channel characteristics at the non-
pilot subcarriers (data subcarriers/ null subcarriers), the extracted pilot bits are interpolated.
The pilot structure is look like a comb, so the pilot structure is called as comb pilot structure.
The comb pilot structure is in the following Fig. 5.1.
Fig. 5.1 Comb pilot structure
time
frequency

55
b. Slow Fading Channel
As the channel characteristics do not change over a few OFDM symbols. It is
sufficient to estimate the channel characteristics once for a few symbols. So an OFDM
symbol with full of pilots is transmitted for every a few OFDM symbols. The pattern of the
pilots is like a block so the pilot structure is also called as block pilot structure and is shown
in the following Fig. 5.2.
Fig.5.2 Block pilot structure
5.2.3 Mathematical Model of Channel Estimation
The data symbol of X(k) with pilots and nulls is given for IFFT for modulation. The
IFFT converts this frequency domain signal to time domain signal x(n). The output of the
OFDM transmitter is given by
time
frequency
𝒙( 𝒏) = 𝑰𝑫𝑭𝑻(𝑿( 𝒌))
𝒙( 𝒏) = ∑ 𝑿( 𝒌) 𝒆
𝒋𝒘𝒏𝒌
𝑵
𝑵−𝟏
𝒏=𝟎
𝟎 ≤ 𝒏 ≤ 𝑵 − 𝟏

56
To avoid ISI and ICI, cyclic prefix is inserted. The cyclic prefix is given by the
following equation.
The cyclic prefix insertion makes the linear convolution of transmitted signal with the
channel impulse response as circular convolution. Thus making the received signal is the
circular convolution of transmitted signal and channel impulse response in addition with
Additive White Gaussian Noise (AWGN).
Where Y(k), X(k), H(k), W(k) are the frequency responses of received signal y(n),
transmitted signal x(n), channel impulse response h(n), Additive White Gaussian Noise w(n)
respectively. As the transmitted signal is having the cyclic prefix symmetry, the received
signal is also have the cyclic prefix symmetry.
As the pilots are known prior to the receiver and the channel characteristics can be
estimated using the following equation.
If the AGWN is negligible then the channel characteristics are
The estimated channel characteristics are given to the channel equalizer for removal
of channel effect on the data. After channel equalization the data is given to signal demapper
to get the binary data.
𝒙 𝒈( 𝒏) = 𝒙(𝒏 𝒈 + 𝒏) ; 𝒏 𝒈 = −𝑵 𝒈, −𝑵 𝒈 + 𝟏, … − 𝟏 𝒂𝒏𝒅 𝒏 = 𝟎, 𝟏, 𝟐,… 𝑵 − 𝟏
𝒀( 𝒌) = 𝑿( 𝒌) 𝑯( 𝒌)+ 𝑾(𝒌)
𝒚 𝒈( 𝒏) = 𝒚(𝒏 𝒈 + 𝒏) ; 𝒏 𝒈 = −𝑵 𝒈,−𝑵 𝒈 + 𝟏, …− 𝟏 𝒂𝒏𝒅 𝒏 = 𝟎, 𝟏, 𝟐,… 𝑵 − 𝟏
𝑯( 𝒌) =
𝒀( 𝒌)− 𝑾(𝒌)
𝑿(𝒌)
𝑯( 𝒌) =
𝒀( 𝒌)
𝑿(𝒌)

57
5.3 Implementation of Pilot Extractor using FIFO
In this project the pilot are inserted at the subcarriers numbered 7, 14, 21, 28, 35, 42,
49, and 56. And the subcarriers numbered 0, 1, 2, 3, 60, 61, 62, and 63 are used as nulls. That
means no data is transmitted on these sub carriers because these subcarriers are near to the
DC carrier and the data transmitted on the DC carrier near subcarriers cannot be
reconstructed. While passing the data through the practical low pass filter, the data on the DC
subcarrier and near subcarriers will be distorted and hence no data is transmitted using these
subcarriers. The pilot inserter transfers the user data bits when the subcarriers other than
mentioned above come and it inserts the pilot bits when pilot subcarriers come and transfer
zeros when null subcarriers come. The designed pilot extractor reads the data when the user
data subcarriers are present at its input and it transfer the user data to data output and reads
the data of pilot subcarriers and transfers the data to pilot data output and when null
subcarriers come, it ignores the data and returns nothing. The input of the pilot extractor is
having 64 samples per symbol and the output of the pilot extractor is having only 48 samples
per symbol. So to maintain the frame rate the input and output clocks are taken in the clock
frequency ratio as 64:48 i.e. 4:3 for input data writing and output data reading.
Hence the pilot extractor is implemented using FIFO because the FIFO supports
different data rates for input data and output data. The input clock used is 9.333 Mbps clock
for writing data into FIFO and output clock used is 7 Mbps clock for reading data from the
FIFO. When the user data bits are presented at the input of the pilot extractor the write enable
of the FIFO is enabled such that it writes the user data bits into it and when the pilot bits and
nulls are presented at the input of the pilot extractor, the write enable of the FIFO is disabled
such that those bits are ignored. After some samples are stored in the FIFO, the read enable is
enabled continuously such that the output of pilot extractor is continuous user data stream.
Specifications of pilot extractor:
Write clock – 9.333 Mbps
Read clock – 7 Mbps
Buffer length – 1024 samples
Read latency – 1 clock cycle

58
Fig.5.3 Spectrum of output data with pilots having frequency components at 7 MHz and
9.333 MHz and their harmonics
Fig. 5.4 Spectrum of output data, after removal of pilots, having frequency components at 7
MHz and its harmonics

59
The above Figs. 5.3 and 5.4 show the spectrums of the signal with pilots and the
signal after removal of pilots. Before removal of pilots the signal is having pilots so the
spectrum has frequency components at both 7MHz and 9.333 MHz and at their harmonics.
After removal of pilots and nulls the spectrum of the signal has frequency components only at
7 MHz and at its harmonics. Thus the pilot extractor is implemented successfully.
5.4 Concept of Symbol Mapping
In OFDM system, at the transmitter the digital data bits are mapped to the amplitude
and phase values and placed at correct locations in frequency spectrum. To represent the
amplitude and phase of the symbol, complex signals are used. A complex signal consists of
Inphase component (I) and Quadrature component (Q). Hence a Symbol mapper is used to
map the digital data bits to corresponding I and Q values.
At the receiver, after demodulation Inphase and Quadrature signals are obtained.
Hence a symbol demapper is used to convert the Inphase and Quadrature signals to
correspond digital data bits. Depending on the symbol mapper selected at the transmitter,
corresponding symbol demapper is selected at the receiver.
Generally for symbol mapping digital modulators such as BPSK, QPSK, M-PSK,
QAM, and M-QAM are used. For symbol demapping the corresponding digital demodulators
are used.
5.4.1 Different Symbol Mapping Techniques and their Spectral Efficiencies
In MPSK digital modulation technique log2 𝑀 bits are used to encode one complex
symbol. Thus the symbol rate of M-PSK is reduced by a factor of log2 𝑀. If the baud rate is
reduced by log2 𝑀 factor, then the bandwidth required to transmit the signal is also reduced
by the same factor. Fallowing Table. 5.1 gives the spectrum efficiency of different digital
modulation schemes.

60
Type of digital
modulation technique
Spectral efficiency
(bits/Hz)
BPSK 1
QPSK 2
8PSK 3
16QAM 4
64QAM 6
Table. 5.1 Spectral efficiency (bits/Hz) of different digital modulation techniques
5.4.2 Selection of Proper Symbol Mapping Technique for Given OFDM System
In OFDM system one or more symbol mapping techniques can be used. In some
OFDM systems depending on the parameters dynamically the symbol mapping technique is
selected. If the size of the constellation symbol mapper increases then the spectrum efficiency
increases but the bit error rate (BER) also increases. So there is a controversy in the selection
of size of constellation. So the selection of symbol mapping technique is done based on the
following parameters.
i. Distance between the transmitter and the receiver
ii. Characteristics of the channel
iii. Bit Error Rate (BER) specifications
In dynamic selection of digital modulation technique, if the BER obtained is very less
than the specified BER for a given SNR, then the constellation size (i.e. the value of M in M-
PSK, M-QAM) is increased. If the BER obtained is greater than the specified BER for a
given SNR, then the constellation size is reduced.
5.5 Concept of QPSK
In this project, (Quadrature Phase Shift Keying) QPSK is used for the symbol
mapping. QPSK is one of the digital modulation techniques, in which two binary digits are
mapped to one complex symbol. In QPSK the symbol rate reduced to half of input data rate.

61
There are two types of QPSK mappings, one is binary mapping and other is gray code
mapping. The following figures show the two QPSK mapping constellations.
Fig. 5.5 Binary QPSK constellation Fig. 5.6 Gray code QPSK constellation
5.5.1 QPSK Modulator
The QPSK signal is generated by taking two bits at a time and multiplying one bit
with cosine wave, other bit with sine wave and adding both waves gives the QPSK signal.
The block diagram of QPSK modulator is shown in the following figure.
Fig. 5.7 Block diagram of QPSK modulator
0001
10 11
450
I
Q
0001
1011
450
Q
I
Carrier
Generator
900
cos(2πfct)
sin(2πfct)
I channel
Q channel
bit stream
2-bit shift
register
QPSK
signal

62
Fig. 5.8 In phase component, Quadrature component and QPSK signal outputs
The above figure shows the In phase component, Quadrature component and QPSK
signal of a QPSK modulator. This is generated using MATLAB 7.10.
5.5.2 QPSK Demodulator
Coming to QPSK demodulation, the input signal is multiplied with the same carriers
which are used to at the transmitter for QPSK modulation. After multiplication Inphase
component and Quadrature component are obtained. The energy of the symbol is compared
with a threshold value. If the energy of symbol is greater than the threshold value then the bit
is taken as 1 otherwise it is taken as 0. Then I channel bits and Q channel bits are multiplexed
to get the reconstructed data stream. The following Fig. 5.9 shows the block diagram of
QPSK demodulator.
If there is carrier frequency offset, then the constellation of QPSK rotates. One
symbol is detected as the other and the bit error rate increases. To eliminate this problem the
phase locked loops are used in QPSK receiver for locking the carrier frequency and phase.

63
Fig. 5.9 Block diagram of QPSK demodulator
5.6 Implementation of QPSK Demapper
In this project, QPSK demodulator is used as the symbol demapper. The QPSK
demapper is implemented using VHDL code and Cordic IP Core. Cordic IP core is the one
which gives the phase of a complex signal. Depending on the phase of the signal the binary
data bits are assigned. The following Fig. 5.10 shows the I/O port diagram of Cordic.
Fig. 5.10 I/O port diagram of Cordic
CORDIC
X_IN
Y_IN
Phase_Out
ND
CE
CLK
RDY
RFD
QPSK
signal
cos(2πfct)
sin(2πfct)
I channel
Q channel
Output
bit stream
∫
𝑻
𝟎
Threshold
Carrier
Generator
900
∫
𝑻
𝟎
MUX
Comparator
Comparator

64
Port Name Direction Description
X_IN Input X component of input sample
Y_IN Input Y component of input sample
ND Input New sample on input ports (Active high)
CE Input Clock enable (Active high)
CLK Input Rising edge Clock
PHASE_OUT Output Phase component of the output sample.
RFD Output Ready for new data sample (Active high)
RDY Output New output data is ready (Active high)
Table. 5.2 I/O port description of Cordic
The above Table. 5.2 describes the I/O ports of the Cordic. Cordic[24] accepts the real
and imaginary components of a complex signal and it gives the phase of the complex signal.
Knowing phase angle of a complex signal (symbol) is nothing but knowing about the
quadrant (Cartesian quadrant) in which the symbol falls. If the quadrant of the symbol is
known then the corresponding digital data bits are assigned using VHDL coding[15]. Thus
QPSK demapper is implemented successfully using Cordic IP core.
5.7 Result
The functioning of pilot extractor is tested using the pilot inserter. The output of the
pilot inserter is fed as the input to pilot extractor. In this project the pilot are inserted at the
subcarriers numbered 7, 14, 21, 28, 35, 42, 49, and 56. And the subcarriers numbered 0, 1, 2,
3, 60, 61, 62, and 63 are used as nulls. That means no data is transmitted on these sub
carriers. The pilot inserter transfers the user data bits when the subcarriers other than
mentioned above come and it inserts the pilot bits when pilot subcarriers comes and transfer
zeros when null subcarriers come. The designed pilot extractor reads the data when the user
data subcarriers are present and it transfer the data to data output and reads the data of pilot
subcarriers and transfers the data to pilot data output and when null subcarriers come it

65
ignores the data and returns nothing. The input of the pilot extractor is having 64 samples per
symbol and the output of the pilot extractor is having only 48 samples per symbol. So to
maintain the frame rate the input and output clocks are taken in the clock frequency ratio as
64:48 i.e. 4:3 for input data writing and output data reading. The output of the pilot inserter is
given as input to the pilot extractor and different test sequences are given as the input to the
pilot inserter. The output of the pilot extractor and delayed version of the input of the pilot
inserter are compared and zero BER is observed. Hence it tells that the performance of the
pilot extractor is good. The fallowing Fig. 5.11 shows the BER testing of designed pilot
extractor.
Fig. 5.11 VHDL simulation output of testing of pilot extractor with pilot inserter giving zero
BER
The behavior of symbol demapper which is implemented using QPSK demapper is
tested with the symbol mapper which is implemented with QPSK modulator. The output data
rate of QPSK symbol demapper is double the data rate of input of it. So two clocks in the
ratio 1:2 are used for input and output clocks of QPSK symbol demapper. The output of the
QPSK symbol mapper is given as input to the QPSK symbol demapper. Different binary test
sequences are given as the input to the symbol mapper and output of the symbol demapper is

66
observed. It is same as the input test sequence. So the working of the designed QPSK symbol
demapper is satisfactory. The fallowing Fig. 8.6 shows the BER performance of the QPSK
symbol demapper.
Fig. 8.6 VHDL simulation result of testing of designed QPSK symbol demapper with QPSK
symbol mapper and is giving zero BER
As all the individual modules are designed and implemented successfully, they have
to be integrated. In the following Chapter, the integration and hardware implementation of
the OFDM based baseband receiver will be discussed.

67
Chapter 6
System Integration and Hardware Implementation of
OFDM Based Baseband Receiver
6.1 Introduction
As the OFDM based baseband receiver modules are designed and tested, they have be
integrated. In this Chapter how these modules are integrated, what are the tools used to
implement this on Xilinx Spartan 3 FPGA, how it is implemented and what are the problems
occurred in hardware implementation and how they are eliminated will study in this Chapter.
6.2 Integration of OFDM BasedBaseband ReceiverModules
All the designed modules are integrated to make OFDM based baseband receiver
modules. Even a single bit of the received signal is missed due to any delay in any module
the bit error rate increases. So these modules are integrated by proper control and
handshaking signals.
As the received signal is up converted OFDM signal, the first module in the receiver
should be down converter. The received signal is mixed with a locally generated carrier using
mixer. This output is fed to low pass filter and the filter starts allowing the input data when
there is a high value (bit 1) on the new data (nd) input of the filter. So this nd input is
connected to ready (Rdy) output. So when the output of the mixer is valid the Rdy output is
high, filter starts taking data for processing. When the processing completes and output data
is ready then filter highs the Rdy output of it. The Rdy out is connected to write enable
(wr_en) of the down sampler. When write enable is high then down sampler takes the output
of the filter and resample with a lower sampling rate. The clocks for mixer, filter, and write
clock of down sampler should be same. Depending on the ratio of input data rate and output
data rate the read clock for down sampler is selected.
After down conversion the cyclic prefix has to be removed. So the output of down
sampler is given to cyclic prefix remover. For removing of the cyclic prefix the start and stop
of the OFDM symbol should be known. So when the output data of down sampler is valid the

68
cyclic prefix remover is enabled. The write clock of cyclic prefix remover is same as that of
down sampler read clock. The read clock of cyclic prefix remover is selected such that the
ratio of the clocks of input and output, and the ratio of data rates of the signals with cyclic
prefix and without cyclic prefix are same.
The output of the cyclic prefix remover is given to FFT for demodulation. The FFT
starts loading the input data when rfd is high. rfd becomes after one clock cycle than the start
is high. The output comes after one clock cycle of read enable (rd_en) is enabled. So the
rd_en of the cyclic prefix remover is given to start of the FFT. Start is enabled on that clock
cycle and rfd becomes high in next clock cycle taking the valid data output from cyclic prefix
remover without missing any data samples. When the output of the FFT is valid then the FFT
block generates a data valid (dv) signal. The output of FFT consists of pilot along the user
data bits. So these pilots are removed using pilot extractor. The data valid (dv) of FFT is
given to write enable (wr_en) of pilot remover. The pilot remover allows the data when
wr_en is high. The clocks for reading of output data (read clock) of cyclic prefix remover,
FFT, write clock of pilot remover are same. The read clock of pilot remover is selected such
that the ratio of the clocks of input and output, and the ratio of data rates of the signals with
pilots and without pilots are same.
After removal of pilots, the complex signal data (I and Q) should be mapped to digital
data bits. For this, first the phase of the signal is found using the Cordic. After getting the
phase value depending on the phase value digital data bits are assigned. When the output of
pilot extractor is valid then the Cordic takes the complex signal and gives the corresponding
phase. The phase value is given to symbol demapper for mapping digital data bits. The clocks
for read clock of pilot remover, Cordic, input of the symbol demapper should be same. The
output clock of the symbol demapper should be double the input clock of it, because symbol
demapper used is a QPSK demodulator.
Thus all the blocks are integrated to make OFDM based baseband Receiver. The
block diagram of designed OFDM based baseband Receiver is shown in the following Fig.
6.1. It shows the control signals and data flow of the designed receiver.

69
Fig. 6.1 Block diagram of designed OFDM based baseband Receiver showing control
signals and dataflow
6.3 Testing of OFDM BasedBaseband Receiver
The performance of the system as a whole is evaluated with the OFDM based
baseband transmitter designed in the lab. The digital output of the OFDM based baseband
transmitter is taken as the input to the designed OFDM based baseband receiver. Random
binary test sequence of 14 Mbps is given as input to the OFDM based baseband transmitter
and output of the receiver and the delayed version of the input of the transmitter are
compared, and the zero BER is observed i.e. the output data of the receiver is same as the
input of the transmitter. So the designed OFDM based baseband receiver is working
satisfactorily. The VHDL simulation output of the testing of OFDM based baseband receiver
is shown in the following Fig. 6.2.
Mixer
(Multiplier)
Datain-1
Datain-2 Dataout
Rdy
Carrier
generator
Transmitter
output data
Down Sampler
(FIFO)
Wr_en valid
Datain Dataout
Cyclic Prefix Remover
(FIFO)
wr_en rd_en
Datain Dataout
LPF (RC Filter)
(FIR Compiler)
Rdynd
Datain Dataout
Output
Digital data
Pilot Extractor
(FIFO)
valid wr_en
Dataout Datain
FFT
(FFT IP Core)
startdv
DatainDataoutPhase out
Cordic
Datain
Rdy ce
Symbol
Demapper
Phase inDataout
enableDatavalid

70
Fig. 6.2 VHDL simulation output of testing of OFDM based baseband receiver with OFDM
based baseband transmitter giving zero BER
6.4 Hardware Implementation of OFDM BasedBaseband Receiver
After successful design and integration of OFDM based baseband Receiver modules,
it has to be implemented on Spartan-3 (XC3S5000) FPGA. After successful simulation of the
design, the design is synthesized and programming file is generated using Xilinx ISE Design
Suite 13.2. The FPGA board is connected to the computer having the software ChipScope Pro
Tool using the Xilinx Platform Cable USB II and JTAG. The generated programming file is
dumped on to the FPGA using ChipScope Pro Tool.
6.4.1 Spartan-3 FPGA
The Spartan -3 family FPGAs[25] enhanced with more logic resources, more number
of I/O ports, increased internal RAM, improved clock management functions. These Spartan-
3 FPGAs have advanced process technology and deliver more functionality, and setting new
standards in programmable logic industry.

71
As they are exceptionally low cost Spartan-3 FPGAs are ideally suited for a wide
range of applications including consumer electronics, broadband access, networking, and
digital television equipment.
6.4.2 Features of Spartan-3 FPGA
Spartan-3 FPGAs are Low-cost, give high performance logic solution for high
volume, and can be used for consumer oriented applications. They have high density up
to 74880 logic cells with shift register capability. They have up to 633 I/O pins and
support data rate of more than 622 Mbps per I/O.
6.4.3 ChipScope Pro Tool
The ChipScope Pro tool is used for on chip debugging of an FPGA implementation.
The generated bit files can be dumped into the FPGA using ChipScope Pro tool. Using the
CDC file, the required signals can be observed in ChipScope Pro.
ChipScope Pro tool allows embedding the following core within the design which
assists with on-chip debugging: Integrated Logic Analyzer (ILA), Integrated Bus Analyzer
(IBA), and Virtual Input Output (VIO) low profile software cores. These cores allow
viewing internal signals and nodes in the FPGA.
6.4.4 The Problems Occurred in the Hardware Implementation and their Solutions
While implementing the integrated OFDM baseband receiver, the following problems
are occurred. These problems are eliminated by using the following solutions.
a. The design is too large for given device
Problem Definition: If the required resources for implementing the design are greater than
the available resources in the given FPGA then this problem occurs. There are different
situations where this problem occurs and corresponding solutions are given below.

72
Solutions:
i. There is limited number of multipliers in FPGA. If more modules are designed to use
these limited multipliers there may occur scarcity of multipliers causing the above
problem. While implementing the design if this problem occurs then it has to be checked
whether more modules are designed to use multipliers. If the modules, which can be
implemented using combinational logic blocks (CLB) or look up tables (LUT), are
designed to use multipliers, then their design has to be changed to use CLBs and LUTs.
ii. Generally one trigger clock is used for FPGA implementation. Remaining clocks which
are required in design are derived from that trigger clock. So this trigger clock is applied
to FPGA using clock buffer. Spartan-3 FPGA has only 8 clock buffers. Only one clock
buffer is sufficient for clocking the PFGA and it has to be programmed in the design. The
remaining will be used by the FPGA automatically. If more than one clock buffer is used
then there may be a problem of insufficient clock buffers. To avoid this problem the clock
buffers used externally have to be reduced.
b. Timing constraints
Problem Definition: Timing constraints occurs due to combinational path delay is greater
than the period of the clock signal. Timing constraints are two types one is set up time
violation and other is hold time violation. Set up time is the minimum time that the data has
to be presented on the data port before the occurrence of clock trigger. Due to combinational
path delay if the data is not presented on the data port before the clock occurrence then set up
time violation occurs. Hold time is the minimum time that the data has to be presented after
the occurrence of clock trigger. If the data is not presented on input port for the minimum
time after occurrence of clock trigger then hold time violation occurs. These timing violations
occur due to maximum combinational path delays.
Solution:
To eliminate these timing violations there are two solutions.
i. The clock period has to be increased greater than the maximum combinational path
delay (i.e. clock frequency has to be reduced). But this solution is not preferable
solution.

73
ii. The combinational path length has to be reduced such that the combinational path
delay is less than the clock period. The combinational path length can be reduced by
inserting sequential elements such as flip-flops, buffers in the combinational path.
After removal all problems occurred in hardware implementation and successful
implementation of the design on Spartan-3 FPGA. The Digital to Analog Converter
(DAC5682Z) is configured to the FPGA and the output of the DAC is given to spectrum
analyzer HP8593E. The spectrums of the signals at different stages are observed.
6.4.5 DAC5682Z
. DAC5682Z[26] is a dual channel 16 – bit, 1.0 GSPS digital to analog converter with
wideband data input, integrated 2x/4x interpolation filters, on-board clock multiplier and
internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk and PLL
phase noise performance.
6.4.6 Hardware Setup for Testing of OFDM BasedBaseband Receiver
The above Fig. 6.3 shows the hardware setup for testing the OFDM based baseband
Receiver for wireless radio. The computer, which has ChipScope Pro tool, is connected to the
FPGA board using the Xilinx Platform Cable USB II and JTAG. The FPGA board is
configured using ChipScope Pro tool. The regulated DC power supply is used for powering
the FPGA board. The board requires voltage of 5V and current of 0.5-0.8A. The output of the
DAC is connected to spectrum analyzer through SMA connector. The spectrums of signals at
different stages are observed. Thus the OFDM based baseband Receiver for wireless radio
application is implemented successfully.

OFDM based baseband Receiver

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