Praveen Kumar has over 2.5 years of experience as a semiconductor test engineer specializing in post silicon validation, characterization, and automated test equipment environments. He has expertise in digital and analog circuit design and developing test programs to validate microcontrollers and power management integrated circuits. Praveen has worked on Teradyne Flex test systems and has experience with hardware design, test planning, vector creation, characterization, and data analysis. He is proficient in C, VHDL, and various EDA tools.
Ciena India is looking for SVT/PV (System Verification or Product Verification ) Engineer with 2 Plus Year experience with Layer 2 / Packet / MPLS Technology. Candidate can apply directly to me at nabajaj@ciena.com.
Ciena India is looking for SVT/PV (System Verification or Product Verification ) Engineer with 2 Plus Year experience with Layer 2 / Packet / MPLS Technology. Candidate can apply directly to me at nabajaj@ciena.com.
Embitel’s VLSI team has rich experience in design and validation of complex digital designs, FPGA design services, ASIC design service, chip design and verification, IP Development and SoCs across UK, Germany, France, Sweden, Finland and Netherlands.
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the modular netlist and test languages (ICL and PDL) to facilitate the description of the components involved in analog tests as well as the content of the tests themselves.
Embitel’s VLSI team has rich experience in design and validation of complex digital designs, FPGA design services, ASIC design service, chip design and verification, IP Development and SoCs across UK, Germany, France, Sweden, Finland and Netherlands.
eInfochips proven physical design flow, methodologies, and rich experience helps us to deliver physical design implementation with superior performance across 180 -16nm technology node. Our comprehensive internal checklist for Sign off ensures Netlist to GDSII in < 3 iterations.
Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the modular netlist and test languages (ICL and PDL) to facilitate the description of the components involved in analog tests as well as the content of the tests themselves.
1. PRAVEEN KUMAR Correspondence Address
Semiconductor Test Engineer-Digital and Analog C/o-Vijay Prasad ,
Phone No: +91-7406490263 Vill-Nayadih, PO-Derhgaon
PS-Kashichak,
Dist-Nawada,
Bihar, PIN-805130
Email: praveen5932@gmail.com
Profile
2.5 years experience as a Test engineer in Tessolve Semiconductor Pvt Ltd.
Professional Summary
• Experience in post silicon validation, Characterization and ATE environment.
• Have good experience in AC characteristics, DC characteristics and functional tests
debugging.
• Have good experience in validating of DIGITAL (Micro Controllers) & PMIC (Buck &
Boost Converters) devices.
• Sound knowledge on digital and analog circuit design & concepts and developing the test
programs, test plans as per device specs.
• Experience on hardware design – Schematic capture, lay out and PCB design rules
• Have good experience in designing the validation boards, HIB (Hardware interface board),
PIB (Probe Interface board) and Probe cards, supported to PCB team in Schematic
Placement, Routing stages.
• Working experience on Teradyne Flex ATEs , Handlers , Probers and Complex
test systems
• Good understanding on Reliability engineering, such as HV Screening, ESD/Leakage, Thermal
Cycling etc
• Exposure on data analysis of tested results (eg: Cpk, Cgm, Correlation, Overkill, under kill
Analysis etc.)
• Have good knowledge on SCAN, ATPG, boundary Scan etc.
• Have experience in SOC (Pressure Sensor System) validation.
• Able to develop data analysis scripts using VB.
• Have good programming skills in C language and VHDL.
• Have good knowledge on different type of trimmings (Vbg(band gap), Iref, oscillator, Vref
etc.), communication protocols (SPI,JTAG), Memory blocks (OTP, EEPROM),
Regulators
• Very familiar with oscilloscope, functional generators, logical analyzer etc.
Roles and Responsibilities
• Test List/ Test Plan Development
• Hardware design and development
• Schematic creation and review, Placement review, Layout verification
• Test Vector Creation/ Conversion
• Test Program Development & debug.
2. • Characterization, Correlation
• Support for reliability engineering and Data analysis
• Optimization (Process, Test Time, Test Limits etc), Release to Production
Software or Programming Skills
• Programming languages :C, Assembly Languages 8051, VBA, VHDL
• Software packages : Xilinx, MATLAB, TINA, Allegro
ATE Platforms experience
• Ultra Flex, Integra Flex
• J750
Educational Qualifications
B Tech in Electronics and Communication Engineering, passed with first class with distinction
DETAILED WORK EXPERIENCE
Ι) PROJECT: J750 to Ultra FLEX Conversion for Final Test
ATE: Ultra Flex
DEVICE DESCRIPTION: This is a microcontroller unit for safety application in automobile.
Device having two type of packaging BGA and LQFP with different pin count
ROLES AND RESPONSIBILITIES:
• Involved in test program development , test debug and test time reduction
Involved in critical test debug of module ADC, PMC(Power Management controller), Temp
sensor, OSC.
• Successfully completed debug for multisite x8 and x12 for BGA and LQFP respectively.
• Having knowledge of Instrument like UP1600,UP800, UVI80, UVS256 UPAC80 source
and capture.
ΙΙ) PROJECT: Probe and FT Conversion from Single Site to Octal Site
ATE: Integra Flex
DEVICE DESCRIPTION: Device is Ultrasonic interface controller, Used for communication to
the Ultrasonic Sensors (Protocol Controller and Transceiver).
ROLES AND RESPONSIBILITIES:
• Involved in Design of Load Board, Probe Card and Prober Interface .
• Developed and debugged test program for wafer and package part.
• Worked on JTAG and SPI interface.
3. • Debugged critical test like Bandgap, Oscillator ,Iref, HSS trimming,
• Prepared preliminary Cgm report for data analysis.
• Having knowledge of different IG-XL tools and different Integra Flex instruments.
ΙΙΙ) PROJECT: Probe and FT Conversion from Single Site to Octal Site
DEVICE DESCRIPTION: Device is a sensor which controls the ultrasonic drive pulse and
processes the received echo signal.
ATE: Integra Flex
ROLES AND RESPONSIBILITIES
• Converted customer library function to standard routines to use in our program.
• Involved in Design of Load Board, Probe Card and Prober Interface Board.
• Developed and debugged test program for wafer and package part.
• Debugged critical test like Bandgap, Oscillator, Iref and high current trimming.
Ις) Project: Program audit
ATE: Ultra Flex
PROJECT DESCRIPTION: This is production program review for the 100% compliance for the
test spec, test method and limits
ROLES AND RESPONSIBILITIES
• Compared Spec Vs Production ETS code.
• Found some critical error, limit mismatch and created the report which shared with TE.
Praveen Kumar