MPMC all units .pdf

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Department of Electronics & Communication
Engineering
Notes for B.Tech Students
Microprocessors and Microcontrollers
ETEC-305
Fifth Semester
Maharaja Surajmal Institute of Technology
C-4, Janak Puri, New Delhi

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Microprocessors and Microcontrollers
Paper Code: ETEC-305 L T/P C
Paper: Microprocessors and Microcontrollers 3 1 4
INSTRUCTIONS TO PAPER SETTERS: MAXIMUM MARKS: 75
1.
Question No. 1 should be compulsory and cover the entire syllabus. This question should have objective or
short answer type questions. It should be of 25 marks.
2.
Apart from Question No. 1, rest of the paper shall consist of four units as per the syllabus. Every unit should
Objective:e of the paper is to facilitate the student with the knowledge of microprocessor systems and
microcontroller.
UNIT- I
Introduction to Microprocessor Systems: Architecture and PIN diagram of 8085, Timing Diagram,
memory organization, Addressing modes, Interrupts. Assembly Language Programming. [T1][No. of
hrs. 10]
UNIT- II
8086 Microprocessor: 8086 Architecture, difference between 8085 and 8086 architecture, generation of
physical address, PIN diagram of 8086, Minimum Mode and Maximum mode, Bus cycle, Memory
Organization, Memory Interfacing, Addressing Modes, Assembler Directives, Instruction set of 8086,
Assembly Language Programming, Hardware and Software Interrupts.
[T2][No. of hrs. :12]
UNIT- III
Interfacing of 8086 with 8255, 8254/ 8253, 8251, 8259: Introduction, Generation of I/O Ports, Programmable
Peripheral Interface (PPI)-Intel 8255, Sample-and-Hold Circuit and Multiplexer, Keyboard and Display
Interface, Keyboard and Display Controller (8279), Programmable Interval timers (Intel 8253/8254), USART
(8251), PIC (8259), DAC, ADC, LCD, Stepper Motor.
[T1][No. of hrs. :12]
UNIT-IV
Overview of Microcontroller 8051: Introduction to 8051 Micro-controller, Architecture, Memory
organization, Special function registers, Port Operation, Memory Interfacing, I/O Interfacing, Programming
8051 resources, interrupts, Programmer’s model of 8051, Operand types, Operand addressing, Data transfer
instructions, Arithmetic
instructions, Logic instructions, Control transfer instructions, Timer & Counter Programming,
Interrupt Programming. [T3][No. of hrs. 11] Text Books:
[T1] Muhammad Ali Mazidi, “Microprocessors and Microcontrollers”, Pearson, 2006
[T2] Douglas V Hall, “Microprocessors and Interfacing, Programming and Hardware” Tata McGraw Hill,
2006.
[T3] Ramesh Gaonkar, “MicroProcessor Architecture, Programming and Applications with the 8085”, PHI

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1.1 Introduction to Microprocessor Systems
Microprocessor is an electronic chip that functions as the central processing unit of a computer. All processors
are use the basic concept of stored program execution. Program or instructions are stored sequentially in the
memory. Every microprocessor has its own associated set of instructions. Instruction set for microprocessor
is in two forms one in mnemonic, which is comparatively easy to understand and the other is binary machine
code. The main function of microprocessor is to perform several functions as well as decision making for
changing the series of program implementation. In computers, a central processing unit will be executed on
single or additional circuit boards to perform the computing task.
Definition: A microprocessor is a multipurpose, clock-driven, register-based electronic devices that reads
binary instructions from a storage device called memory, accepts binary data as input and process data
according to those instructions, and provides result as output.
8085 microprocessor:
● It is one kind of semiconductor device synchronised by clock. This processor can be built with
electronic logic circuits that are fabricated using the technologies like VLSI or LSI.
● The actual name of this processor is 8085 A and it consists of thousands of transistors. This
processor is available in 3 versions such as 8085 AH, 8085 AH1 add 8085 AH2 with clock
frequencies 3 MHz, 5MHz and 6MHz resp. The highly developed versions use 20% of power
supply.
● The Intel 8085 is an 8-bit microprocessor that can deal with memory of 64K byte, introduced by
Intel in 1977. The 8085 is a conventional Neumann design based on the Intel 8080.
● It is designed by using NMOS technology. The "5" in the model number came from the fact that the
8085 requires only a +5-Volt (V) power supply rather than requiring the +5 V, −5 V and +12 V
supplies the 8080 needed.
● It has 8 bit data bus and 16 bit address bus. It can work up to 5 MHz frequency and works at 3.2
MHz single segment clock.. It has 40 pins in its chip. Lower order address bus is multiplexed with
data bus to minimize the chip size.
● The 8085 has extensions to support new interrupts, with three maskable interrupts (RST 7.5, RST
6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one externally serviced interrupt
(INTR). The RST n.5 interrupts refer to actual pins on the processor, a feature which permitted
simple systems to avoid the cost of a separate interrupt controller.
Microprocessor based system:
Fig-1.1 shows a simplified but formal structure of a microprocessor-based or a product. It includes three
components: Microprocessor, I/O (Input/output), and Memory (read/write memory and read only memory).
These components are organized around a common communication path called a bus. The entire group of
components is also referred to as a system or a microcomputer system, and the components themselves are
referred to as sub-system.

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Figure 1.1 Microprocessor-based System with bus Architecture
Microprocessor:
The microprocessor is one component of the microcomputer. The microprocessor can be divided into three
segments for the sake of clarity, as shown in fig-1: Arithmetic/Logic unit (ALU), register array, and control
unit. The most important part of microprocessor is CPU.
Arithmetic/logic unit: This is the area of the microprocessor where various computing functions are
performed on data. The ALU unit performs such as arithmetic operation as addition and subtraction, and
such logic operations as AND, OR, and exclusive-OR.
Register Array: This area of the microprocessor consists of various registers identified by letters such as
B, C, D, E, H, and L. These register are primarily used to store data temporarily during the execution of a
program and are accessible to the user through instructions
Control unit: The control unit provides the necessary timing and control signals to all the operations in the
microcomputer. It controls the flow of data between the microprocessor and memory and peripherals.
Memory:
Memory stores such binary information as instructions and data, and provides that information to the
microprocessor whenever necessary. To execute programs, the microprocessor reads instruction and data
from memory and performs the computing operation in its ALU section. Results are either transferred to the
output section for display or stored memory for later use. The block shown in fig-1 has two section: Read-
only memory (ROM) and Read/Write memory (R/WM), popularly known as Random-Access memory
(RAM).
I/O (input/output):
The third component of a microprocessor-based system is I/O; It communicates with outside world. I/O
includes two types of devices: input and output. These I/O devices also known as peripherals. The input
devices such as keyboard, switches, and an analog to digital convertor (A/D) transfer binary information
from the outside world to the microprocessor. The output devices transfer data from the microprocessor to
the outside world. They includes devices such as: light emitting diodes (LED), a cathode ray tube (CRT) or
video screen, a printer, X-Y plotter, a magnetic tape, and digital to analog convertor (D/A).
System Bus:
The system bus is a communication path between the microprocessor and peripherals: it is nothing but a
group of wires to carry bits. In fact, there are several buses in the system. All peripherals and memory share
the same bus; however, the microprocessor communicates with only one peripheral at a time. The timing is
provided by the control unit of the microprocessor. [1]

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1.2 Architecture of 8085
8085 architecture consists of five functional units: both the temporary registers as well as accumulator are
utilised for holding the information throughout in the operations then the outcome will be stored within the
accumulator. The different flags are arranged or rearrange based on the outcome of operation.
1. Arithmetic and logic unit:
The ALU performs the actual numerical and logic operation such as addition, increment, subtraction,
decrement, logical operations like AND, OR, Ex-OR, Complement, evaluation, left shift or right shift. Uses
data from memory and from Accumulator to perform arithmetic. Always stores result of operation in
Accumulator.
2. General purpose registers: [Register Array]
• The general purpose programmable registers are classified into several types apart from the
accumulator such as B, C, D, E, H and L. These are utilised as 8 bit registers otherwise coupled to
stock up the 16 bit of data. The programmer can use these registers to store or copy data into the
registers by using data copy instructions.
• 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C
register contains low-order byte. Some instructions may use BC register as a data pointer.
• 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E
register contains low-order byte. Some instructions may use DE register as a data pointer.
• 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L
register contains low-order byte. HL register usually contains a data pointer used to reference
memory addresses.
• The short term W & Z registers are used in the processor and it cannot be utilised with the developer.

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Figure 1.2 the functional Block Diagram of 8085 Microprocessor
3. Special purpose registers:
a) Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). The result of an operation
is stored in the accumulator. The accumulator is also identified as register A.
b) Flag is an 8-bit register containing 5 1-bit flags.The ALU includes five flip-flops, which are set or reset
after an operation according to data conditions of the result in the accumulator and other registers. They
are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit
positions in the flag register are shown in the Figure below. The most commonly used flags are Zero,
Carry, and Sign. The microprocessor uses these flags to test data conditions.
These flags have critical importance in the decision-making process of the microprocessor. The
conditions (set or reset) of the flags are tested through the software instructions. For example, the
instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY
flag is set. The thorough understanding of flag is essential in writing assembly language programs.
● Sign - set if the most significant bit (D7) of the result is set (1).
● Zero - set if the result (of ALU operation) is zero.
● Auxiliary carry - set if there was a carry out from bit 3 (lesser nibble) to bit 4 of the result.
● Parity - set if the parity (the number of set bits in the result) is even.
● Carry - set if there was a carry during addition, or borrow during subtraction/comparison.
Note- between the 5 types of flags, the AC flag is employed on the inside intended for BCD arithmetic
as well as remaining 4 flags are used with the developer to make sure the conditions of outcome of a
process.
c) Stack pointer: It is a 16-bit register used as a memory pointer. It points to a memory location in
R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack
pointer. This register is always incremented/decremented by 2 throughout push or pop process.
d) Program counter: It is a 16-bit register that deals with sequencing the execution of instructions. This
register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.
The microprocessor uses this register to sequence the execution of the instructions. The function of
the program counter is to point to the memory address from which the next byte is to be fetched. When a
byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory
location.
Address bus and data bus: the data bus is useful in carrying the related information that is to be stock up.
It is bidirectional, but address bus indicates the position as to where it must be stored and it is unidirectional,
useful for transmitting the information as well as addressing input/output devices.
Increment or decrement register: the 8 bit register contents or else a memory position can be increased or
decreased with a one. The 16 bit register is useful for incrementing or decrement program counters as well
as stack pointer register content with one. This operation can be performed on any memory position or any
kind of register.
Address-buffer and address-data buffer: address buffer stores the copied information from the memory
for the execution. The memory and I/O chips are associated with these buses; CPU can replace the preferred
data by I/O chips and the memory.
4. Instruction register and decoder:
Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to
execution. Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded instruction
then passed to next stage.

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5. Timing and control unit: Generates signals within microprocessor to carry out the instruction, which has
been decoded. In reality causes certain connections between blocks of the microprocessor to be opened or
closed, so that data goes where it is required, and so that ALU operations occur.
It coordinates with all the actions of microprocessor by the clock and gives the control signals which are
required for communication among the microprocessor as well as peripherals.
The timing and control units are used to control the internal as well as external circuits. These are classified
into 4 types namely control units, status units, reset units and DM like HLDA and HOLD.
1.3 Pin Diagram of 8085
Figure 1.3 pin diagram of 8085
● 8085 up is an 8-bit general purpose microprocessor capable of addressing 64Kb of memory.
The device has 40 pins, +5 V power supply, operate on 3 to 5 MHZ frequency single phase clock.
All the signals can be classified in 8085 up pin diagram into six groups –
1) Address Bus: in this 16 signals lines. These lines are splits into two segments –
a) Address bus A15-A8 – unidirectional and used for the higher order address (MSB).
b) Address bus or Data bus AD7-AD0 – Dual purpose, these pins are applicable for LSB
(least significant bits) of the address bus in the primary apparatus clock cycle as well as
employed as data bus for second clock cycle and 3rd
clock cycle. A clock cycle can be
designed as, the time in use among 2 oscillator’s nearby pulses, or simply it can refer to
zero volts. Here the first clock is the primary transition of pulse ranges from zero Volt to
5 Volt and reaches back to zero bolt.
2) Control and status signals: these signals are used to identify the nature of operation.
Three control signals that are-

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RD – it is an active low signal that indicates an operation is executed whenever the indication goes small, it
is used for controlling the microprocessor read operation. When RD pin goes small then microprocessor
understands or reads the information from I/O device or memory.
WR-it is an active low signal. It controls the microprocessor write operations. When this pin goes small, then
the information will be written to the I/O device or memory.
ALE (Address Latch Enable) - it is a +ve going pulse generated every time the 8085 begins an operation
(machine cycle). It helps in demultiplexing the data bus as well as low order address. This will go high
throughout the primary clock cycle as well as allows the address bits with low order. The address bus with
low order is added for memory otherwise any exterior latch.
Three status signals that are –
IO/M- this is a status signal used to differentiate between IO and Memory operations. When the address is
high then the address of address bus is used for devices of input or output devices. When the address is low
then the address of address bus is used for the memory.
S1 and S0- status signals, similar to IO/M, can identify various operations. That are rarely used in the
systems. Status signal represent some operation in 8085 as defined in Table-1.
Table-1.1 status signal
S1 S0 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
3) Power supply:
VCC: +5 V pin
VSS: Ground pin
4) Clock Frequency:
X1, X2: A crystal (RC, LC N/W) is connected at these two pins. This frequency is internally divided by 2.X1
and X2 terminals are associated with the exterior oscillator for generating the required as well as appropriate
operation of clock.
CLK OUT: clock output this signal can be used as the system clock for the other peripherals or digital
integrated circuits.
5) Externally initiated signals: Five interrupt signals: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
INTA: interrupt acknowledge
RESET IN: It is an active low signal. It is used to reset the program counter towards zero and rearranges
interrupt enable as well as HLDA flip flops. The central processing unit is detained in RST condition till this
pin is high. But the registers as well as flags won’t get damaged apart from instruction register.
RESET OUT: This signal indicates that the CPU is being reset, the signal can be used to reset other devices.
READY: If ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to
send or receive data. If ready is low, the CPU will wait for ready to go high before completing the read or
write cycle.

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HOLD: this signal indicate that another master (means any other device) is requesting the use of the address
and data buses. For example: the 2 devices are LCD and A/D converter. Assume that if A/D converter is
employing the address bus as well as a data bus, when LCD desires the utilise of both the buses by providing
hold signal, subsequently the microprocessor transmits the control signal towards the LCD after that the
existing cycle will be ended. When the LCD procedure is over, then the control signal is transmitted reverse
to A/D converter.
HLDA: HOLD Acknowledge (response signal of HOLD) indicates that the CPU has received the Hold
request. HLDA goes low after the HOLD request is removed. The CPU takes the buses one half clock cycle
HLDA goes low.
6) Serial I/O ports:
SOD: serial output data line, the data on this pin sends its output towards the 7th
bit of accumulator whenever
a SIM instruction is executed.
SID: Serial input data line, the data on this line is loaded into 7th
bit of accumulator whenever a RIM (Read
Interrupt Mask) instruction is executed. RIM verifies the interrupt whether it is covered or not covered.
In this data bits are sent over a single line one bit at a time.
For ex: Transmission over phone lines. [1]
1.4 Timing Diagrams of 8085
It is one of the best way to understand to process of micro-processor/controller. With the help of timing
diagram, we can understand the working of any system, step by step working of each instruction and its
execution, etc. It is the graphical representation of process in steps with respect to time. The timing diagram
represents the clock cycle and duration, delay, content of address bus and data bus, type of operation i.e.
Read/write/status signals.
Important terms related to timing diagrams:
1. Instruction cycle: this term is defined as the number of steps required by the CPU to complete the entire
process i.e., Fetching and execution of one instruction. The fetch and execute cycles are carried out in
synchronization with the clock.
2. Machine cycle: It is the time required by the microprocessor to complete the operation of accessing the
memory devices or I/O devices. In machine cycle various operations like opcode fetch, memory read,
memory write, I/O read, I/O write are performed.
3. T-state: Each clock cycle is called as T-states.
Rules to identify number of machine cycles in an instruction:
1. If an addressing mode is direct, immediate or implicit then No. of machine cycles = No. of bytes.
2. If the addressing mode is indirect then No. of machine cycles = No. of bytes + 1. Add +1 to the No. of
machine cycles if it is memory read/write operation.
3. If the operand is 8-bit or 16-bit address then, No. of machine cycles = No. of bytes +1.
4. These rules are applicable to 80% of the instructions of 8085.
Timing Diagram:

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Figure 1.4 Instruction Cycle Where,
Instruction cycle= Fetch Cycle(FC) + Execute cycle(EC).
Opcode fetch:
The microprocessor requires instructions to perform any particular action. In order to perform these actions
microprocessor utilizes Opcode which is a part of an instruction which provides detail (i.e., Which
operation a µp needs to perform) to microprocessor.
Figure 1.5 Opcode fetch timing diagram Operation:
1. During T1 state, microprocessor uses IO/M (bar), S0, and S1 signals are used to instruct microprocessor
to fetch opcode. Thus, when IO/M (bar) =0, S0=S1= 1, it indicates opcode fetch operation. During this
operation 8085 transmits 16-bit address and also uses ALE signal for address latching.
2. At T2 state microprocessor uses read signal and make data ready from that memory location to read opcode
from memory and at the same time program counter increments by 1 and points next instruction to be
fetched. In this state microprocessor also checks READY input signal, if this pin is at low logic level i.e.,
'0' then microprocessor adds wait state immediately between T2 and T3.
3. At T3, microprocessor reads opcode and store it into instruction register to decode it further.
4. During T4 microprocessor performs internal operation like decoding opcode and providing necessary
actions.
5. The opcode is decoded to know whether T5 or T6 states are required, if they are not required then µp
performs next operation.
Read and write timing diagram for memory and I/O Operation
Figure 1.6 Memory read timing diagram

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Operation:
1. It is used to fetch one byte from the memory.
2. It requires 3 T-States.
3. It can be used to fetch operand or data from the memory.
4. During T1, A8-A15 contains higher byte of address. At the same time ALE is high. Therefore, Lower byte
of address A0-A7 is selected from AD0-AD7.
5. Since it is memory ready operation, IO/M(bar) goes low.
6. During T2 ALE goes low, RD(bar) goes low. Address is removed from AD0-AD7 and data D0-D7 appears
on AD0-AD7.
7. During T3, Data remains on AD0-AD7 till RD(bar) is at low signal.
Memory Write:
Figure 1.7 Memory write timing diagram Operation:
It is used to send one byte into memory.
2. During T1, ALE is high and contains lower address A0-A7 from AD0-AD7.
3. A8-A15 contains higher byte of address.
4. As it is memory operation, IO/M(bar) goes low.
5 During T2, ALE goes low, WR(bar) goes low and Address is removed from
AD0-AD7 and then data appears on AD0-AD7.
6 Data remains on AD0-AD7 till WR(bar) is low. IO Read:
Figure 1.8 I/O read timing diagram Operation:
1. It is used to fetch one byte from an IO port.

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3. During T1, The Lower Byte of IO address is duplicated into higher order address bus A8-A15.
4. ALE is high and AD0-AD7 contains address of IO device.
5. IO/M (bar) goes high as it is an IO operation.
6. During T2, ALE goes low, RD (bar) goes low and data appears on AD0-AD7 as input from IO device.
7. During T3 Data remains on AD0-AD7 till RD(bar) is low. IO Write:
Figure 1.9 I/O write timing diagram Operation:
1. It is used to write one byte into IO device.
3. During T1, the lower byte of address is duplicated into higher order address bus A8-A15.
4. ALE is high and A0-A7 address is selected from AD0-AD7.
5. As it is an IO operation IO/M (bar) goes low.
6. During T2, ALE goes low, WR (bar) goes low and data appears on AD0-AD7 to write data into IO device.
7. During T3, Data remains on AD0-AD7 till WR(bar) is low. [2]
1.5 Memory organization
Memory Interfacing:-As we know that any system which process digital data needs the facility for storing
the data. Interfacing is a technique to be used for connecting the Microprocessor to Memory. Now a days
Semiconductor memories are used for storing purpose. There are some of the advantages of the
semiconductor memory.
Small size
High speed
Better reliability
Low cost
Generally, RAM or ROM is used for memory interfacing.
Memory:-A memory is a digital IC which stores the data in binary form.
Memory Size:-The number of location and number of bits per word will vary from memory to memory.
For example, if a particular memory chip is capable of storing M words with each word having N-bits.
Then the size of the memory will be M× N.
Interfacing a ROM memory of 4096*8 with 8085 Microprocessor:-
Given memory size = 4096 * 8 4096 =2^12.
So, 12 lines will be used for interfacing. A0 to A11

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In this system A0 to A11 lines of Microprocessor will be connected to the address lines of the memory and
D0 to D7 of the 8085 microprocessor will be connected to the data bus of the memory. As we know that it is
EPROM, so only RD pin is connected to the microprocessor. There is not the facility for writing data. In case
if you are using RAM then you have to connect one more pin for writing operation. [3]
Figure 1.10 Memory Interfacing
1.6 Addressing Modes in 8085
To perform any operation using microprocessor, we have to give the corresponding instruction to
microprocessor. For executing any instruction, microprocessor requires data. Hence along with the
instruction, we have to give address of source data. The method by which address of source data is given in
an instruction is called as addressing mode of source.
Using the value of data, microprocessor will execute the instruction to obtain the result. For storing these
result, microprocessor will need destination, so along with the instruction we have to give address of
destination of result. The method of which address of destination is given in an instruction is called addressing
mode of destination.
The way of specifying data to be operated by an instruction is called addressing mode. Part of programming
flexibility for each microprocessor is the number and different kind of ways the programmer can refer to data
stored in the memory. The different ways that a microprocessor can access data are referred as addressing
modes.
There are five addressing modes in 8085.
1. Immediate Addressing Mode: - In this mode, the source operand is always data. If 8/16 bit
data required for executing the instruction is given along with the instruction. If the data is 8 bit
then the instruction will be of 2 bytes, if the data is of 16 bit the instruction will be of 3 bytes. In
these instructions the last alphabet of mnemonic will be generally I . Eg:-
MVI A, 30H (30H is copied into the register A)
MVI B,40H(40H is copied into the register B).
LXI H 3050
2. Register Addressing Mode: - in this mode, the 8/16 bit data to be operated is available inside
the register/register pair. And register/register pair is used as operands or the name of
register/register pair is given along with the instruction . Eg: -
MOV B, A (the content of A is copied into the register B)
MOV A, C (the content of C is copied into the register A).
ADD B
3. Direct Addressing Mode: - in this mode, 8/16 bit data to be operated is available inside a
memory location. And the 16 bit address of memory location is directly specified as operand or
16 bit address of this memory location is given alongwith the instruction. Eg: -

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LDA 3000H (The content at the location 3000H is copied to the register A).
STA 9000H
4. Register Indirect Addressing Mode: - in this mode, 8/16 bit data to be operated is available
inside a memory location. And the 16 bit address of memory location is indirectly specified by a
register pair or 16 bit address of memory location is present in register pair and the name of
register pair is given along with the instruction.
Eg: - MOV A, M (data is transferred from the memory location pointed by the register to the accumulator).
LDAX B
STAX B
5. Implied/Implicit Addressing Mode: - in this mode, the operand is hidden and the 8/16 bit
data to be operated is available in the instruction itself. Or if the address of source of data and
address of destination of result is fixed then there is no need to give any operand along with the
instruction.
Eg: - RAL, CMP [3]
1.7 Interrupts in 8085
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor
and get itself serviced. Generally, interrupt signals are generated by external devices to request the
microprocessor to perform a particular task. In the microprocessor-based system the interrupts are used for
data transfer between the peripheral devices and the microprocessor.
Interrupt Service Routine (ISR): A small program or a routine that when executed services the corresponding
interrupting source is called as an ISR.
Maskable/Non-Maskable Interrupt: An interrupt that can be disabled by writing some instruction is known
as Maskable Interrupt otherwise it is called Non-Maskable Interrupt.
Vector interrupt: in this type of interrupt, the interrupt address is known to the processor. for example:
RST 7.5, RST 6.5, RST 5.5 and trap.
Non vector interrupt: in this type of interrupt, the interrupt address is not known to the processor so, the
interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR
There are 6 pins available in 8085 for interrupt:
1. TRAP
2. RST 7.5
3. RST6.5
4. RST5.5
5. INTR
6. INTA
Execution of Interrupts
When there is an interrupt requests to the Microprocessor then after accepting the interrupts

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Microprocessor send the INTA (active low) signal to the peripheral. The vectored address of particular
interrupt is stored in program counter. The processor executes an interrupt service routine (ISR) addressed
in program counter.
There are two types of interrupts used in 8085 Microprocessor:
1. Hardware Interrupts
2. Software Interrupts
Software Interrupts
A software interrupts is a particular instructions that can be inserted into the desired location in the program.
There are eight Software interrupts in 8085 Microprocessor. From RST0 to RST7.
1. RST0
2. RST1
3. RST2
4. RST3
5. RST4
6. RST5
7. RST6
8. RST7
They allow the microprocessor to transfer program control from the main program to the subroutine
program. After completing the subroutine program, the program control returns back to the main
program. We can calculate the vector address of these interrupts using the formula given below:
Vector Address = Interrupt Number * 8 For Example:
RST2: Vectored address = 2*8 =16
RST1: Vectored address = 1*8 =08
Table: 1.2 Vector address table for the software interrupts
Interrupt Vectored Address
RST0 0000H
RST1 0008H
RST2 0010H
RST3 0018H
RST4 0020H
RST5 028H
RST6 0030H
RST7 0038H
Hardware Interrupt
I have already discussed that there are 6 interrupt pins in the microprocessor used as Hardware Interrupts
given below:

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1. TRAP
2. RST7.5
3. RST6.5
4. RST5.5
5. INTR
INTA is not an interrupt. INTA is used by the Microprocessor for sending the acknowledgement. If 8085
gets an interrupt signal it is recognised by INTA. As a result, when the interrupt will be obtained then INTA
will be high.
TRAP has highest priority and RST7.5 has second highest priority and so on.
Table: 1.3 The Vector address of these interrupts
Interrupt Vectored Address
RST7.5 003CH
RST6.5 0034H
RST5.5 002CH
TRAP 0024H
TRAP
It is non maskable edge and level triggered interrupt. TRAP has the highest priority and vectors
interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is
acknowledged. In case of sudden power failure, it executes a ISR and send the data from main memory
to backup memory. TRAP cannot be masked but it can be delayed using HOLD signal. This interrupt
transfers the microprocessor's control to location 0024H. TRAP interrupts can only be masked by
resetting the microprocessor. There is no other way to mask it. By default, it is enabled until it gets
acknowledged.
RST7.5
It has the second highest priority. It is maskable and edge level triggered interrupt. The vector address of
this interrupt is 003CH. Edge sensitive means input goes high and no need to maintain high state until it is
recognized. It can also be reset or masked by resetting microprocessor. It can also be resettled by DI
instruction. When this interrupt is executed, the processor saves the content of PC register into the stack and
branches to 003C H address.
RST6.5 and RST5.5
These are level triggered and maskable interrupts. When RST6.5 pin is at logic 1, INTE flip-flop is set.
RST 6.5 has third highest priority and RST 5.5 has fourth highest priority. It can be masked by giving DI
and SIM instructions or by resetting microprocessor. When this interrupt is executed, the processor saves
the content of PC register into the stack and branches to 0034 H and 002C H address resp.
INTR
It is level triggered and maskable interrupt. The following sequence of events occurs when INTR signal goes
high:
1. The 8085 checks the status of INTR signal during execution of each instruction.

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2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt
acknowledge signal, if the interrupt is enabled.
3. On receiving the instruction, the 8085 save the address of next instruction on stack and execute
received instruction.
It has the lowest priority. It can be disabled by resetting the microprocessor or by DI and SIM instruction. [3]
1.8 Assembly language programming
An assembly language program is a set of instructions written in the mnemonics of a given microprocessor.
These instructions are the commands to the microprocessor to execute in the given sequences to accomplish
a task. To write such program for the 8085 microprocessor, we should be familiar with programming model
and instruction set of the microprocessor.
The 8085 Programming Model:
The 8085-programming model includes six registers, one accumulator, and one flag register, as shown
in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are
described briefly as follows.
Figure 1.11 Programming Model
Register, Accumulator, Flags, Program counter (PC) and Stack Pointer (SP)
Instruction Set
An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The
instruction set of microprocessor is the collection of instructions that the microprocessor is designed to
execute. Each instruction is represented by 8-bit binary value. Intel 8085 is an 8-bit microprocessor. It handles
8-bit data at a time. One byte consists of 8bits.A memory location for Intel 8085 microprocessor is designed
to accumulate 8-bit data. If 16bit data are to be stored, they are stored in consecutive memory locations. The
address of memory location is 16-bit i.e., 2 bytes.
Due to different ways of specifying data for instruction are not of same length.
So, there are three types of instructions of Intel 8085:
(1) Single byte instruction
(2) Two-byte instruction
(3) Three-byte instruction
1. Single-Byte instruction:
The content information regarding operands in the opcode itself .These are of one byte.
Ex-MOV A,B ; Move the content of register B to A
78H is opcode for MOV A, B. The binary form of opcode 78H is 01111000. The first two bit i.e., 01 for
MOV operation; the next 3 bits i.e., 111 for register A and last 3 bits 000 are for register B.
2. Two-Byte instruction.

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In case of two-byte instruction the 1st byte of the instruction is opcode and 2nd byte is either data or address.
Both bytes are stored in two consecutive memory locations.
Ex-MVI B, 05; Move 05 to register B
06, 05; MVI B, 05 in the code form
Here in this case the 1st byte i.e., 06 is the opcode for MVI B and 2nd byte i.e., 05 is the data which is to be
moved to register B.
3. Three-Byte instruction.
In case of three bytes instruction the 1st byte of instruction is opcode and 2nd and 3rd byte of instruction are
either 16-bit data or 16-bit address.
They are stored in three consecutive memory locations. Ex-
LXI H, 2400H ; load H-L pair with 2400H
21,00,24; LXI H, 2400H in code form.
Here 1st byte i.e., 21 is the opcode for instruction LXI H. The 2nd byte i.e., 00 is 8 LSBs of data which is
loaded in to register L. The 3rd byte i.e., 24 is 8 MSBs of data which is loaded in to register H.
Types of instruction set:
The 74 instructions available in the 8085A (out of maximum 256 different operation) can be divided into
five groups depending on their function.
1) Data transfer instructions:
Instructions, which are used to transfer data from one register to another register, from memory to register or
register to memory, come under this group. Examples are: MOV, MVI, LXI, LDA, STA etc. When an
instruction of data transfer group is executed, data is transferred from the source to the destination without
altering the contents of the source (means the previous data of the source is not lost, but the previous data of
destination will be lost). For example, when MOV A, B is executed the content of the register B is copied
into the register A, and the content of register B remains unaltered. Similarly, when LDA 2500 is executed
the content of the memory location 2500 is loaded into the accumulator. But the content of the memory
location 2500 remains unaltered.
EXAMPLES:
1. MOV r1, r2 (Move Data; Move the content of the one register to another). [r1] <-- [r2]
2. MOV r, m (Move the content of memory register). r <-- [M]
3. MOV M, r. (Move the content of register to memory). M <-- [r]
4. MVI r, data. (Move immediate data to register). [r] <-- data.
5. MVI M, data. (Move immediate data to memory). M <-- data.
6. LXI rap, data 16. (Load register pair immediate). [rp] <-- data 16 bits, [rh] <-- 8 LSBs of data.
7. LDA addr. (Load Accumulator direct). [A] <-- [addr].
8. STA addr. (Store accumulator direct). [addr] <-- [A].
9. LHLD addr. (Load H-L pair direct). [L] <-- [addr], [H] <-- [addr+1].
10. SHLD addr. (Store H-L pair direct) [addr] <-- [L], [addr+1] <-- [H].
11. LDAX rp. (LOAD accumulator indirect) [A] <-- [[rp]]
12. STAX rp. (Store accumulator indirect) [[rp]] <-- [A].
13. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <--> [D-E].
2) Arithmetic instructions:
The instructions of this group perform arithmetic operations such as addition, subtraction; increment or
decrement of the content of a register or memory. Microprocessor can perform the following arithmetic
operation:
i. 8-bit addition without carry
ii. 16-bit addition without carry
iii. 8-bit BCD addition
iv. 8-bit subtraction with or without borrow

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v. Increment and decrement of 16- or 8-bit data
vi. Comparison of 8-bit numbers
Microprocessor will execute arithmetic operations in alu and status of result is copied into status flags. In all
arithmetic instruction the first data is taken from accumulator and result is stored back to accumulator.
Examples:
1). ADD r. (Add register to accumulator) [A] <-- [A] + [r].
2) .ADD M. (Add memory to accumulator) [A] <-- [A] + [[H-L]].
3).ADC r. (Add register with carry to accumulator). [A] <-- [A] + [r] + [CS].
4). ADC M. (Add memory with carry to accumulator) [A] <-- [A] + [[H-L]] [CS].
5) .ADI data (Add immediate data to accumulator) [A] <-- [A] + data.
6) .ACI data (Add with carry immediate data to accumulator). [A] <-- [A] + data + [CS].
7).DAD rp. (Add register paid to H-L pair). [H-L] <-- [H-L] + [rp].
8).SUB r. (Subtract register from accumulator). [A] <-- [A] – [r].
9).SUB M. (Subtract memory from accumulator). [A] <-- [A] – [[H-L]].
10).SBB r. (Subtract register from accumulator with borrow). [A] <-- [A] – [r] – [CS].
11).SBB M. (Subtract memory from accumulator with borrow). [A] <-- [A] – [[H-L]] – [CS].
12).SUI data. (Subtract immediate data from accumulator) [A] <-- [A] – data.
13).SBI data. (Subtract immediate data from accumulator with borrow). [A] <-- [A] – data – [CS].
14).INR r (Increment register content) [r] <-- [r] +1.
15). INR M. (Increment memory content) [[H-L]] <-- [[H-L]] + 1.
16).DCR r. (Decrement register content). [r] <-- [r] – 1.
17).DCR M. (Decrement memory content) [[H-L]] <-- [[H-L]] – 1.
18).INX rp. (Increment register pair) [rp] <-- [rp] – 1.
19).DCX rp (Decrement register pair) [rp] <-- [rp] -1.
20).DAA (Decimal adjust accumulator).
The instruction DAA is used in the program after ADD, ADI, ACI, ADC, etc instructions. After the execution
of ADD, ADC, etc instructions the result is in hexadecimal and it is placed in accumulator. The DAA
instruction operates on this result and gives the final result in decimal system. It uses carry and auxiliary
carry for decimal adjustment. 6 is added to 4 LSBs of the content of accumulator if their value lies in between
A and F or the AC flag is set to 1. Similarly, 6 is also added to 4 MSBs of the content of the accumulator if
their value lies in between A and F or the CS flag is set to 1. All latest flags are affected. When DAA is used
data should be in decimal numbers.
3) Logical instructions:
The instructions which are used to perform logical operation in microprocessor such as and, or, exor, 1’s
compliment, compare, rotate the data towards left/right, with or without carry etc.
1. ANA r (AND Accumulator with Register r Data) [A] <-- [A] AND [r].
CF =0, AC =1 always and Z, S, P will indicate status of result.
2. ANI data (AND Accumulator with Immediate Data) [A] <-- [A] AND data.
3. ANA M (AND Accumulator with Memory Data) [A] <-- [A] AND [[H-L]].
4. ORA r (OR Accumulator with Register r Data) [A] <-- [A] OR [r]. CF =0,
AC =1 always and Z, S, P will indicate status of result.
5. ORI data (OR Accumulator with Immediate Data) [A] <-- [A] OR data. CF
=0, AC =1 always and Z, S, P will indicate status of result.
6. ORA M (OR Accumulator with Memory Data) [A] <-- [A] OR [[H-L]]. CF
=0, AC =1 always and Z, S, P will indicate status of result.
7. XRA r (EX-OR Accumulator with Register r Data) [A] <-- [A] EX-OR [r].

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8. XRI data (EX-OR Accumulator with Immediate Data) [A] <-- [A] EX-OR
data. CF =0, AC =1 always and Z, S, P will indicate status of result.
9. XRA M (EX-OR Accumulator with Memory Data) [A] <-- [A] EX-OR [[H-
L]]. CF =0, AC =1 always and Z, S, P will indicate status of result.
10 CMP r (compare register r with Accumulator and affect flags) [A]-[r].
If [A] > [r] then CF=0, Z=0
If [A] =[r] Then CF=0, Z=1
If [A] < [r] then CF=1, Z=0
11. CPI data (compare immediate data with Accumulator and affect flags) [A]-data.
If [A] > data then CF=0, Z=0
If [A] =data Then CF=0, Z=1
If [A] < data then CF=1, Z=0
12. CMP M (compare memory with Accumulator and affect flags) [A]-[[H-L]].
If [A] > [[H-L]] then CF=0, Z=0
If [A] = [[H-L]] Then CF=0, Z=1
If [A] < [[H-L]] then CF=1, Z=0
13. CMA (Complement Accumulator) [A] <-- [A’]
14. STC (Set carry flag to 1) CF<-- 1
15. CMC (Complement carry flag) CF<-- CF’
16).RLC (Rotate accumulator left) [An+1] <-- [An], [A0] <-- [A7], [CS] <-- [A7].
Figure 1.13
The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry
bit as well as to the zero bit of the accumulator. Only CS flag is affected.
17).RRC. (Rotate accumulator right) [A7] <-- [A0], [CS] <-- [A0], [An] <-- [An+1].
Figure 1.14
The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the
seventh bit as well as to carry bit. Only CS flag is affected.
18). RAL. (Rotate accumulator left through carry) [An+1] <-- [An], [CS] <-- [A7], [A0] <-- [CS].
19).RAR. (Rotate accumulator right through carry) [An] <-- [An+1], [CS] <-- [A0], [A7] <-- [CS].
4) Branching Instructions:
This group includes the instructions for conditional and unconditional jump, subroutine call and return, and
restart.
Examples:
1. JMP addr (label). (Unconditional jump: jump to the instruction specified by the address). [PC] <-- Label.
2. Conditional Jump addr (label): After the execution of the conditional jump instruction the program jumps
to the instruction specified by the address (label) if the specified condition is fulfilled. The program
proceeds further in the normal sequence if the specified condition is not fulfilled. If the condition is true
and program jumps to the specified label, the execution of a conditional jump takes 3 machine cycles:

22
10 states. If condition is not true, only 2 machine cycles; 7 states are required for the execution of the
instruction.
1. JZ addr (label). (Jump if the result is zero)
2. JNZ addr (label) (Jump if the result is not zero)
3. JC addr (label). (Jump if there is a carry)
4. JNC addr (label). (Jump if there is no carry)
5. JP addr (label). (Jump if the result is plus)
6. JM addr (label). (Jump if the result is minus)
7. JPE addr (label) (Jump if even parity)
8. JPO addr (label) (Jump if odd parity)
3. CALL addr (label) (Unconditional CALL: call the subroutine identified by the operand)
CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address
of the next instruction of the main program is saved in the stack. The content of the stack pointer is
decremented by two to indicate the new stack top. Then the program jumps to subroutine starting at address
specified by the label.
4. RET (Return from subroutine).
5. RST n (Restart) Restart is a one-word CALL instruction. The content of the program counter is saved in
the stack. The program jumps to the instruction starting at restart location.
5). Stack, I/O and Machine control instructions:
This group includes the instructions for input or output ports, stack and machine control.
1. IN port-address. (Input to accumulator from I/O port) [A] <-- [Port]
2. OUT port-address (Output from accumulator to I/O port) [Port] <-- [A]
3. PUSH rp (Push the content of register pair to stack)
4. PUSH PSW (PUSH Processor Status Word)
5. POP rp (Pop the content of register pair, which was saved, from the stack)
6. POP PSW (Pop Processor Status Word)
7. HLT (Halt)
8. XTHL (Exchange stack-top with H-L)
9. SPHL (Move the contents of H-L pair to stack pointer)
10. EI (Enable Interrupts)
11. DI (Disable Interrupts)
12. SIM (Set Interrupt Masks)
13. RIM (Read Interrupt Masks)
14. NOP (No Operation). [3]
Application of Microprocessor
A microprocessor makes daily life easier because of its low cost, low power, small weight, and vast
application in every field. There are several applications of microprocessors. Some of the important
applications are:
A. Household Devices
The programmable thermostat allows the control of temperature at homes. In this system, a
microprocessor works with the temperature sensor to determine and adjust the temperature
accordingly. High-end coffee makers, washing machines, and radio clocks contain microprocessor
technology. Some other home items that contain microprocessors are: microwaves, toasters,
televisions, VCRs, DVD players, ovens, stoves, clothes washers, stereo systems, home computers,

23
alarm clocks, hand-held game devices, thermostats, video game systems, bread machines,
dishwashers, home lighting systems and even some refrigerators with digital temperature control.
B. Industrial Applications of Microprocessors
Some industrial items which use microprocessors technology include: cars, boats, planes, trucks,
heavy machinery, elevators, gasoline pumps, credit-card processing units, traffic control devices,
computer servers, most high-tech medical devices, surveillance systems, security systems, and even
some doors with automatic entry.
C. Transportation Industry
Automobiles, trains and planes also use microprocessor technology. Consumer vehicles-buses, cars,
trucks -integrate microprocessors to communicate important information throughout the vehicle.
E.g., navigation systems provide information using microprocessors and global positioning system
(GPS) technology.
D. Computers and Electronics
Microprocessor-drives technology is the brain of the computer. They are used in all type of
computers ranging from microcomputers to supercomputers. A cell phone or mobile device executes
game instructions by way of the microprocessor. VCRs, televisions and gaming platforms also
contain microprocessors for executing complex instructions and tasks.
E. Instrumentation
Microprocessor is also very useful in the field of instrumentation. Function generators, frequency
counters, frequency synthesizers, spectrum analyses and many other instruments are available, when
microprocessors are used as controller.
F. Embedded Systems at Home
A number of modern devices in the home are microprocessor based i.e., camera; washing machines;
calculators; hi-fi systems; telephones; microwave ovens; burglar alarms etc. The input are usually
simple numeric keyboards, sensors, buttons or while the output include lights, simple LCD screens
displays, motors and relays, LEDs, buzzers etc.
G. Office Automation and Publication
Microprocessor based system with software packages has changed the office environment.
Microprocessors based systems are being used for spreadsheet operations, word processing, storage
etc. The Publication technology has revolutionized by the microprocessor.
H. Communication
In communication the telephone industry is most important. In this industry, microprocessors are
used in digital telephone sets, telephone exchanges and modem etc. The use of microprocessor in
satellite communication, television, has made teleconferencing possible.
Railway reservation and airline reservation system also uses microprocessor technology. WAN (Wide Area
Network) and LAN (Local Area Network) for communication of vertical information through computer
network.
EXAMPLES
Example-1. WAP to Count Number of one’s in a number.
Statement: Write a program to count number of l’s in the contents of D register and store the count in the B
register.
1. MVI B, 00H
2. MVI C, 08H
3. MOV A, D
4. BACK: RAR
5. JNC SKIP
6. INR B
7. SKIP: DCR C

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8. JNZ BACK
9. HLT
Sample problem
(2200H) = 04
(2201H) = 34H
(2202H) = A9H
(2203H) = 78H
(2204H) = 56H
Result = (2202H) = A9H
Example-2. WAP to Arrange in ascending order
Statement: Write a program to sort given 10 numbers from memory location 2200H in the ascending order.
1. MVI B, 09 :"Initialize counter"
2. START : LXI H, 2200H: Initialize memory pointer"
3. MVI C, 09H :"Initialize counter 2"
4. BACK: MOV A, M :"Get the number"
5. INX H :"Increment memory pointer"
6. CMP M :"Compare number with next number"
7. JC SKIP :"If less, don’t interchange"
8. JZ SKIP :"If equal, don’t interchange"
9. MOV D, M
10. MOV M, A
11. DCX H
12. MOV M, D
13. INX H :"Interchange two numbers"
14. SKIP:DCR C :"Decrement counter 2"
15. JNZ BACK :"If not zero, repeat"
16. DCR B :"Decrement counter 1"
17. JNZ START
18. HLT :"Terminate program execution"
Example-3. WAP to calculate the sum of series of even numbers
Statement: Calculate the sum of series of even numbers from the list of numbers. The length of the list is in
memory location 2200H and the series itself begins from memory location 2201H. Assume the sum to be 8-
bit number so you can ignore carries and store the sum at memory location 2210H.
Sample problem
2200H= 4H
2201H= 20H
2202H= l5H
2203H= l3H
2204H= 22H
Result 22l0H= 20 + 22 = 42H
= 42H
1. LDA 2200H
2. MOV C, A :"Initialize counter"
3. MVI B, 00H :"sum = 0"
4. LXI H, 2201H :"Initialize pointer"

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6. ANI 0lH :"Mask Bit l to Bit7"
7. JNZ SKIP :"Don’t add if number is ODD"
8. MOV A, B :"Get the sum"
9. ADD M :"SUM = SUM + data"
10. MOV B, A :"Store result in B register"
11. SKIP: INX H :"increment pointer"
12. DCR C :"Decrement counter"
13. JNZ BACK :"if counter 0 repeat"
14. STA 2210H :"store sum"
Example-4. WAP to calculate the sum of series of odd numbers
Statement: Calculate the sum of series of odd numbers from the list of numbers. The length of the list is in
memory location 2200H and the series itself begins from memory location 2201H. Assume the sum to be
16-bit. Store the sum at memory locations 2300H and 2301H.
Sample problem
2200H = 4H
2201H= 9AH
2202H= 52H
2203H= 89H
2204H= 3FH
Result = 89H + 3FH = C8H
2300H= H Lower byte
2301H = H Higher byte 1.
Source program:
2. LDA 2200H
3. MOV C, A :"Initialize counter"
4. LXI H, 2201H :"Initialize pointer"
5. MVI E, 00 :"Sum low = 0"
6. MOV D, E :"Sum high = 0"
8. ANI 0lH :"Mask Bit 1 to Bit7"
9. JZ SKIP :"Don’t add if number is even"
10. MOV A, E :"Get the lower byte of sum"
11. ADD M :"Sum = sum + data"
12. MOV E, A :"Store result in E register"
13. JNC SKIP
14. INR D :"Add carry to MSB of SUM"
15. SKIP: INX H :"Increment pointer"
Example-5. WAP to find the square of given number.

26
Statement: Find the square of the given numbers from memory location 6100H and store the result from
memory location 7000H.
Sample problem
2200H = 4H
2201H= 9AH
2202H= 52H
2203H= 89H
2204H= 3FH
Result = 89H + 3FH = C8H
2300H= H Lower byte
2301H = H Higher byte
1. LXI H, 6200H :"Initialize lookup table pointer"
2. LXI D, 6100H :"Initialize source memory pointer"
3. LXI B, 7000H :"Initialize destination memory pointer"
4. BACK: LDAX D :"Get the number"
5. MOV L, A :"A point to the square"
6. MOV A, M :"Get the square"
7. STAX B :"Store the result at destination memory location"
8. INX D :"Increment source memory pointer"
9. INX B :"Increment destination memory pointer"
10. MOV A, C
11. CPI 05H :"Check for last number"
12. JNZ BACK :"If not repeat"
Example-6. WAP to search a byte in a given number
Statement: Search the given byte in the list of 50 numbers stored in the consecutive memory locations and
store the address of memory location in the memory locations 2200H and 2201H. Assume byte is in the C
register and starting address of the list is 2000H. If byte is not found store 00 at 2200H and 2201H.
1. LX I H, 2000H :"Initialize memory pointer 52H"
2. MVI B, 52H :"Initialize counter"
4. CMP C :"Compare with the given byte"
5. JZ LAST :"Go last if match occurs"
6. INX H :"Increment memory pointer"
7. DCR B :"Decrement counter"
8. JNZ B :"If not zero, repeat"
9. LXI H, 0000H
10. SHLD 2200H
11. JMP END :"Store 00 at 2200H and 2201H"
12. LAST: SHLD 2200H :"Store memory address"
13. END: HLT :"Stop"
Example-7. WAP to add two decimal numbers of 6 digit each.
Statement: Two decimal numbers six digits each, are stored in BCD package form. Each number occupies
a sequence of byte in the memory. The starting address of first number is 6000H. Write an assembly

27
language program that adds these two numbers and stores the sum in the same format starting from memory
location 6200H.
1. LXI H, 6000H :"Initialize pointer l to first number"
2. LXI D, 6l00H :"Initialize pointer2 to second number"
3. LXI B, 6200H :"Initialize pointer3 to result"
4. STC
5. CMC :"Carry = 0"
6. BACK: LDAX D :"Get the digit"
7. ADD M :"Add two digits"
8. DAA :"Adjust for decimal"
9. STAX.B :"Store the result"
10. INX H :"Increment pointer 1"
11. INX D :"Increment pointer2"
12. INX B :"Increment result pointer"
13. MOV A, L
14. CPI 06H :"Check for last digit"
15. JNZ BACK :"If not last digit repeat"
Example-8. WAP to separate even numbers from given numbers
Statement: Write an assembly language program to separate even numbers from the given list of 50
numbers and store them in another list starting from 2300H. Assume starting address of 50 number list is
2200H.
1. LXI H, 2200H :"Initialize memory pointer l"
2. LXI D, 2300H :"Initialize memory pointer2"
3. MVI C, 32H :"Initialize counter"
5. ANI 0lH :"Check for even number"
6. JNZ SKIP :"If ODD, don’t store"
7. MOV A, M :"Get the number"
8. STAX D :"Store the number in result list"
9. INX D :"Increment pointer 2" 10. SKIP: INX H :"Increment pointer l"
11. DCR C :"Decrement counter"
12. JNZ BACK :"If not zero, repeat"
13. HLT :"Stop
************************************************************************
** Text Books:
[T3] Ramesh Gaonkar, “Microprocessor Architecture, Programming and Applications with the 8085”, PHI
References Books:
[R4] Vaneet Singh, Gurmeet Singh, “Microprocessor and Interfacing”, Satya Prakashan, 2007.
References

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[1] R. Gaonkar, Microprocessor Architecture, Programming and Application with the 8085, vol.
6th, New York: PRI, 2015.
[2] "Timing diagram of 8085," [Online].
[3] G. S. Vaneet Singh, Microprocessor and Interfacing, Satya Prakashan, 2007.
GATE Based question
1. The following instruction have been executed by 8085 microprocessor. For which address will the
next instruction be fetched? [GATE 1997]
Address (HEX) Instruction
6010 LXI H, 8A79H
6013 MOV A, L
6015 ADD H
6016 DAA
6017 MOV H, A
6018 PCHL
a) 6019
b) 6379
c) 6979
d) None of these
2. An I/O processor control the flow of information between [GATE 1998]
a) Cache Memory and I/O devices
b) Main Memory and I/O devices
c) Two I/O devices
d) Cache and Main Memory
3. An Instruction used to set the carry flag in a computer can be classified as [GATE 1998] a)
Data transfer
b) Arithmetic
c) Logical
d) Program control
4. In the 8085 microprocessor, the RST6 instruction transfer the program execution to the following
location [GATE 2000]
a) 30H
b) 48H
c) 24H
d) 60H
5. The number of hardware interrupts (which require an external signal to interrupt) present in 8085
microprocessor are [GATE 2000]

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a) 1
b) 4
c) 5
d) 13
6. An 8085-microprocessor based system uses a 4K X 8-bit RAM whose starting address is AA00H.
The address of the last byte in this RAM is [GATE 2001]
a) 0FFFH
b) 1000H
c) B9FFH
d) BA00H
7. In an 8085 microprocessor the instruction CMP B has been executed will the content of the
accumulator is less than that of the register B. As a result [GATE 2003]
a) Carry flag will be set but zero flag will be reset
b) Carry flag will be reset but zero flag will be set
c) Both Carry flag and zero flag will be reset
d) Both Carry flag and zero flag will be set
8. The number of memory cycle required to execute the following 8085 instructions.
(i) LDA 3000H (ii) LXI D, F0F1H [GATE 2004] a) 2 for
(i) and 2 for(ii)
b) 4 for (i) and 3 for (ii)
c) 3 for (i) and 3 for(ii)
d) 3 for (i) and 4 for (ii)
9. In a microprocessor, the service routine for a certain interrupts start from a fixed location of memory
which cannot be externally set, but the interrupt can delayed or rejected. Such an
interrupts is [GATE 2009]
a) Non-maskable and non-vectored
b) Maskable and non-vectored
c) Non-maskable and vectored
d) Maskable and vectored
10. For 8085 microprocessor, the following program is executed
MVI A, 05H
MVI B, 05H
PTR: ADD B DCR
B
JNZ PTR
ADI 03H
HLT
At the end of the program, accumulator contains? [GATE 2013] a)
17H
b) 20H
c) 23H
d) 05H
11. The following instruction were executed on the 8085 microprocessor
MVI A, 33H
MVI B, 78H
ADD B
CMA
ANI 32H

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The accumulator value immediately after the execution of the fifth instruction is
[GATE 2017] a) 00H
b) 10H
c) 11
d) 32
Answer Key: 1) c 2) b 3) c 4) a 5) c 6) c 7) a 8) b 9) d
10) a 11) b
Question Bank based on 8085 microprocessor
1. What is a microcomputer?
2. What is the signal classification of 8085?
3. What are operations performed on data in 8085
4. How many interrupts does 8085 have, mention them
5. Basic concepts in memory interfacing
6. Define instruction cycle, machine cycle and T-state 7. What is an instruction?
8. Explain the function of ALE pin of 8085. [IPU Feb-2018]
9. How many machine cycles does 8085 have, mention them
10. Explain the signals HOLD, READY and SID
11. Explain LDA, STA and DAA instructions
12. What is the use of addressing modes, mention the different types?
13. Give the register organization of 8085
14. Define Flags
15. How does the microprocessor differentiate between data and instruction?
16. What is subroutine?
17. What are the difference between microcontroller and microprocessor?
18. What are the flags available in 8085 explain?
19. If the frequency of the crystal connected to 8085 is 6MHz calculate the time to fetch and execute
NOP instruction?
20. What is a T-state?
21. Define instruction cycle and machine cycle?
22. Explain the architecture of microprocessors 8085. [IPU Dec-2018] 23.
Explain the pin diagram of 8085.
24. What are the different programmable registers in 8085 microprocessors? Explain all.
[IPU June-2018] 25.
Explain the requirement of a program counter, stack pointer and status flags in the architecture of 8085
microprocessor.
26. Explain the memory mapped I/O addressing scheme.
27. Draw and explain the timing diagram of memory read cycle. [IPU June 2017]
28. Draw and explain the timing diagram of memory write cycle with example.
29. Draw and explain the timing diagram of opcode fetch cycle.
30. Explain the direct addressing modes and indirect addressing modes of 8085 with example.

31
31. Assume that the accumulator contents data bytes 88 hand instruction MOV C, A 4FH is fetched.
List the steps decoding and executing the instruction.
32. Draw the functional block diagram of 8085 microprocessor and explain.
33. Write a Program to Perform the following functions and verify the output steps:
a. Load the number 5CH in register D
b. Load the number 9E H in register C,
c. Increment the Contents of register C by one.
d. Add the contents of register C and D and Display the sum at output port1.
34. Write an assembly language program to find out the largest number from a given unordered array
of 8 bit numbers, stored in the locations starting from a known address.
35. Explain the various hardware and software interrupts of 8085 in details and also calculate the
vectored address of each interrupts. [IPU Dec-2016]
36. With suitable examples explain 8085 instruction set in detail.
37. Explain the different addressing modes of 8085 with an example of each. [IPU Feb-2017 ]
38. Explain 8085 Stack in detail.
39. Write a 8085 ALP to generate a accurate time delay of 100ms.
40. Write a program in 8085 to generate Fibonacci series. [IPU Dec-2018] 41.
Write 8085 assembly language program to SORT an array of 10 bytes in Descending order.
42. Write an 8085 ALP to perform 32 bit binary addition?
43. Explain the terms- maskable and non maskable interrupt. [IPU Feb-2017]
44. Write an 8085 ALP to convert the hexadecimal value to decimal value?

32
UNIT-II
2.1 Introduction to Microprocessor 8086
The main limitation of the 8-bit microprocessor were their low speed of execution, low memory addressing
capability, limited no of General purpose registers and less powerful instruction set. All these limitations
of the 8 bit microprocessors tempted the designers to go for more powerful processors in terms of advanced
architecture, more processing capability, larger memory addressing capability and a more powerful
instruction set. The 8086 was a result of such development design efforts.
In the family of 16-bit microprocessors, 16 bit microprocessor, Intel 8086 was the first one, launched in
1978. The introduction of 16-bit processor was a result of the increasing demand for more and more
powerful and high speed computational resources.
8086 Microprocessor Features:
1. It is 16-bit microprocessor
2. 16 bit ALU
3. It has a 16-bit data bus, so it can read data from or write data to memory and ports either 16-bit or 8-bit
at a time.
4. Maximum clock frequency is 5 MHz
5. It requires a single +5V power supply
6. It has 20 bit address bus and can access up to 220
memory locations (1 MB).
7. It can support up to 64K I/O ports
8. It provides 14, 16-bit registers
9. It has multiplexed address and data bus AD0-AD15 & A16-A19
10. It requires single phase clock with 33% duty cycle to provide internal timing.

33
11. Prefetches up to 6 instruction bytes from memory and queues them in order to speed up the processing.
12. 8086 supports 2 modes of operation
a) Minimum mode
b) Maximum mode
2.2 Architecture of 8086 microprocessor:
The complete architecture of 8086 as shown in fig 2.1 can be divided into two independent functional
parts
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)
Fig 2.1: Internal block diagram of 8086
The BIU performs all bus operations such as instruction fetching, reading and writing operands for
memory and calculating the addresses of the memory operands. The instruction bytes are transferred to
the instruction queue. EU executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution
mechanism which is called as Pipelining. This results in efficient use of the system bus and system
performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

34
1. Bus Interfacing Unit: It provides a full 16 bit bidirectional data bus and 20 bit address
bus. The bus interface unit is responsible for performing all external bus operations.
Specifically, it has the following functions:
➢ Instruction fetch Instruction queuing, Operand fetch and storage, Address relocation and
Bus control.
➢ The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.
➢ This queue permits prefetch of up to six bytes of instruction code. Whenever the queue
of the BIU is not full, it has room for at least two more bytes and at the same time the EU
is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction.
➢ These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
➢ After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.
➢ The EU accesses the queue from the output end. It reads one instruction byte after
the other from the output of the queue. If the queue is full and the EU is not requesting access
to operand in memory.
➢ These intervals of no bus activity, which may occur between bus cycles are known as Idle
state.
➢ If the BIU is already in the process of fetching an instruction when the EU request it to
read or write operands from memory or I/O, the BIU first completes the instruction fetch
bus cycle before initiating the operand read / write cycle.
➢ The BIU also contains a dedicated adder which is used to generate the 20 bit physical
address that is output on the address bus. This address is formed by adding an appended
16 bit segment address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current
contents of the instruction pointer IP register.
➢ The BIU is also responsible for generating bus control signals such as those for memory
read or write and I/O read or write.
2. Execution Unit: The Execution unit contains the register set of 8086 segment registers
and Instruction Pointer. It has a 16-bit ALU, able to perform the arithmetic and logical
operation. The execution unit may pass the results to the Bus interface unit for storing them
in memory.
➢ The Execution unit is responsible for decoding and executing all instructions.
➢ The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bus
cycles to memory or I/O and perform the operation specified by the instruction on the
operands.
➢ During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction.
➢ If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to
top of the queue.
➢ When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
➢ Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

35
Both units operate synchronously to give 8086 an overlapping instruction fetch and
instruction execution mechanism. This parallel processing of the BIU and EU eliminates
the time needed to fetch many of the instructions. This results in efficient use of the system
bus and significantly improve system performance.
2.3 Detailed Description of Block Diagram of 8086
(1) Address pins: It has 20 address pins A19-A16 and AD15-AD0
(2) Data Pins: It has 16 data pins AD15 to AD0. So, address and data pins are common or time shared.
(3) Register set of 8086: The register set of 8086 can be divided into four groups.
a. General Data Registers
b. Segment Registers
c. Pointers and Index Registers
d. Flag Register
Fig 2.2: Register organization of 8086
a. General Purpose Registers
➢ The registers AX, BX, CX and DX are the general purpose 16-bit registers.
➢ AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is
designated as AH. AL can be used as an 8-bit accumulator for 8-bit operation.
➢ All data register can be used as either 16 bit or 8 bit. BX is a 16-bit register, but BL indicates
the lower 8-bit of BX and BH indicates the higher 8-bit of BX.
➢ The register BX is used as offset storage for forming physical address in case of certain
addressing modes.
➢ The register CX is used default counter in case of string and loop instructions.
➢ DX register is a general purpose register which may be used as an implicit operand or destination
in case of a few instructions.
b. Segment Registers. There are 4 segment registers. They are:
o Code Segment Register (CS)
o Data Segment Register (DS)
o Extra Segment Register (ES)
o Stack Segment Register (SS)
➢ The 8086 architecture uses the concept of segmented memory. 8086 able to address a memory
capacity of 1 megabyte and it is byte organized. This 1megabyte memory is divided into 16 logical
segments. Each segment contains 64 kbytes of memory.

36
o Code segment register (CS): is used for addressing memory location in the code segment of the
memory, where the executable program is stored. CS is 16 bits wide. But we can imagine it to be
a 20 bit register where the least significant hex digit is 0H i.e., the least significant 4 bits are always
zero.
the segment register cannot start at locations where the LSB is not zero. The 16-bit contents of
segment register is called the segment offset/effective address.
o Data segment register (DS): points to the data segment of the memory where the data is stored.
The data segment holds the data, constant and work areas needed by the program. Where exactly
the data segment starts in the memory is indicated by the contents of the register called data
segment, DS Register.
o Extra Segment Register (ES): also refers to a segment in the memory which is another data
segment in the memory. The destination where the string will be moved must be in the another
segment called Extra Segment. Where exactly the extra segment starts in memory is indicated by
the contents of the register called ES Register, which is 16 bits wide. o Stack Segment Register
(SS): is used for addressing stack segment of the memory. The stack segment is that segment of
memory which is used to store stack data.
While addressing any location in the memory bank, the physical address is calculated from two
parts:
Physical address= segment address + offset address
The first is segment address, the segment registers contain 16-bit segment base addresses, related to
different segment. The second part is the offset value in that segment.
Index Registers: The index registers are used as general purpose registers as well as for offset
storage in case of indexed, base indexed and relative base indexed addressing modes. 8086
contains two index registers.
• Source index register (SI)
• Destination index register (DI)
The register SI is used to store the offset of source data in data segment. The register DI is used to
store the offset of destination in data or extra segment. The index registers are particularly useful
for string manipulation.
c. Pointer Registers: 8086 contains 3 pointer registers. They are
• Stack Pointer
• Base Pointer
• Instruction Pointer
The pointer register IP contains offset within the code segment. The pointer register BP contains
offset within the data segment. The pointer register SP contains offset within the stack segment.
(4) Arithmetic Logic Unit: ALU can perform various arithmetic and logical operations of 8 as well as 16
bit numbers.
(5) Flag Register: contains a group of status bits called flags that indicate the status of the CPU or the
result of arithmetic operations. There are two types of flags:
a) The status flags which reflect the result of executing an instruction. The programmer cannot
set/reset these flags directly.
b) The control flags enable or disable certain CPU operations. The programmer can set/reset these
bits to control the CPU's operation.

37
Fig 2.3: Flag Registers of 8086
Nine individual bits of the status register are used as control flags (3 of them) and status flags (6 of
them). The remaining 7 are not used. A flag can only take on the values 0 and 1. We say a flag is set
if it has the value 1. The status flags are used to record specific characteristics of arithmetic and of
logical instructions.
Fig 2.3: Flag Registers of 8086
• Control Flags: There are three control flags
The Direction Flag (D): Affects the direction of moving data blocks by such instructions as MOVS,
CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the STD (set D)
and CLD (clear D) instructions.
The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are actions
initiated by hardware block such as input devices that will interrupt the normal execution of
programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated
by the CLI (clear I) and STI (set I) instructions.
The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each
instruction. When this flag is set (i.e. = 1), the programmer can single step through his program to
debug any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3 instruction.
• Status Flags: There are six status flags
The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too large
to fit in the destination register. This happens when there is an end carry in an addition operation or
there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no carry.
The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too large
to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when adding two
numbers with the same sign (i.e. both positive or both negative). A value of 1 = overflow and 0 = no
overflow.

38
The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is negative.
This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means negative and 0 =
positive.
The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal to
zero. A value of 1 means the result is zero and a value of 0 means the result is not zero.
The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to bit 4
(or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry.
The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the number
of 1s is even its value = 1 and if the number of 1s is odd then its value = 0
(6) Instruction Queue (IQ) and Pipelining: These are 6 eight bit registers in the instruction queue of
8086. Initially the program is prepared using the instruction in form of mnemonics. Each mnemonic
is translated into hexadecimal codes and stored into successive memory location. Following steps
took place when microprocessor executes the programme:
1. Initially microprocessor will read, store six bytes of instruction codes in the six registers of
instruction queue. This is called prefetching.
2. For executing the instruction codes, microprocessor will read these codes from the registers of
instruction queue in FIFO sequence.
3. When two register of instruction queue becomes vacant, then in parallel with internal operation,
microprocessor will fetch two bytes of instruction codes in sequence and store these codes in
the vacant registers of instruction queue i.e. speed increases.
4. This method of prefetching instruction codes in advance in FIFO sequence is called as
pipelining.
5. If branching instruction comes in between, then all the six registers of instruction queue are
flushed or cleared to 000 H and the new instruction codes are read from new branching address.
Fig 2.4: Instruction Queue of 8086
2.4 Memory Segmentation
The memory in an 8086 based system is organized as segmented memory. The CPU 8086 is able to
access 1MB of physical memory. The complete 1MB of memory can be divided into 16 segments, each
of 64KB size and is addressed by one of the segment register. The 16-bit contents of the segment register
actually point to the starting location of a particular segment. The address of the segments may be
assigned as 0000H to F000h respectively. To address a specific memory location within a segment, we
need an offset address. The offset address values are from 0000H to FFFFH so that the physical addresses

39
range from 00000H to FFFFFH.The memory connected with 8086/8088 is divided into four memory
segments. Those memory segments will be maximum of 64K memory location. The 20 bit starting
memory location address of each memory segment is called as Base Address (BA) of the corresponding
memory segment. The 4 LSB’s of each base address should be always 0000 = 0 H and rest of the 16
MSB’s of Base address can be from 0000 H to FFFF H.
Fig 2.5: Memory Segmentation of 8086
Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum size can
go up to 64kilobytes. But if another segment starts along with this 64kilobytes location of
the first segment, then the two are said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its maximum size
can go up to 64kilobytes. But if another segment starts before this 64kilobytes location of
the first segment, then the two segments are said to be Non-Overlapped Segment.

40
Fig 2.6: Overlapping and Non-Overlapping segment
In the overlapping area locations physical address = CS1+IP1 = CS2+IP2. Where ‘+’
indicates
the procedure of physical address formation.
2.4.1 Method of Generating Physical Address:
Physical address = Segment address * 10H + Offset address.
PA = SBA * 10 + EA
=1400H*10+1200H=15200H
Ex: Segment address 1005H Offset address ----------5555H

41
Segment address ------- 1005H 0001 0000 0000 0101
Shifted left by 4 Positions 0001 0000 0000 0101 0000
+
Offset address --- 5555H ------ 0101 0101 0101 0101
Physical address ----155A5H 0001 0101 0101 1010 0101
2.5 Addressing Modes of 8086
Addressing mode indicates a way of locating data or operands. The addressing modes describe the
types of operands and the way they are accessed for executing an instruction. According to the flow
of instruction execution, the instructions may be categorized as
1. Sequential control flow instructions
2. Control transfer instructions

42
1) Sequential control flow instructions are the instructions, which after execution, transfer
control to the next instruction appearing immediately after it (in the sequence) in the program.
For example, the arithmetic, logic, data transfer and processor control instructions are sequential
control flow instructions.
2) The control transfer instructions, on the other hand, transfer control to some predefined
address or the address somehow specified in the instruction, after their execution. For example,
INT, CALL, RET and JUMP instructions fall under this category. The addressing modes for
sequential control transfer instructions are:
a) Immediate: In this type of addressing, immediate data is a part of instruction and appears in
the form of successive byte or bytes.
Ex: MOV AX, 0005H
In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit
in size.
b) Direct: In the direct addressing mode a 16-bit memory address (offset) is directly specified in
the instruction as a part of it.
Ex: MOV AX, [5000H]
Here, data resides in a memory location in the data segment, whose effective address may be
completed using 5000H as the offset address and content of DS as segment address. The
effective address here, is 10H * DS + 5000H.
c) Register: In register addressing mode, the data is stored in a register and is referred using the
particular register. All the registers, except IP, may be used in this mode.
Ex: MOV BX, AX
d) Register Indirect: Sometimes, the address of the memory location, which contains data or
operand, is determined in an indirect way, using the offset register. This mode of addressing is
known as register indirect mode. In this addressing mode, the offset address of data is in either
BX or SI or DI register. The default segment is either DS or ES. The data is supposed to be
available at the address pointed to by the content of any of the above registers in the default
data segment.
Ex: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address is in BX. The effective
address of the data is given as 10H * DS+[BX].
e) Indexed: In this addressing mode, offset of the operand is stored in one of the index registers.
DS and ES are the default segments for index registers, SI and DI respectively. This is a special
case of register indirect addressing mode.
Ex: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS. The effective address, in this case,
is computed as 10*DS+[SI].
f) Register Relative: In this addressing mode, the data is available at an effective address formed
by adding an 8-bit or 16-bit displacement with the content of any one of the registers

43
BX, BP, SI and DI in the default (either DS or ES) segment. Ex:
MOV AX, 50H[BX]
Here, the effective address is given as 10H *DS+50H+[BX]
g) Based Indexed: The effective address of data is formed, in this addressing mode, by adding
content of a base register (any one of BX or BP) to the content of an index register (any one of
SI or DI). The default segment register may be ES or DS.
Ex: MOV AX, [BX][SI]
Here, BX is the base register and SI is the index register the effective address is computed as
10H * DS + [BX] + [SI].
h) Relative Based Indexed: The effective address is formed by adding an 8 or 16-bit displacement
with the sum of the contents of any one of the base register (BX or BP) and any one of the index
register, in a default segment.
Ex: MOV AX, 50H [BX] [SI]
Here, 50H is an immediate displacement, BX is base register and SI is an index register the
effective address of data is computed as
10H * DS + [BX] + [SI] + 50H
For control transfer instructions, the addressing modes depend upon whether the destination is
within the same segment or different one. It also depends upon the method of passing the destination
address to the processor.
Basically, there are two addressing modes for the control transfer instructions,
• intersegment addressing and
• intrasegment addressing modes.
If the location to which the control is to be transferred lies in a different segment other than the
current one, the mode is called intersegment mode.
If the destination location lies in the same segment, the mode is called intrasegment mode.

44
Fig 2.7: Addressing modes for control transfer instructions
I. Intrasegment Direct Mode: In this mode, the address to which the control is to be transferred
lies in the same segment in which the control transfer instruction lies and appears directly in
the instruction as an immediate displacement value. In this addressing mode, the displacement
is computed relative to the content of the instruction pointer IP.
The effective address to which the control will be transferred is given by the sum of 8 or 16-bit
displacement and current content of IP. In the case of jump instruction, if the signed
displacement (d) is of 8-bits (i.e –128<d<+128) we term it as short jump and if it is of 16-bits
(i.e-32, 768<d<+32,768) it is termed as long jump.
II. Intrasegment Indirect Mode: In this mode, the displacement to which the control is to be
transferred, is in the same segment in which the control transfer instruction lies, but it is passed
to the instruction indirectly. Here, the branch address is found as the content of a register or a
memory location. This addressing mode may be used in unconditional branch instructions.
III. Intersegment Direct: In this mode, the address to which the control is to be transferred is in a
different segment. This addressing mode provides a means of branching from one code
segment to another code segment. Here, the CS and IP of the destination address are specified
directly in the instruction.
IV. Intersegment Indirect: In this mode, the address to which the control is to be transferred lies
in a different segment and it is passed to the instruction indirectly, i.e contents of a memory
block containing four bytes, i.e IP (LSB), IP(MSB), CS(LSB) and CS (MSB) sequentially. The
starting address of the memory block may be referred using any of the addressing modes,
except immediate mode.
Forming the effective Addresses:
The following examples explain forming of the effective addresses in various modes
Ex: 1. The contents of different registers are given below. Form effective addresses for different
addressing modes.
Offset (displacement)=5000H
[AX]-1000H, [BX]- 2000H, [SI]-3000H, [DI]-4000H, [BP]-5000H, [SP]-6000H, [CS]-0000H,
[DS]-1000H, [SS]-2000H, [IP]-7000H
Shifting segment address four bits to the left is equivalent to multiplying it by 16D or 10H
Direct addressing mode:

45
MOV AX, [5000H]
DS: OFFSET ↔ 1000H: 5000H
10H*DS ↔10000—segment address
offset ↔ +5000------offset address
15000H – Effective address
Register indirect:
MOV AX, [BX]
DS: BX ↔ 1000H: 2000H 10H*DS
↔ 10000—segment address
[BX] +2000---offset address
Register relative:
MOV AX, 5000 [BX]
DS: [5000+BX]
10H*DS ↔10000
offset ↔ +5000
[BX] +2000
Based indexed:
MOV AX, [BX] [SI]
DS: [BX + SI]
10H*DS ↔ 10000
[BX] ↔ +2000

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[SI] ↔ +3000
Relative based index:
MOV AX, 5000[BX][SI]
DS: [BX+SI+5000]
10H*DS ↔ 10000
[BX] ↔ +2000
[SI] ↔ +3000
+5000
1A000H – Effective address
2.6 8086 Pin Diagram
2.6.1 Signal description of 8086:
➢ The 8086 is a 16-bit microprocessor. This microprocessor operates in single processor or
multiprocessor configurations to achieve high performance.
➢ The pin configuration of 8086 is shown in the figure. Some of the pins serve a particular function in
minimum mode (single processor mode) and others function in maximum mode (multiprocessor
mode).
The 8086 signals are categorized into 3 types:
➢ Common signals for both minimum mode and maximum mode.
➢ Special signals which are meant only for minimum mode
➢ Special signals which are meant only for maximum mode

47
Fig 2.8: Pin diagram of 8086 ➢
The following signal descriptions are common for both modes.
▪ AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address
remains on the lines during T1 state, while the data is available on the data bus during T2, T3,
Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and
local bus hold acknowledge cycles.
▪ A19/S6, A18/S5, A17/S4, and A16/S3: These are the time multiplexed address and status
lines. o During T1 these are the most significant address lines for memory operations. o
During I/O operations, these lines are low. o During memory or I/O operations, status
information is available on those lines for T2, T3, Tw and T4.
o The status of the interrupt enable flag bit is updated at the beginning of each clock
cycle.
o The S4 and S3 combine indicate which segment registers is presently being used for
memory accesses as in below fig
o These lines float to tri-state off during the local bus hold acknowledge. The status
line S6 is always low.
o The address bit is separated from the status bit using latches controlled by the ALE
signal.

48
Fig 2.9: Memory Read and Write cycle
▪ BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order
(D15D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used
to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for
read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher
byte of data bus. The status information is available during T2, T3 and T4. The signal is active
low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge
cycle
▪ RD – Read: This signal on low indicates the peripheral that the processor is performing
memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read
cycle. The signal remains tristated during the hold acknowledge

49
▪ READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. the signal is active high.
▪ INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles
of each instruction to determine the availability of the request. If any interrupt request is
pending, the processor enters the interrupt acknowledge cycle. This can be internally masked
by resulting the interrupt enable flag. This signal is active high and internally synchronized.
▪ TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution
will continue, else the processor remains in an idle state. The input is synchronized internally
during each clock cycle on leading edge of clock.
▪ CLK- Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. It’s an asymmetric square wave with 33% duty cycle. Figure shows the Pin
functions of 8086.
Fig 2.10: Signal Groups of 8086
The following pin functions are for the minimum mode operation of 8086
▪ M/IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When
it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that
the CPU is having a memory operation. This line becomes active high in the previous T4 and
remains active till final T4 of the current cycle. It is tristated during local bus “hold
acknowledge “.
▪ INTA – Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge
cycles. i.e. when it goes low, the processor has accepted the interrupt.
▪ ALE – Address Latch Enable: This output signal indicates the availability of the valid address
on the address/data lines and is connected to latch enable input of latches. This signal is active
high and is never tristated.

50
▪ DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow
through the transceivers (bidirectional buffers). When the processor sends out data, this signal
is high and when the processor is receiving data, this signal is low.
▪ DEN – Data Enable: This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This
is tristated during ‘hold acknowledge’ cycle.
▪ HOLD, HLDA- Acknowledge: When the HOLD line goes high; it indicates to the processor
that another master is requesting the bus access. The processor, after receiving the HOLD
request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle
after completing the current bus cycle.
At the same time, the processor floats the local bus and control lines. When the processor detects
the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be
externally synchronized. If the DMA request is made while the CPU is performing a memory or
I/O cycle, it will release the local bus during T4 provided :
1. The request occurs on or before T2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word.
3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.
The following pin functions are applicable for maximum mode operation of 8086.
▪ S2, S1, and S0 – Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor. These become activity during T4 of the previous cycle and
active during T1 and T2 of the current bus cycles.
▪ LOCK: This output pin indicates that other system bus master will be prevented from gaining
the system bus, while the LOCK signal is low. The LOCK signal is activated by the ‘LOCK’
prefix instruction and remains active until the completion of the next instruction. When the CPU
is executing a critical instruction which requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the system will not gain the control of the bus.
The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may
be connected to an external bus controller. By prefetching the instruction, there is a considerable
speeding up in instruction execution in 8086. This is known as instruction pipelining.
Fig 2.11: Maximum mode of operation 0f 8086

51
➢ At the starting the CS: IP is loaded with the required address from which the execution is to be
started. Initially, the queue will be empty and the microprocessor starts a fetch operation to
bring one byte (the first byte) of instruction code, if the CS: IP address is odd or two bytes at a
time, if the CS: IP address is even.
➢ The first byte is a complete opcode in case of some instruction (one byte opcode instruction)
and is a part of opcode, in case of some instructions (two byte opcode instructions), the
remaining part of code lie in second byte.
➢ The second byte is then decoded in continuation with the first byte to decide the instruction
length and the number of subsequent bytes to be treated as instruction data. The queue is
updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at
least two bytes of the queue are empty and the EU may be concurrently executing the fetched
instructions.
➢ The next byte after the instruction is completed is again the first opcode byte of the next
instruction. A similar procedure is repeated till the complete execution of the program. The
fetch operation of the next instruction is overlapped with the execution of the current
instruction. As in the architecture, there are two separate units, namely Execution unit and Bus
interface unit.
➢ While the execution unit is busy in executing an instruction, after it is completely decoded, the
bus interface unit may be fetching the bytes of the next instruction from memory, depending
upon the queue status.
Fig
2.12: Status flag of 8086
▪ RQ/GT0, RQ/GT1 – Request/Grant: These pins are used by the other local bus master in
maximum mode, to force the processor to release the local bus at the end of the processor current
bus cycle.
Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins
have internal pull-up resistors and may be left unconnected. Request/Grant sequence is as
follows:
1. A pulse of one clock wide from another bus master requests the bus access to 8086.
2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it will
enter the ‘hold acknowledge’ state at next cycle. The CPU bus interface unit is likely to be
disconnected from the local bus of the system.
3. A one clock wide pulse from another master indicates to the 8086 that the hold request is
about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus
each master to master exchange of the local bus is a sequence of 3 pulses. There must be
at least one dead clock cycle after each bus exchange. The request and grant pulses are
active low. For the bus request those are received while 8086 is performing memory or I/O

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