This document discusses the challenges of verifying mixed-signal integrated circuits. It presents how Freescale used Cadence eManager and a variety of modeling and simulation techniques to verify a sensor IC. They took a progressive approach starting with digital simulations using wreal models for speed and then incorporating more accurate Verilog-AMS and transistor-level models. They were able to set up a single simulation environment in eManager to run analog, digital and mixed-signal simulations. The document discusses using control-oriented and data-oriented functional coverage to ensure the chip's functionality was verified.
Dec ''too simple'' digital electronics demystified (mc grawChethan Nt
This document is the table of contents for the book "Digital Electronics Demystified" by Myke Predko. It lists 12 chapters that make up the book, divided into two parts - an introduction to digital electronics and digital electronics applications. The chapters cover topics such as boolean logic, number systems, combinational and sequential logic circuits, oscillators, counters, interfaces, and computer processors.
The document provides information about the Linear Systems and Signals Laboratory course conducted at the National Institute of Technology Karnataka, Surathkal. It contains two modules - Circuit Simulation using PSPICE and Simulation using MATLAB/SIMULINK. The objectives of the course are to introduce circuit analysis using PSPICE and modeling/simulation of signals and systems using MATLAB and SIMULINK. The document describes the evaluation plan and weekly schedule of the course.
1) Digital to analog converters (DACs) convert digital input signals into analog output signals. Common DAC circuit types include weighted resistor DACs, R-2R ladder DACs, switched current-source DACs, and switched-capacitor DACs.
2) R-2R ladder DACs use only two resistor values (R and 2R) which makes them easy to manufacture with less errors compared to weighted resistor DACs.
3) DAC resolution refers to the fineness of output voltage changes for each change in the least significant bit of the digital input. Higher resolution DACs allow for finer detail in the approximated analog output signal
The document discusses programming microcontrollers for embedded systems. It provides examples of interfacing multiple switches to a single pin of a microcontroller and configuring the microcontroller's analog-to-digital converter (ADC). The examples demonstrate starting and stopping the ADC, reading ADC values, and setting the ADC prescaler and reference voltages. Practical programming techniques are presented for reading sensor inputs using the ADC to acquire data from the real world.
Parallel/flash ADCs use a voltage ladder and comparators to convert an analog input to a thermometer code. They can achieve sampling rates over 1GHz but require 2N-1 comparators. Interpolating and averaging ADCs reduce comparator count by interpolating between ladder voltages and averaging comparator outputs. Folding ADCs further reduce comparator count by mapping the input range onto a smaller set of subranges. Time-interleaved ADCs achieve high speeds by parallelizing conversions across multiple ADCs.
This document describes a lab report on modeling in SPICE. It includes:
1) Testing the validity of an NMOS transistor model by comparing hand calculations of drain currents to SPICE simulation results.
2) Finding accurate MOSFET model parameters by matching measured data to equations and simulations.
3) Evaluating a CMOS inverter model in SPICE by analyzing its digital characteristics.
4) Comparing CMOS and BJT TTL inverter models in SPICE to determine modeling usefulness.
This document discusses different types of analog-to-digital converters (ADCs). It describes counter type ADCs, successive approximation ADCs, and flash ADCs. It also discusses cascaded ADC architectures that can reduce hardware complexity for high resolution converters. Cascaded designs combine coarse and fine quantization stages to lower component count compared to single-stage flash ADCs. The optimal cascaded design trades off conversion time and hardware cost.
This document summarizes the features and specifications of the AT24C512B 512K serial EEPROM chip. Key points include:
- The chip provides 524,288 bits of serial EEPROM organized as 65,536 words of 8 bits each.
- It uses a two-wire serial interface for communication and supports both 1.8V and 2.5V voltage operation.
- Features include page write mode, self-timed write cycles, high endurance of 1 million write cycles, and data retention of 40 years.
- The chip comes in various package types including 8-pin PDIP, 8-lead SOIC, 8-ball dBGA2, and 8-lead
Dec ''too simple'' digital electronics demystified (mc grawChethan Nt
This document is the table of contents for the book "Digital Electronics Demystified" by Myke Predko. It lists 12 chapters that make up the book, divided into two parts - an introduction to digital electronics and digital electronics applications. The chapters cover topics such as boolean logic, number systems, combinational and sequential logic circuits, oscillators, counters, interfaces, and computer processors.
The document provides information about the Linear Systems and Signals Laboratory course conducted at the National Institute of Technology Karnataka, Surathkal. It contains two modules - Circuit Simulation using PSPICE and Simulation using MATLAB/SIMULINK. The objectives of the course are to introduce circuit analysis using PSPICE and modeling/simulation of signals and systems using MATLAB and SIMULINK. The document describes the evaluation plan and weekly schedule of the course.
1) Digital to analog converters (DACs) convert digital input signals into analog output signals. Common DAC circuit types include weighted resistor DACs, R-2R ladder DACs, switched current-source DACs, and switched-capacitor DACs.
2) R-2R ladder DACs use only two resistor values (R and 2R) which makes them easy to manufacture with less errors compared to weighted resistor DACs.
3) DAC resolution refers to the fineness of output voltage changes for each change in the least significant bit of the digital input. Higher resolution DACs allow for finer detail in the approximated analog output signal
The document discusses programming microcontrollers for embedded systems. It provides examples of interfacing multiple switches to a single pin of a microcontroller and configuring the microcontroller's analog-to-digital converter (ADC). The examples demonstrate starting and stopping the ADC, reading ADC values, and setting the ADC prescaler and reference voltages. Practical programming techniques are presented for reading sensor inputs using the ADC to acquire data from the real world.
Parallel/flash ADCs use a voltage ladder and comparators to convert an analog input to a thermometer code. They can achieve sampling rates over 1GHz but require 2N-1 comparators. Interpolating and averaging ADCs reduce comparator count by interpolating between ladder voltages and averaging comparator outputs. Folding ADCs further reduce comparator count by mapping the input range onto a smaller set of subranges. Time-interleaved ADCs achieve high speeds by parallelizing conversions across multiple ADCs.
This document describes a lab report on modeling in SPICE. It includes:
1) Testing the validity of an NMOS transistor model by comparing hand calculations of drain currents to SPICE simulation results.
2) Finding accurate MOSFET model parameters by matching measured data to equations and simulations.
3) Evaluating a CMOS inverter model in SPICE by analyzing its digital characteristics.
4) Comparing CMOS and BJT TTL inverter models in SPICE to determine modeling usefulness.
This document discusses different types of analog-to-digital converters (ADCs). It describes counter type ADCs, successive approximation ADCs, and flash ADCs. It also discusses cascaded ADC architectures that can reduce hardware complexity for high resolution converters. Cascaded designs combine coarse and fine quantization stages to lower component count compared to single-stage flash ADCs. The optimal cascaded design trades off conversion time and hardware cost.
This document summarizes the features and specifications of the AT24C512B 512K serial EEPROM chip. Key points include:
- The chip provides 524,288 bits of serial EEPROM organized as 65,536 words of 8 bits each.
- It uses a two-wire serial interface for communication and supports both 1.8V and 2.5V voltage operation.
- Features include page write mode, self-timed write cycles, high endurance of 1 million write cycles, and data retention of 40 years.
- The chip comes in various package types including 8-pin PDIP, 8-lead SOIC, 8-ball dBGA2, and 8-lead
This document provides the course plan and evaluation plan for the Linear Systems & Signals Lab course (EC216). The course is a 3 credit lab course with 0-0-3 teaching hours. The objective is to introduce PSPICE and MATLAB for circuit analysis and modeling/simulating signals and systems. Students will be evaluated continuously (30%) and through two tests - Test 1 on PSPICE (30%) and Test 2 on MATLAB/SIMULINK (40%). The course has two modules, the first focusing on PSPICE over 5 weeks and the second on MATLAB/SIMULINK over 7 weeks, with tests in weeks 6 and 12.
This document describes a 10-bit 165MSPS video ADC. It uses a time-interleaved SAR architecture with multiple low-power SAR ADCs operating in parallel to achieve the high sampling rate. Each SAR ADC samples every nth cycle, resulting in an effective sampling rate that is n times higher than an individual ADC. The design achieves low power consumption and area through its digital nature and use of scaled CMOS technology. It provides offset correction through a calibration technique to improve accuracy for video applications.
- Digital signal processing and its applications involve converting analog signals to digital signals using analog-to-digital conversion and processing digital signals using techniques like sampling.
- Sampling involves taking discrete measurements of a continuous signal at regular time intervals. The sampling rate must be at least twice the highest frequency of the original signal to avoid aliasing.
- Sample and hold circuits sample an analog input signal by connecting it to a capacitor, then hold the sampled value by disconnecting the capacitor, allowing time for analog-to-digital conversion without changes in the input affecting the held value.
Report-Implementation of Quantum Gates using VerilogShashank Kumar
It was a project-based work in which I was guided to implement the quantum-based gates which would be equivalent to classical gates So, the project name was "FPGA Implementation of Digital Logic Design using Quantum Computing". Actually, it is to mitigate the problem, since in quantum any NAND based circuit is not shown universal as in the classical it was so tried by using the "IBM Quantum Composer" to make such circuit which would behave as the NAND gate and also reversible in nature as per the quantum physics says and simulated the circuitry using the "Verilog".
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
Implementation of quantum gates using verilogShashank Kumar
Implementing the XOR, AND, OR gate in the quantum circuits and with the help of IBM Quantum Composer which is a graphical programming tool. Also utilizing the Quantum circuit as well as HDL i.e., Verilog by Xilinx ISE Design Suite version 14.7 for visualizing the simulation graph with implementing the XOR, AND, OR and NAND gates also actually NAND gate is not found the universal gate in quantum, so trying to build the NAND gate which can also perform the reversible nature with simulating using the Verilog code for the desired result i.e. NAND output.
The document describes several types of analog-to-digital converters (ADCs): dual slope, flash, successive approximation, and sigma-delta. It explains the basic functioning of each type, including their key components and steps in the conversion process. For each ADC type, it provides a brief summary of their pros and cons in terms of speed, accuracy, cost, and resolution. The document serves to introduce the fundamental concepts and tradeoffs of different ADC architectures.
This document summarizes the design of a 3-bit pipeline analog-to-digital converter (ADC) using 0.18 micrometer CMOS technology. Key aspects discussed include the design of individual circuit blocks like latches, comparators, and op-amps. Simulation results show the ADC operates at a sampling rate of 80 MHz with low power consumption compared to other architectures. The pipeline architecture achieves high sampling speeds while maintaining relatively low power.
To study the relay operation from digital control signal using LabVIEW.Ankita Tiwari
The document describes an experiment to control a relay using LabVIEW and an Arduino board. The apparatus used includes an Arduino board, a relay, and the LabVIEW software environment. It then provides background on LabVIEW and how it can be used for graphical programming and interfacing with hardware. It also describes how the ULN2803 relay driver IC works to interface low-voltage logic signals from the Arduino with the higher voltages needed for relay control. The experiment checks for new values from LabVIEW and uses those to calculate and set the motor speed, sending the results to another serial port to confirm the code is working properly.
This document describes the design of a 4-bit flash analog-to-digital converter (ADC). It first discusses basic concepts of ADCs including input voltage range, resolution, quantization, and conversion modes. It then presents the design requirements and theoretical design of the key components, including a flash converter, voltage reference, comparators, and binary encoder. The document concludes by showing the real design, stimulation results, and comments on the design's performance at different input voltages and temperatures.
DOWNLOAD HERE: https://goo.gl/f2F7X5
Near Space Arduino Course is an open course where different aspects concerning electronics in near space environments are explained, with real experiences and exercises.
Contents:
Generalities about arduino
Battery dimensioning
BMP180
Relay
Bluetooth coms
Types of comms
GPS sentences and filtering
Iridium communication
Simulation of 3 bit Flash ADC in 0.18μmTechnology using NG SPICE Tool for Hig...ijsrd.com
This paper provides the basic simulation result for the 3 bit flash type ADC in 0.18μm technology using the NG Spice device simulator tool. It includes two stages, first stage includes 7 comparators and second stage has a thermometer encoder. The simulation is done in NG spice tool developed by university of California at Berkeley (USA).The response time of the comparator and ADC are 3.7ns and 4.9ns respectively with 50.01μw power dissipation which makes the ADC more suitable for high speed application with lower power devices.
Karthik Koneru is seeking an entry-level position in analog and mixed-signal design/verification starting in May 2015. He has a Master's degree in Electrical Engineering from Arizona State University and experience designing circuits including op-amps, voltage references, PLLs, ADCs, and LDO voltage regulators. His skills include Verilog, Cadence tools, and he has experience with projects involving PLL, sigma-delta modulator, and pipelined ADC design.
The document discusses successive approximation analog-to-digital converters (ADCs). It outlines the converter type, provides an example of how successive approximation works using a 10-bit resolution, and discusses literature comparing published ADC designs. It also summarizes the market for ADC ICs, listing major manufacturers and comparing features of Texas Instruments' 6-channel SAR ADCs.
Analog & Digital Integrated Circuits (Question Bank)Mathankumar S
This document contains question banks for the subject Analog & Digital Integrated Circuits. It is divided into 5 units covering topics such as operational amplifiers, phase locked loops, ADCs and DACs, Boolean algebra, combinational logic circuits, sequential logic circuits and flip-flops. The question bank contains objective type questions to test knowledge as well as longer questions requiring explanations and circuit design to test comprehension. It aims to provide a comprehensive set of practice questions covering the key concepts of the subject.
Design and Simulation of 4-bit DAC Decoder Using Custom Designerijsrd.com
Digital to Analog Converter (DAC), are the most complex structures and having digital input and analog output, it is found in almost all Analog and Mixed Signal Design today. There are different types of DACs currently on the market. The goal of this paper is to implement 4-bit Resistor String D/A converter using 4-bit AND gate and 4-to-16 Decoder with the help of 4 numbers Inverter. Binary (digital) coded 4-bit data was input to the converter. The data converter will convert all 4-bit binary coded data into correspondent different level of "staircase" voltage.
This document provides information about analog to digital conversion and digital to analog conversion. It discusses different types of converters including flash ADCs, successive approximation ADCs, dual slope ADCs, R-2R ladder DACs, and weighted resistor DACs. It also covers analog and digital signals, the conversion processes, and applications of ADCs and DACs in areas like data acquisition and fiber optic communication.
The MC13783 is an integrated circuit that provides power management and audio functionality for portable devices. It includes a battery charger, voltage regulators, audio codecs, amplifiers, and other features to support full device functionality while optimizing system size and bill of materials. Key features include power management, a 13-bit voice codec, stereo recording and playback, and a processor interface. The document describes the various blocks and features implemented on the MC13783 chip.
This document describes a technique called "multi-supply digital layout" that allows reliable back-annotation between digital blocks powered by different voltage supplies. It presents a design flow that uses standard CAD tools from RTL to layout. Digital blocks are grouped into voltage regions separated by isolation rings. Level shifter cells are used for voltage conversion at region interfaces. Libraries are generated for level shifters to integrate them into the digital flow for synthesis, simulation, and test. Floorplanning scripts automate placement of cells into the appropriate voltage regions.
Re usable continuous-time analog sva assertionsRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
Verification Of 1 M+ Transistors Mixed Signal IcRégis SANTONJA
This document discusses verification techniques for a mixed-signal integrated circuit containing over 1 million transistors used in cellular and multimedia applications. It describes creating block-level testbenches first before integrating them into a chip-level testbench. Verification goals have expanded from just functional verification to also consider signal integrity and power consumption to avoid issues during fabrication. A verification matrix is used to ensure all specification aspects are tested through simulation before production.
This document provides the course plan and evaluation plan for the Linear Systems & Signals Lab course (EC216). The course is a 3 credit lab course with 0-0-3 teaching hours. The objective is to introduce PSPICE and MATLAB for circuit analysis and modeling/simulating signals and systems. Students will be evaluated continuously (30%) and through two tests - Test 1 on PSPICE (30%) and Test 2 on MATLAB/SIMULINK (40%). The course has two modules, the first focusing on PSPICE over 5 weeks and the second on MATLAB/SIMULINK over 7 weeks, with tests in weeks 6 and 12.
This document describes a 10-bit 165MSPS video ADC. It uses a time-interleaved SAR architecture with multiple low-power SAR ADCs operating in parallel to achieve the high sampling rate. Each SAR ADC samples every nth cycle, resulting in an effective sampling rate that is n times higher than an individual ADC. The design achieves low power consumption and area through its digital nature and use of scaled CMOS technology. It provides offset correction through a calibration technique to improve accuracy for video applications.
- Digital signal processing and its applications involve converting analog signals to digital signals using analog-to-digital conversion and processing digital signals using techniques like sampling.
- Sampling involves taking discrete measurements of a continuous signal at regular time intervals. The sampling rate must be at least twice the highest frequency of the original signal to avoid aliasing.
- Sample and hold circuits sample an analog input signal by connecting it to a capacitor, then hold the sampled value by disconnecting the capacitor, allowing time for analog-to-digital conversion without changes in the input affecting the held value.
Report-Implementation of Quantum Gates using VerilogShashank Kumar
It was a project-based work in which I was guided to implement the quantum-based gates which would be equivalent to classical gates So, the project name was "FPGA Implementation of Digital Logic Design using Quantum Computing". Actually, it is to mitigate the problem, since in quantum any NAND based circuit is not shown universal as in the classical it was so tried by using the "IBM Quantum Composer" to make such circuit which would behave as the NAND gate and also reversible in nature as per the quantum physics says and simulated the circuitry using the "Verilog".
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
Implementation of quantum gates using verilogShashank Kumar
Implementing the XOR, AND, OR gate in the quantum circuits and with the help of IBM Quantum Composer which is a graphical programming tool. Also utilizing the Quantum circuit as well as HDL i.e., Verilog by Xilinx ISE Design Suite version 14.7 for visualizing the simulation graph with implementing the XOR, AND, OR and NAND gates also actually NAND gate is not found the universal gate in quantum, so trying to build the NAND gate which can also perform the reversible nature with simulating using the Verilog code for the desired result i.e. NAND output.
The document describes several types of analog-to-digital converters (ADCs): dual slope, flash, successive approximation, and sigma-delta. It explains the basic functioning of each type, including their key components and steps in the conversion process. For each ADC type, it provides a brief summary of their pros and cons in terms of speed, accuracy, cost, and resolution. The document serves to introduce the fundamental concepts and tradeoffs of different ADC architectures.
This document summarizes the design of a 3-bit pipeline analog-to-digital converter (ADC) using 0.18 micrometer CMOS technology. Key aspects discussed include the design of individual circuit blocks like latches, comparators, and op-amps. Simulation results show the ADC operates at a sampling rate of 80 MHz with low power consumption compared to other architectures. The pipeline architecture achieves high sampling speeds while maintaining relatively low power.
To study the relay operation from digital control signal using LabVIEW.Ankita Tiwari
The document describes an experiment to control a relay using LabVIEW and an Arduino board. The apparatus used includes an Arduino board, a relay, and the LabVIEW software environment. It then provides background on LabVIEW and how it can be used for graphical programming and interfacing with hardware. It also describes how the ULN2803 relay driver IC works to interface low-voltage logic signals from the Arduino with the higher voltages needed for relay control. The experiment checks for new values from LabVIEW and uses those to calculate and set the motor speed, sending the results to another serial port to confirm the code is working properly.
This document describes the design of a 4-bit flash analog-to-digital converter (ADC). It first discusses basic concepts of ADCs including input voltage range, resolution, quantization, and conversion modes. It then presents the design requirements and theoretical design of the key components, including a flash converter, voltage reference, comparators, and binary encoder. The document concludes by showing the real design, stimulation results, and comments on the design's performance at different input voltages and temperatures.
DOWNLOAD HERE: https://goo.gl/f2F7X5
Near Space Arduino Course is an open course where different aspects concerning electronics in near space environments are explained, with real experiences and exercises.
Contents:
Generalities about arduino
Battery dimensioning
BMP180
Relay
Bluetooth coms
Types of comms
GPS sentences and filtering
Iridium communication
Simulation of 3 bit Flash ADC in 0.18μmTechnology using NG SPICE Tool for Hig...ijsrd.com
This paper provides the basic simulation result for the 3 bit flash type ADC in 0.18μm technology using the NG Spice device simulator tool. It includes two stages, first stage includes 7 comparators and second stage has a thermometer encoder. The simulation is done in NG spice tool developed by university of California at Berkeley (USA).The response time of the comparator and ADC are 3.7ns and 4.9ns respectively with 50.01μw power dissipation which makes the ADC more suitable for high speed application with lower power devices.
Karthik Koneru is seeking an entry-level position in analog and mixed-signal design/verification starting in May 2015. He has a Master's degree in Electrical Engineering from Arizona State University and experience designing circuits including op-amps, voltage references, PLLs, ADCs, and LDO voltage regulators. His skills include Verilog, Cadence tools, and he has experience with projects involving PLL, sigma-delta modulator, and pipelined ADC design.
The document discusses successive approximation analog-to-digital converters (ADCs). It outlines the converter type, provides an example of how successive approximation works using a 10-bit resolution, and discusses literature comparing published ADC designs. It also summarizes the market for ADC ICs, listing major manufacturers and comparing features of Texas Instruments' 6-channel SAR ADCs.
Analog & Digital Integrated Circuits (Question Bank)Mathankumar S
This document contains question banks for the subject Analog & Digital Integrated Circuits. It is divided into 5 units covering topics such as operational amplifiers, phase locked loops, ADCs and DACs, Boolean algebra, combinational logic circuits, sequential logic circuits and flip-flops. The question bank contains objective type questions to test knowledge as well as longer questions requiring explanations and circuit design to test comprehension. It aims to provide a comprehensive set of practice questions covering the key concepts of the subject.
Design and Simulation of 4-bit DAC Decoder Using Custom Designerijsrd.com
Digital to Analog Converter (DAC), are the most complex structures and having digital input and analog output, it is found in almost all Analog and Mixed Signal Design today. There are different types of DACs currently on the market. The goal of this paper is to implement 4-bit Resistor String D/A converter using 4-bit AND gate and 4-to-16 Decoder with the help of 4 numbers Inverter. Binary (digital) coded 4-bit data was input to the converter. The data converter will convert all 4-bit binary coded data into correspondent different level of "staircase" voltage.
This document provides information about analog to digital conversion and digital to analog conversion. It discusses different types of converters including flash ADCs, successive approximation ADCs, dual slope ADCs, R-2R ladder DACs, and weighted resistor DACs. It also covers analog and digital signals, the conversion processes, and applications of ADCs and DACs in areas like data acquisition and fiber optic communication.
The MC13783 is an integrated circuit that provides power management and audio functionality for portable devices. It includes a battery charger, voltage regulators, audio codecs, amplifiers, and other features to support full device functionality while optimizing system size and bill of materials. Key features include power management, a 13-bit voice codec, stereo recording and playback, and a processor interface. The document describes the various blocks and features implemented on the MC13783 chip.
This document describes a technique called "multi-supply digital layout" that allows reliable back-annotation between digital blocks powered by different voltage supplies. It presents a design flow that uses standard CAD tools from RTL to layout. Digital blocks are grouped into voltage regions separated by isolation rings. Level shifter cells are used for voltage conversion at region interfaces. Libraries are generated for level shifters to integrate them into the digital flow for synthesis, simulation, and test. Floorplanning scripts automate placement of cells into the appropriate voltage regions.
Re usable continuous-time analog sva assertionsRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
Verification Of 1 M+ Transistors Mixed Signal IcRégis SANTONJA
This document discusses verification techniques for a mixed-signal integrated circuit containing over 1 million transistors used in cellular and multimedia applications. It describes creating block-level testbenches first before integrating them into a chip-level testbench. Verification goals have expanded from just functional verification to also consider signal integrity and power consumption to avoid issues during fabrication. A verification matrix is used to ensure all specification aspects are tested through simulation before production.
Verilog Ams Used In Top Down Methodology For Wireless Integrated CircuitsRégis SANTONJA
The document discusses using the VerilogAMS language and top-down methodology for wireless integrated circuit designs. Specifically, it discusses:
1) Using the top-down methodology to allow for general functionality verification early in the design process by analyzing the ASIC from top to bottom before individual block implementation.
2) Describing the steps of behavioral modeling of blocks using VerilogA, replacing blocks with transistor-level designs, and simulating the entire design with mixed behavioral and transistor-level blocks.
3) Noting that the top-down methodology can be applied whether the design has a large analog/small digital portion or large digital/small analog portion.
This document is a resume for Regis Santonja, a 39-year-old French national with over 15 years of experience leading verification teams for mixed-signal integrated circuits. He currently works as a Mixed-Signal IC Verification Leader at Freescale, where he leads international teams and drives verification methodology. Prior to this, he held several engineering and leadership roles in digital design and verification at companies including Motorola, CSTI, LSI Logic, and others.
Re usable continuous-time analog sva assertions - slidesRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
This document presents a systematic approach for creating accurate behavioral models for analog and mixed-signal system design and verification. The approach aims to reduce risks from model errors by collaborating closely with circuit designers to thoroughly understand circuit behavior. Key steps include automatically generating model shells, studying schematics, interviewing designers, developing circuit descriptions, validating descriptions with designers, and deciding which behaviors to include in models based on verification plans. The approach applies to modeling languages like Verilog, Verilog-AMS, and SystemVerilog.
This document discusses trends in mixed signal validation. It begins with an overview of mixed signal systems that contain both analog and digital components. The evolution of mixed signal validation is then described, from early approaches that simulated analog and digital components separately to modern tools that can jointly simulate both domains using languages like Verilog-AMS. The key steps in mixed signal validation are outlined, including modeling components in Verilog-AMS, validating blocks, and performing system-level validation. Throughout, the importance of accurate models for verification is emphasized. Examples of mixed signal modeling and a charge pump PLL validation environment are also provided.
This document describes a modular approach to constructing mixed-signal testbenches using virtual test equipment implemented in VHDL. The virtual equipment, such as signal generators and analyzers, encapsulate complexity and allow quick generation of testbenches and test cases with little effort. This modular structure can be used for both chip-level and block-level mixed-signal simulation and verification. The virtual equipment also provides a way to translate tests to real lab equipment for validation.
SAF ANALYSES OF ANALOG AND MIXED SIGNAL VLSI CIRCUIT: DIGITAL TO ANALOG CONVE...VLSICS Design
Digital to analog converter is widely used mixed-signal circuit. Testing of analog and mixed signals faces
lots of challenges due to the wide range of circuits and unavailability of one appropriate fault model. SAF
(stuck_at_Fault), Stuck_open and stuck_short fault model at transistor level is used in this paper. Furtherthese fault models are used to analyze the effects on the
characteristics parameter of 3-bit R-2R DAC.
This document summarizes a research paper about designing an interface for a successive approximation register (SAR) analog-to-digital converter (ADC) using a globally asynchronous locally synchronous (GALS) architecture. The GALS design allows independent clocking of locally synchronous blocks to reduce clock skew. Simulation results showed the 12-bit SAR ADC interface operated at 186 MHz using 30 flip-flops and 30 lookup tables on a Spartan 3 FPGA. The design achieves medium resolution conversion at high speeds ranging from kilo to mega samples per second.
1. The document presents a simulation of a low power analog channel decoder for error correction implemented in 65nm CMOS technology.
2. The decoder uses analog circuitry operating in the sub-threshold region to perform decoding, allowing for ultra-low power operation below 40uW for throughput up to 2.5Mbps.
3. The decoder architecture includes an analog decoding core that implements the sum-product algorithm, digital interfaces for input and output, and a digital controller to manage timing.
This document contains information about various VLSI and low power projects, including titles, codes, and brief descriptions. It lists 30 projects related to topics like area-efficient adders and multipliers, low power filter and encryption designs, testing techniques, and transforms. The projects aim to optimize aspects like area, speed, power consumption and implementation on FPGAs or ASICs.
This chapter discusses digital control systems, including their components and operation. Digital control systems consist of a digital controller, analog to digital converter (ADC), and digital to analog converter (DAC). The ADC converts analog signals from sensors into digital signals for the controller. The controller processes the digital signals and outputs digital signals to the DAC. The DAC then converts the digital outputs back into analog signals to act on the physical system. Key aspects covered include comparing analog and digital control loops, describing the operation of ADCs and DACs, and selecting appropriate sampling frequencies to avoid signal distortion.
ARM Based Handy and Portable Oscilloscope Using Graphical DisplayIJERA Editor
The need to have a visual perception of signals in order to monitor events in time and value brought about the
development of a measuring instrument referred to as oscilloscope. This is a design of handy and low cost
oscilloscope. The user can start/stop the display, adjust the time division and adjust the voltage division. The
requirements of the oscilloscope were three-fold: 1) low cost design, 2) capture frequencies at the medium range
and 3) construct able with a basic skill of PCB designing.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document describes a unified functional verification approach for mixed analog-digital ASIC designs. It discusses using discrete-time models in VHDL to represent analog blocks and Verilog for digital blocks. Specman is used for random stimulus generation and coverage analysis. The approach is demonstrated on a voice codec chip with digital filters, ADCs, embedded DSP, and analog/digital interfaces. Separate analog and digital environments are unified to improve coverage and reduce duplication. A Simulink model is used as a fast DSP reference model.
This document describes SysML-Companion, a tool that automatically generates simulatable and analyzable models from SysML specifications. It allows engineers to create a single SysML model as a common repository, then perform virtual prototyping and testing through simulation and hardware-in-the-loop testing. The document provides an example of using SysML-Companion to model and simulate a simple circuit containing both digital and analog components. Key benefits include enabling early testing, reducing prototype costs, and shortening time to market.
Gene's law, Common gate, kernel Principal Component Analysis, ASIC Physical Design Post-Layout Verification, TSMC180nm, 0.13um IBM CMOS technology, Cadence Virtuoso, FPAA, in Spanish, Bruun E,
Michael J. Ledford has a Bachelor of Science in Computer Engineering and Electrical Engineering from North Carolina State University. He has experience in hardware and software design, verification, and testing roles at Qualcomm, Intel, and Cisco. His skills include SystemVerilog, Perl/Python scripting, hardware debugging, and signal integrity analysis. He is looking for a role as a system hardware/software designer and tester in the consumer electronics industry.
[DCG 25] Александр Большев - Never Trust Your Inputs or How To Fool an ADC DefconRussia
Мы поговорим об общей проблеме валидации входных данных и качестве их обработки. Интерпретация входящих данных оказывает прямое влияние на решения, принимаемые в физической инфраструктуре: если какая-либо часть данных обрабатывается недостаточно аккуратно, это может повлиять на эффективность и безопасность процесса.
В этой беседе мы обсудим атаки на процесс обработки данных и природу концепции «never trust your inputs» в контексте информационно-физических систем (в общем смысле, то есть любых подобных систем). Для иллюстрации проблемы мы используем уязвимости аналого-цифровых преобразователей (АЦП), которые можно заставить выдавать поддельный цифровой сигнал с помощью изменения частоты и фазы входящего аналогового сигнала: ошибка масштабирования такого сигнала может вызывать целочисленное переполнение и дает возможность эксплуатировать уязвимости в логике PLC/встроенного ПО. Также мы покажем реальные примеры использования подобных уязвимостей и последствия этих нападений.
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1) The document proposes techniques for reducing power consumption in VLSI circuits, including minimizing bus transitions using coding schemes, resistive feedback paths to eliminate glitches, and voltage scaling.
2) A resistive feedback method is developed to eliminate glitches in CMOS circuits which reduces power consumption and improves performance.
3) Simulation results show that the proposed resistive feedback technique is effective at minimizing glitches and reducing unnecessary power dissipation compared to a design without feedback paths.
This document contains contact information for Candor Minds and a list of 29 codes describing VLSI and digital circuit design projects. The codes are grouped under categories such as High Speed, Low Power, Testing, and VLSI with MATLAB. Each code lists a title, brief 1-2 sentence description of the project. The document provides an overview of the types of projects available from Candor Minds in the areas of VLSI design, digital circuits, and DSP applications.
A to D Convertors
work to convert analog (continuous, infinitely variable) signals to digital (discrete-time, discrete-amplitude) signals. In more practical terms, an ADC converts an analog input, such as a microphone collecting sound, into a digital signal.
The document discusses attacking industrial control systems by exploiting vulnerabilities in analog-to-digital converters (ADCs). It describes how generating signals at specific frequencies and amplitudes can cause ADCs to output incorrect digital values, potentially compromising sensor monitoring systems. Several proof-of-concept attacks are demonstrated, including generating signals that race the ADC clock, exceed the valid amplitude range, or produce different readings from multiple ADCs measuring the same signal. The document warns that many industrial systems have vulnerabilities in their analog interfacing that could allow remote manipulation if exploited.
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Mixed signal verification challenges
1. Mixed-Signal Verification Challenges
Regis Santonja, Verification Engineer, Freescale
Semiconductors
The increasing complexity of today’s Mixed-Signal Integrated Circuits (IC) goes with
increasing needs in IC verification to ensure the functionality, but also signal integrity
and power consumption. This paper is going to present the challenges of mixed-signal
verification in its two main phases: simulation setting and coverage analysis on the
other hand. In the mean time, it will present how, at Freescale, we took up these
challenges during the development of a real-case Sensor IC, using Cadence eManager
together with Verilog-AMS, SystemVerilog, and “wreal-based” digital models of the
analog environment.
CDNLive! EMEA 2010 1 Challenges of Mixed-Signal Verification
2. Contents
Presentation of the IC and its Verification Environment................................................ 3
Early simulations with wreal models............................................................................. 3
Mixed-signal simulations .............................................................................................. 4
A single simulation environment................................................................................... 5
Simulation Results and Coverage.................................................................................. 7
Control-oriented functional coverage ........................................................................ 8
Data-oriented functional coverage............................................................................. 8
Applying advanced digital methods to mixed-signal verification................................. 10
Conclusion.................................................................................................................. 10
Bibliography ............................................................................................................... 11
CDNLive! EMEA 2010 2 Challenges of Mixed-Signal Verification
3. Presentation of the IC and its Verification Environment
The methodology detailed in this paper has been applied to a low-power three axis
accelerometer IC dedicated to consumer applications. It has several programmable G-
scales and output data rate frequencies It can detect orientation, motion, taps, and free-
fall events. This is a mixed-signal chip where analog and digital functions are roughly
of the same size and complexity.
The chip-level testbench is hierarchical. Its top-level is in Verilog-AMS and gives the
ability to exercise the IC through its digital and analog interfaces, including the
supplies. The sequence of each test is based on a usual initial process, the analog
interface being controlled from it, via the sharing of real values that affect the analog
begin section. Each specific test is coded in a vector file that is included into the
testbench at compilation, thanks to a compiler directive. The monitoring is taken in
charge both by the Verilog-AMS part of the bench, and by an instantiated
Systemverilog monitoring module. The diagram below presents the IC and its
surrounding testbench.
Bandgap
AMS LDO
stimulation Memory SV
oscillator
Monitoring
DSP
ADC
Code coverage
Analog
Generators
Custom Logic I2C Functional
coverage
Supplies and Digital
TESTBENCH
Figure 1 The SoC and its mixed-Signal, Mixed-level testbench
Early simulations with wreal models
We adopted a progressive verification approach to verify our circuit. We started the
chip-level simulations in a pure digital world, using the wreal modeling technique,
taking advantage of the execution speed of the digital solver, and the lack of
convergence issues. This let us look, early in the verification process, for potential long-
run issues that were not affordable with analog or even mixed-signal simulations.
CDNLive! EMEA 2010 3 Challenges of Mixed-Signal Verification
4. However, wreal modeling also has several drawbacks, especially, if the model requires
a high “analog” accuracy level, or when it gets mixed with analog blocks. The code
might then get more complex than its Verilog-AMS equivalent. First of all, you have to
address the connection of wreal nets to logic pins yourself. Secondly, analog operators
available in plain Verilog-AMS code cannot be used here.
Verilog-AMS is rich of several analog operators, such as derivative, time and circular
integrator, transition and slew (that are used to remove discontinuities that help
preventing convergence issues when connected to analog circuits). Finally they include
Laplace and Z-transform filters and the last_crossing function to get the last simulation
time when a signal crossed zero. In pure wreal models, none of these operators are
available, as they can only appear in the analog process. Hence, using wreal models
makes it impossible to backtrack and find the time when a signal crossed a value. It is,
however, possible to design filters, transforms, integration or derivative functions. But
this needs to be done manually, which is not trivial. The input signal must be normally
sampled at twice its Nyquist frequency, or higher, but the more the steps, the slower the
simulation. Still, an analog transfer function, expressed in the s-domain, can be modeled
in the discrete z-domain thanks to the bilinear transform.
Moreover, wreal is based on a signal-flow model and can only handle a single value for
each node, whereas plain Verilog-AMS code represents each signal node with two
values: its potential and its flow. This is the conservative systems model. Signal-flow is
perfect for early verification, but, as the design progresses and some analog behaviors
need to become more accurate, it becomes necessary to take the flow into account.
Indeed, there is no easy way to model basic analog components such as capacitors or
resistors using wreal.
Mixed-signal simulations
Verilog-AMS models can be slow to simulate, depending on the modeling technique
and the level of abstraction used. A model can even be slower than its actual transistor
design! We have presented in a previous paper (“Verification of 1M+ transistors Mixed-
Signal IC for Cellular and Multimedia Applications”, Cadence Live 2008), how it is
possible to speed-up mixed-signal simulations by a mixed-level approach based on
minimal, but well targeted models.
Analog and digital signals are connected together via connect modules. Cadence
provides a set of connect modules to connect both logic and wreal to analog (electrical)
nets, and vice versa. However, when mixing wreal models with analog blocks, there are
several difficulties. One shows up when the value to be transferred through the
connection is representing a current. Indeed, the E2R default connect modules are
representing a voltage source. Tweaking the connect rules of such an R2E and make its
range better fit the required current values, or tweaking its output resistor is not enough
to appropriately represent a current source. Fortunately, Cadence gives in its “Verilog-
AMS Real Valued Modeling Guide” an example of what a R2E representing a current
source output can be. Similarly, an E2R_current main body could be something like:
connectmodule E2R_current (Dout, Ain);
output Dout;
wreal Dout; //output wreal
CDNLive! EMEA 2010 4 Challenges of Mixed-Signal Verification
5. input Ain;
electrical Ain; //inout electrical
electrical vref;
<parameters declaration>
real Iin;
real Dreg;
assign Dout = Dreg;
always @(absdelta(Iin, idelta, ttol, itol))
Dreg = Iin;
analog begin
V(vref) <+ 0.5*vsupply;
I(Ain,vref) <+ V(Ain,vref); //1 ohm resistor btwn Ain and vref
Iin = transition(V(Ain,vref), 0, tr, tf);
end
endmodule
One difficulty with these connect modules is that they pass the values with no sign
change, hence do not respect the usual current sign convention which considers the
current to be positive when getting into the block, and negative when flowing out of it.
Hence, we can get inconsistencies when mixing wreal models with analog, depending
on which block is swapped. Hence smarter connect modules to interface currents have
to be written.
As the design of our accelerometer progressed towards completion, more and more
blocks could be verified at transistor-level. High-frequency analog blocks could be kept,
at first, as wreal models, while those that had a close-to-DC behavior, such as the
biasing, could start being verified at transistor-level. In some cases, an intermediate step
was to replace some wreal models with more accurate Verilog-AMS models. We finally
ended with full-transistor simulations. Indeed, the more the blocks at transistor-level,
the higher the chances to catch leakages, over-consumptions, oscillations and
instabilities, or floating nodes, that cannot be caught earlier.
A single simulation environment
Traditionally, the analog, digital and mixed-signal designers, each, have a specific
simulation environment and flow. However, it is possible to use eManager as a single
front-end for analog, digital and mixed-signal simulations, providing we know how to
launch them from a command-line.
Additionally, having all our simulations self-checking, even the analog ones, eManager
can track our global Test Coverage. The latter is a metric which simply counts which
test passed and which failed, and presents the result as a coverage percentage. Indeed,
eManager is able to scan the simulation log files, look for specific words, strings, or
regular patterns, and record the test’s status accordingly.
Our digital simulations were launched based on the Unix make command and a
corresponding Makefile. Here is an extract of our VSIF file used by eManager to launch
our digital simulations:
session chip_regression {
top_dir : regressions;
output_mode: terminal;
group digital_simulations {
CDNLive! EMEA 2010 5 Challenges of Mixed-Signal Verification
6. timeout: 0; // No time out.
count: 1;
run_script: 'make ncsim TEST=$RUN_ENV(BRUN_TOP_FILES)
COMP_ARGS="-sv" SIM_ARGS="+nowavedump";';
scan_script: vm_scan.pl generic.flt shell.flt ius.flt;
test vey_i2c_standby_shift { count : 1 ;
top_files : vey_i2c_standby_shift;
};
Figure 2 Launching our pure digital simulations from eManager (extract of the VSIF file)
The Makefile tells the make command what to do in details. In the case of our digital
simulations, it launches ncvlog, ncelab and ncsim commands. Some generic command
switches are given to these commands via corresponding CAF files.
ncsim:
ncvlog -file rtl_func.caf -logfile ncvlog.log
-define stimulus_file="$(TEST).v" $(COMP_ARGS)
ncelab -file ncelab.caf -coverage a -logfile ncelab.log
ncsim -status -file ncsim.caf -logfile $(TEST).log
$(SIM_ARGS)
-covoverwrite -covdesign digital -covtest $(TEST)
...
Figure 3 Extract of the Makefile used to launch digital simulations
Our mixed-signal, mixed-level simulations were launched from eManager with a
custom Perl script (start_test.pl) that builds the appropriate amsdesigner command after
a pre-compilation of specific modules such as the custom connect modules and the
Systemverilog monitor. Here is an extract of the VSIF:
group mixed_simulations {
verification_scope: AMS;
timeout: 0;
count : 0;
run_script : “start_test.pl
-lib top_verification
-cell top_testbench
-view $ATTR(my_config)
-test_name $RUN_ENV(BRUN_TOP_FILES)
-run_dir `pwd`
cds_globals generic.cds_globals
-define SEED=`perl -e 'print
int(rand(1e6))'`
-profile";
scan_script: vm_scan.pl generic.flt shell.flt ius.flt;
test i2c {
count : 1 ;
my_config : config_ams;
top_files : i2c;
};
...
Figure 4 Launching our mixed-signal simulations from eManager (extract of the VSIF file)
CDNLive! EMEA 2010 6 Challenges of Mixed-Signal Verification
7. The amsdesigner command is able to read Cadence configuration views from the DFII
analog environment. The configuration views tell which representation of each block in
the design is to be compiled for each specific simulation. This is the place where we
select either a wreal model, an AMS model, or a transistor schematic for each block in
the design.
You can notice that a seed is fed to the simulation with a `define directive. We’ve been
using this seed to drive random ramp-up and ramp-down times on the chip’s power
supplies. The goal was to capture potential cross-conduction between supply lines. Here
is a piece of digital code in the testbench which drives the analog block to generate the
proper supplies. The variables used to drive the rise, fall and delays are real numbers.
initial begin
`ifdef SEED
VDD_rise = 100u + 1u*($random(seed) % 100);
VDD_fall = 100u + 1u*($random(seed) % 100);
VDDIO_rise = 100u + 1u*($random(seed) % 100);
VDDIO_fall = 100u + 1u*($random(seed) % 100);
`endif
end
Figure 5 Creating random supply ramps and delays
The piece of analog code which actually applies the supplies to the chip looks as
follows:
analog begin
V(VDD_stim) <+ transition(VDD_level, 0, VDD_rise, VDD_fall)
I(VDD, VDD_stim) <+ V(VDD, VDD_stim)/RVDD;
V(VDDIO_stim) <+ transition(VDDIO_level, 0, VDDIO_rise,
VDDIO_fall);
I(VDDIO, VDDIO_stim) <+ V(VDD_IO, VDDIO_stim)/RVDDIO;
end
Figure 6 Piece of analog code to drive the supplies
The other analog pins are driven the same way, all controlled from the digital process.
They are driven through resistors whose values are also driven from the digital code.
They can be set to high values to emulate high impedance states, for example when the
corresponding chip’s pin is configured as an output. This mechanism also allows the
dynamic connection of more complex external circuitry (such as RC filters), all being
controlled from the testbench and its stimulus file.
Simulation Results and Coverage
After we were able to simulate the chip, starting with wreal models, then with a mix of
wreal, Verilog-AMS and real transistors, and finally at full-transistor level, we needed
to ensure that enough required functionality got covered.
Test Coverage just tells which simulation passes or fails, but does not say what is
verified. There are two other types of coverage metrics for that: the Code Coverage, and
the Functional Coverage. The first one is automatic and measures the verification
completion of the digital part of the design.
CDNLive! EMEA 2010 7 Challenges of Mixed-Signal Verification
8. We have used ICC (Incisive Comprehensive Coverage) to build the necessary coverage
reports to identify the verification holes and generate additional tests to cover them.
eManager automatically interfaces with ICC and handles the coverage files generated
by the simulations.
We observed that we were right away having an excellent FSM state coverage, but that
some transitions were missing, usually the ones that go back to the Idle state when the
state-machine is interrupted. In the same spirit, we initially had a pretty poor toggle
coverage, especially on reset or enable lines. Indeed, not only is important to validate
what the chip should do (when we enable a particular function), but also what the chip
should not do (if the function is disabled).
The Functional Coverage is based on the specification and is basically a list of the
functional features that need to be covered. It is closely linked to the verification plan
and needs to be specified by the user prior to simulation. As such, it needs more effort
up-front than the automated, effortless Code Coverage.
Systemverilog provides language constructs to specify functional coverage of values or
expressions and their cross-coverage. It also gives means to create and manipulate
coverage bins and associate them with measures.
Control-oriented functional coverage
Our IC measures its acceleration on the 3 dimensional axes which are multiplexed in
time in order to share common hardware resources. The signal chain that converts the
analog acceleration to digital numbers is made of several time-multiplexed analog
stages. The time-sequence of controls of all the involved switches and commands is
very critical for the final converted result accuracy and must be carefully verified.
We have used concurrent assertion constructs provided by Systemverilog to check the
complex chronograms of the control signals fed to the analog signal chain. Here is an
example of how the chronogram of one regulator enable was constantly verified along
every simulation scenario:
prop_vreg_en : assert property
(@(posedge clk) $rose(hf_en)
|=> (vreg_en[*72] ##1 ~vreg_en[*240] ##1 vreg_en[*172] ##1
~vreg_en[*140])[*1:$])
`STIM.PRINT_PASS("vreg_en is OK");
else begin
$warning("%m fails");
PRINT_ERROR("");
end
Figure 7 Code example of a Systemverilog concurrent assertion
Data-oriented functional coverage
Data-oriented functional coverage tracks the number of times a specific variable in the
design reaches a specified set of values, or transitions, or a combination of those.
Systemverilog defines covergroups to gather those variables together. These variables
are called coverpoints. All the coverpoints within a covergroup are evaluated on the
same “clocking” event. The latter can be any expression that becomes true, or even the
start or the end of execution of a named block, task, function, or class method.
CDNLive! EMEA 2010 8 Challenges of Mixed-Signal Verification
9. As an example, here is how we tracked the coverage of all the programmable I2C
registers of our accelerometer. The actual code was generated automatically from the
I2C register map specified in an Excel document.
`define STATUS_FLD 0
`define XD_FLD 1
`define YD_FLD 2
`define ZD_FLD 3
`define F_CNT_FLD 4
`define F_WMRK_FLD 5
`define F_OVF_FLD 6
`define F_MODE_FLD 7
`define NONE 'h300
event i2c_write_field_event;
typedef enum {
STATUS_FLD = `STATUS_FLD,
XD_FLD = `XD_13_6_FLD,
YD_FLD = `YD_5_0_FLD,
ZD_FLD = `ZD_13_6_FLD,
F_CNT_FLD = `F_CNT_FLD,
F_WMRK_FLD = `F_WMRK_FLAG_FLD,
F_OVF_FLD = `F_OVF_FLD,
F_MODE_FLD = `F_MODE_FLD,
NONE = `NONE } i2c_field_type;
i2c_field_type i2c_write_field = `NONE;
covergroup cg_i2c_write_field @i2c_write_field_event;
cov_i2c_write_field : coverpoint i2c_write_field
{option.auto_bin_max = 512;} // otherwise limit is 64 values for
enum
endgroup : cg_i2c_write_field
cg_i2c_write_field I_cg_i2c_write_field = new();
always @(`STIM.f_cnt)
if ($time > 0)
begin
@(`DIGITAL_CORE.vey_i2c.i2c_write);
i2c_write_field = `F_CNT_FLD;
-> i2c_write_field_event;
end
Figure 8: Functional Coverage code for our I2C registers
Additionally, we could track analog events, such as the voltage level reached by the
internal supplies and biasing signals. The code example below shows how we can
record that the bandgap did start. The Systemverilog part of the code is instantiated in
the Verilog-AMS testbench. The latter monitors the signal of interest and sends an event
to the Systemverilog monitor. Here is a piece of the latter:
`define VBGON 1
`define VGBOFF 2
event vbg_event;
CDNLive! EMEA 2010 9 Challenges of Mixed-Signal Verification
10. typedef enum { VBGON = `VBGON,
VBGOFF = `VBGOFF } vbg_state_type;
vbg_state_type vbg = `VBGOFF;
covergroup cg_vbg @vbg_event;
cov_vbg : coverpoint vbg;
endgroup : cg_vbg
cg_vbg I_cg_vbg = new();
Figure 9 Systemverilog code used to monitor analog functional coverage
And here is the related AMS piece of code:
always @(cross(V(`TOPCELL.vbg)-0.9, 0, 1n, 10u))
begin
if (V(`TOPCELL.vbg) > 0.9)
covmon.vbg = `VBGON;
else
covmon.vbg = `VBGOFF;
-> vbg_event;
end
Figure 10 Verilog-AMS code used to trig the Systemverilog monitor on an analog event
Applying advanced digital methods to mixed-signal
verification
Wreal modeling is a means to handle real, analog-like signals, within the discrete digital
solver. As such, it opens the door of mixed-signal simulation to some highly advanced
digital verification tools and methodologies.
However, the quality of the verification is only as good as the quality of the test case
simulations that were developed. Reaching 90% coverage with directed tests is a tough
and costly challenge, in terms of time-to-market, and return on investment. Hence a
complementary approach would be to have an automatic test case generation solution,
just as it exists in pure digital verification. This approach would not replace the need to
write traditional directed tests. It would just be a means to complement the available
suite of directed tests.
As Systemverilog can now be used within mixed-signal, mixed-level simulations, we
can take advantage of its ability to track all types of coverage. As it also enables on-the-
fly queries of the coverage with system tasks such as $get_coverage(), a closed-loop
coverage-driven approach becomes possible. Constrained random stimuli generation
can explore unexpected places of the verification space.
Conclusion
We have presented how, at Freescale, we managed to guaranty a first pass success to a
three axis accelerometer IC, adopting a progressive verification approach, starting with
pure wreal models, then progressively replacing those with more accurate Verilog-AMS
ones, and finally with their transistor-level representation, ending with (full-)transistor
simulations.
CDNLive! EMEA 2010 10 Challenges of Mixed-Signal Verification
11. We have seen that, despite the fact that wreal modeling enables chip-level simulations
very early in the design cycle, helping system designers to find early issues, it also
presents some limitations and difficulties. Still, wreal coding can model complex analog
behaviors, at digital speed, and can be considered a bridge between the analog and the
digital world, opening the door of all the latter’s advanced verification techniques to
mixed-signal ICs.
We have also seen that eManager can be used as a common front-end for all our
simulations. Additionally, as it is linked with ICC, it can gather all types of coverage
metrics available for analog, digital and mixed-signal domains.
Bibliography
• Verification of 1M+ transistors Mixed-Signal IC for Cellular and Multimedia
Applications, in Cadence Live 2008 proceedings, Regis Santonja, Freescale
Semiconductors.
• Verilog-AMS Real Valued Modeling Guide, Cadence Design Systems Inc. 2009.
• ICC Used Guide, Cadence Design Systems Inc. 2009.
• Assertion Writing Guide, Cadence Design Systems Inc. 2009.
• Verilog-AMS Language Reference Manual, version 2.2, Accellera, November
2004.
• Systemverilog 3.1a Language Reference Manual, Accelleram May 2004.
• Solutions for mixed-signal SOC verification. As old methods fall short, new
techniques make advanced SOC verification possible, Kishore Karnane, Greg
Kurtis and Richard Goering, Cadence Design Systems, Inc.
• A scalable Verification Methodology to Overcome the limitations of current
Verification approaches, Brian Bailey, chief technologist for the Design
Verification and Test Division of Mentor Graphics.
• Verification of complex Analog Integrated Circuits, in Custom Integrated
Circuits Conference 2006 proceedings Ken Kundert and Henry Chang.
• Evolving the Coverage-Driven Verification Flow, Matthew Balance, Mentor
Graphics.
• Maximizing Verification Effectiveness using Metric-Driven Verification, Nick
Heaton, Senior Solution Architect, Cadence Design Systems, Inc.
CDNLive! EMEA 2010 11 Challenges of Mixed-Signal Verification