Cv June 2009


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Cv June 2009

  1. 1. Régis SANTONJA 100 rue Saint Pierre – 31600 MURET (home) +33-562 233 082 - (mobile) +33-673 475 019 Email : 39 years old, Divorced, 2 children (5 and 7 years old) French Digital Design & Mixed-Signal IC Verification Leader CORE COMPETENCIES International Team Lead - Multi-cultural context (USA, Europe, India) - Organize tasks & planning, priorities, dependencies. - Identify blocking situations and coordinate actions - Dynamic resource allocation - Several projects in parallel - Setup weekly multi-site team meetings/calls: progresses, issues, risks follow-up. - Escalade issues - Weekly reporting - Team building Technical Innovation - Defined & developed complete set of mixed- - Multi-supply digital layout technique signal verification IPs using Verilog-AMS - Several Technical Awards at Motorola. - Involved in patent development Design - Power Management (SPI/I2C, power up sequence, interrupts, touch-screen controller, etc…) - Voice & Stereo (16 bits) digital filters - Baseband processor, ATM switches, … - Design For Test (scan, Boundary scan,…) Miscellaneous Languages - Multi-site Revision Control & Database Management - English : fluent (Design Sync + a bit of Clearcase) - Spanish : high school level - Unix (C-shell, Korn Shell, Awk, Perl + a bit of Tcl) - CAD (Cadence, Synopsys, Mentor Graphics) - Italian : beginner - MS Office (Word, Excel, PowerPoint, Project) - German : beginner - Lab/debug, com boards, needles under microscope PERSONAL QUALITIES - Rigorous and methodical - Customer focused - Enthusiast - Ethical - Team spirit - Adaptability (to people, priorities, - Open and direct communication procedures & environment). INTERNATIONAL EXPERIENCE (2 years) - United States (San Jose) 9 months - Germany (Stuttgart) 9 months - Italy (Milan) 3 months - Spain (Madrid) 2 months
  2. 2. PROFESSIONAL EXPERIENCE (15 years) 2003 – Today Mixed-Signal IC Verification Leader at Freescale (France) - 5 to 10 people spread over Europe, USA and India. - Build and track verification plan - Track verification coverage - Bug & fixes follow-up - Weekly report (progresses, issues, planning updates) Elaborate company’s best-class standards - Drive cross-functional team in verification methodology - Technology watch Complex mixed-signal ICs (~1M+ components): - Power-Management (LDO’s, Switchers, battery charger, power gating, …) - Audio converters (Voice and Stereo) and their digital interface (I2S,…) - Real Time Clock with wake-up alarm,... - User Interface (USB 2.0 OTG, RGB LEDs,…) 1999 – 2003 Senior Digital IC designer at Motorola Semiconductors (France) - Global IC control logic and digital filters for audio Codec (13 bits resolution, mono-bit sigma-delta) and stereo DAC (16 bits resolution, 4 bits sigma-delta). - Development of a digital filters serial architecture - Formal Verification - Place & route and timing closure - Customer technical interface 1998 Technical Leader at CSTI (France) - Re-design of a digital baseband processor (LPGA at Chip Express) for automobile radio networking (automatic highway tolls) - Coordinated design changes and verification - Analyzed and fixed very tricky killer bug causing frame losses (more than 1 per million specified). - Ran and documented complete verification plan, non- regression tests - Today in mass production and present in anyone's car in France 1997 International Project Coordinator at LSI LOGIC (USA) - Organized conference calls between European, Japanese and US teams in order to fix backend, manufacturing, testing and failure analysis issues. - Identify and fix blocking situations. - Setup and track action lists. - 5 to 10 projects in parallel. 1997 Design For Test expert at LSI LOGIC (Italy) - 3 months mission to help Milan’s Design Center - High priority /short planning project. - Inserted scan and JTAG logic - Generated test patterns 1996-1997 Technical Leader at LSI LOGIC (France) - Digital design of an ATM switch/router ASIC for Matra Ericsson Telecommunication (MET). - Technical customer interface. - Monthly progress/issues customer meetings Project Management Certification at Corphis (Munich)
  3. 3. 1996 Digital Designer at LSI LOGIC (Germany) - Digital design of an FTTC (Fiber To The Curb) ASIC for Interactive Video On Demand services on twisted pair cables for ALCATEL. - ATM frames re-formatting (capture, scrambling, Reed Salomon encoding) + datapath control. - Effective team work in a foreign country. - Won technical respect as a new digital designer. 1994-1995 Applications Engineer at LSI LOGIC (France) - Technical Support of customer's ASIC design. - Ensuring best design and testability practices are met before signoff. EDUCATION 1988 – 1993 ESIEE (Ecole Supérieure d’Ingénieurs en Electronique et Electrotechniques), MSEE, Signal Processing & digital design - 8 months project: Specification and RTL coding of an ASIC to accelerate 3D imaging in PCs. There was no HW acceleration at that time on PC graphic cards. - 2 months in Madrid for the development of a production control system at CMV Plasticos. 1988 High school A level - Physics and Mathematics - Distinction Others I also studied, for my personal interest, and with no plan to take the exam two other MAS (Master of Advanced Studies, called DEA in France). This was in parallel with my engineering training and my military service: - Cognitive Sciences (AI, blur logic, neurology, linguistics, philosophy) - Computer Sciences applied to Digital Imaging OTHER INTERESTS Computers Linux, Windows XP, Mac OS X, Java, Digital Imaging (Photoshop CS) Sport Elastic Jump, paragliding, parachuting, surf Literature Psychology, philosophy, history