EELE 5331 Digital ASIC DesignLab ManualDr. Yushi Zhou.docxtoltonkendal
EELE 5331: Digital ASIC Design
Lab Manual
Dr. Yushi Zhou
Department of Electrical Engineering
Lakehead University
Thunder Bay, Ontario, Canada
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 MOSFET Devices and Layout Tutorial . . . . . . . . . . . . . 4
2.1 Prepare For Schematic . . . . . . . . . . . . . . . . . . 4
2.2 Perform Simulation . . . . . . . . . . . . . . . . . . . . 7
2.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Layout Veri�cation . . . . . . . . . . . . . . . . . . . . 17
2.5 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 How to understand DRC error report . . . . . . . . . . 26
3 CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Design speci�cations . . . . . . . . . . . . . . . . . . . 27
3.2 Lab Procedure . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1
EELE5331:Digital ASIC Design [email protected]
1 Introduction
This lab manual is an essential components of EELE5331: Digital ASIC
Design, o�ered by Dr. Yushi Zhou. The lab works consists of schematic
entry, symbol generation, pre-layout simulation, layout, physical and logic
veri�cation, extraction and post-layout simulation for the design. All the
students are required to submit individual lab report before the deadline.
All reports must be typed and professionally prepared. The content that
needs to be included in the report are given at the end of each lab. There
are total three labs, and each part will be released before the lab starts.
• Lab 1: MOSFET devices and layout tutorial
• Lab 2: CMOS Inverter
• Lab 3: CMOS Digital Logic Circuits
It should be noted that the students are not limited to the assigned lab
time, which may not be enough to complete the lab. Students are expected
to work on the lab during their free time if that case is required. You may
use remote log-in to complete the labs.
TSMC CMOS 180 nm technology process design kit (PDK) is a 1-Poly,
6-Metal technology, with a maximum supply voltage of 1.8 V for thin oxide
devices and 3.3 V for thick oxide devices. This process is suitable for design-
ing analog, digital, RF and mixed-signal circuits and systems. In this course,
all the labs are designed based upon CMOS 180 nm process. The computer-
aided design (CAD) tools that are adopted in this course are from Cadence
Design Systems for the purpose of schematic entry, simulation, implemen-
tation and veri�cation. The Cadence custom IC design platform provides
a graphical interface for various stages in the design �ow. An overview of
the design �ow and which tools are involved in each stage is shown in Fig.1.
As you may notice that there are loops, indicating iterative procedures. For
instance, if the physical layout does not pass design rules check or LVS check,
Page 2
EELE5331:Digital ASIC Design [email protected]
the modi�cation of.
EELE 5331 Digital ASIC DesignLab ManualDr. Yushi Zhou.docxtoltonkendal
EELE 5331: Digital ASIC Design
Lab Manual
Dr. Yushi Zhou
Department of Electrical Engineering
Lakehead University
Thunder Bay, Ontario, Canada
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 MOSFET Devices and Layout Tutorial . . . . . . . . . . . . . 4
2.1 Prepare For Schematic . . . . . . . . . . . . . . . . . . 4
2.2 Perform Simulation . . . . . . . . . . . . . . . . . . . . 7
2.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Layout Veri�cation . . . . . . . . . . . . . . . . . . . . 17
2.5 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 How to understand DRC error report . . . . . . . . . . 26
3 CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Design speci�cations . . . . . . . . . . . . . . . . . . . 27
3.2 Lab Procedure . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1
EELE5331:Digital ASIC Design [email protected]
1 Introduction
This lab manual is an essential components of EELE5331: Digital ASIC
Design, o�ered by Dr. Yushi Zhou. The lab works consists of schematic
entry, symbol generation, pre-layout simulation, layout, physical and logic
veri�cation, extraction and post-layout simulation for the design. All the
students are required to submit individual lab report before the deadline.
All reports must be typed and professionally prepared. The content that
needs to be included in the report are given at the end of each lab. There
are total three labs, and each part will be released before the lab starts.
• Lab 1: MOSFET devices and layout tutorial
• Lab 2: CMOS Inverter
• Lab 3: CMOS Digital Logic Circuits
It should be noted that the students are not limited to the assigned lab
time, which may not be enough to complete the lab. Students are expected
to work on the lab during their free time if that case is required. You may
use remote log-in to complete the labs.
TSMC CMOS 180 nm technology process design kit (PDK) is a 1-Poly,
6-Metal technology, with a maximum supply voltage of 1.8 V for thin oxide
devices and 3.3 V for thick oxide devices. This process is suitable for design-
ing analog, digital, RF and mixed-signal circuits and systems. In this course,
all the labs are designed based upon CMOS 180 nm process. The computer-
aided design (CAD) tools that are adopted in this course are from Cadence
Design Systems for the purpose of schematic entry, simulation, implemen-
tation and veri�cation. The Cadence custom IC design platform provides
a graphical interface for various stages in the design �ow. An overview of
the design �ow and which tools are involved in each stage is shown in Fig.1.
As you may notice that there are loops, indicating iterative procedures. For
instance, if the physical layout does not pass design rules check or LVS check,
Page 2
EELE5331:Digital ASIC Design [email protected]
the modi�cation of.
ECE321322 Electronics I & Lab Spring 2015 1 Final P.docxjack60216
ECE321/322 Electronics I & Lab Spring 2015
1
Final Project – Demo. Review Form
Student name:
Item Comments Grade
Simulation verification
Are the transformer and overall
power supply working
/10
Are the pre/main
amplifiers work?
/10
Final breadboard setup and test
Power supply works?
/10
Is Preamp design approach
correct and the board working?
/10
Is main amplifier design correct
and working?
/10
Lab skills
Proficient with lab equipment
and testing?
/10
Overall grade /60
ECE321/322 Electronics I & Lab Spring 2015
1
Final Project – Report Review Form
Student name:
Item Comments Grade
Project report
Report format as specified?
/10
Technical discussion with
simulation and measurement
data?
(Ability to analyze and design
complex electrical and electronic
devices)
/10
Did theory cover sufficient
details to compare and justify
experimental data?
(Knowledge and ability to apply
mathematics)
/10
Appendix: Pspice source files
and other info (e.g., data
sheet)?
/10
Overall grade /40
1
ECE 321 Final Project
This project is for individual student and is NOT a team project.
HOWEVER, collaboration among team members (i.e., ECE322 team) is strongly
encouraged and should be properly acknowledged in the final project report.
Final Project Report Due: May 4, 2015 to be uploaded onto Evaltools
Project Demo:
Tues., 5/5/15, 1:30 - 3:30 For TTH Classes that meet at 3:00 pm (ECE 322_01)
Wed., 5/6/15, 1:30 - 3:30 For MWF Classes that meet at 3:00 pm (ECE 322_02)
Objective
1. To design an “analog computer” to fulfill the following requirement
Vout = 25*(A*V1in + B*V2in)
where V1in = V2in = 10 mVpp @ 1 kHz, is the input sinusoidal (sine) signal to the analog
computer, which can be generated from a function generator; Vout is the output of the
computer; and A is a constant of your birth month mod 10 (divide by 10 and take the
remainder) and B is a constant of your birth day mod 10 (divide by 10 and take the
remainder).
e.g., If your birthday is November 7, A = 11 mod 10 = 1 and B = 7 mod 10 = 7.
If your birthday is February 26, A = 2 mod 10 = 2 and B = 26 mod 10 = 6.
2. To verify the circuit design with the help of contemporary software
3. To build and test the final design on breadboard
Instructions and Related Information
Figure 1 shows an illustrative block diagram of the analog computer.
Figure 1. Block diagram of an “analog computer”
2
DC dual-polarity power supply:
1. It should be able to provide a stable ±12V dc power.
2. 7812 and 7912 voltage regulators are available (datasheets are available at
AllUser U:\ECE Component Library on lab workstations). If you are using your
own laptop, you need to type \\ECEVault\AllUser\ECE Component Library.
3. Refer to the figure below (read Chapter 17 of your textbook):
...
1. III Semester B.Tech. (E&C)
EC-216 LINEAR SYSTEMS AND SIGNALS LABORATORY
Laboratory Manual
Department of Electronics & Communication Engineering
NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHKAL
SRINIVASNAGAR 575025 KARNATAKA
AUGUST 2010
2. Linear Systems & Signals Laboratory
Contents
Module I Circuit Simulation using PSPICE
1.1 Getting started
1.2 DC Steady state Analysis
1.3 AC Steady state Analysis
1.4 Analysis of Coupled Circuits
1.5 DC Transient Analysis
1.6 Parametric Analysis
1.7 Frequency domain analysis
Module II Simulation using MATLAB/SIMULINK
2.1 Getting started - Introduction to MATLAB: Interactive computation,
2.2 MATLAB scripts, Graphics using MATLAB, Functions
2.3 File I/O, GUI
2.4 Circuit Simulation using MATLAB
2.5 Properties of Signals
2.6 Effect of sampling and quantization
2.7 Modeling using SIMULINK
2.8 Time domain representation of systems
2.9 Frequency Domain Representation of Systems
2.10 Transform Domain Representation of systems
Dept. of E&C, NITK Surathkal 2
3. Linear Systems & Signals Laboratory
COURSE PLAN AND EVALUATION PLAN
Course Code: EC216 Course Title: Linear Systems & Signals Lab
L-T-P: 0-0-3 Credits: 2
Pre – requisites: None Course Instructor: Dr. Sumam David
Teaching Department: Electronics and Communication Engineering
Objective of the course:
Through the experience in these labs the student will be able
• To introduce PSPICE for circuit analysis.
• To analyze the R-L-C networks for different types of excitation
• To use Matlab as a tool for modeling & simulating signals and systems
• To analyze continuous- time signals in terms of their time and frequency domain behavior
Evaluation Plan:
Continuous Evaluation – 30 %
ο Preparation, Class Performance, Documentation, Regularity, Class projects
Test I – 30 %
ο Circuit Simulation using PSPICE
Test II – 40 %
ο Circuit Simulation using MATLAB / SIMULINK
Circuit Simulation Using PSPICE
Introduction to PSPICE
Module I DC and single phase AC steady state analysis Week 1 – 5
Coupled circuit analysis.
DC transient analysis, Frequency domain analysis.
TEST 1 Week 6
Simulation Using MATLAB/SIMULINK
Introduction to MATLAB: Interactive computation, MATLAB scripts
Graphics using MATLAB, Function, File I/O, GUI,
Module II Modeling using SIMULINK Week 7-11
Properties of Signals
Effect of sampling and quantization
Time domain representation of systems
Frequency Domain Representation of Systems
Transform Domain Representation of systems
TEST 2 Week 12
Prepared by: Approved by
Sumam David S. Sumam David S.
Course Instructor Head, Dept of E&C and DUGC Chairperson
Dept. of E&C, NITK Surathkal 3
4. Linear Systems & Signals Laboratory
MODULE I - CIRCUIT SIMULATION USING PSPICE
What is Circuit Simulation?
Simulation lets one predict how a circuit will behave without constructing a prototype. A
simulator is a software breadboard on which software models of circuit components can be
assembled and tested. It provides economic and fast solution for testing of designs.
What is PSPICE?
SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis and PSpice
is a PC version of SPICE. The program SPICE was developed at University of California,
Berkeley in early 1970’s and has become a defacto standard in the area of circuit simulation.
Over the years many mainframe and PC versions of SPICE have evolved. PSpice contains
circuit models for common circuit elements, active as well as passive, analog as well as
digital, and is capable of simulating most of the electrical and electronic circuits. The
software forms a set of analysis equations from the circuit description and is solved using
numerical methods.
OrCAD PSPICE, a Windows based package, comes as part of Cadence PCB System
Division's OrCAD series products consisting of tools for analog and digital circuit simulation,
waveform analysis, and PCB design. In this laboratory module we will be using OrCAD
PSPICE 9.2 Lite Edition for circuit simulation. This public domain software has most of the
capabilities of its full version, except for a limitation on circuit size.
In OrCAD PSPICE, the circuit can be described either as a netlist or as a schematic.
However, we will be using the schematic approach for this laboratory module. The circuit is
then analysed and the waveform are displayed interactively using the waveform viewer,
Probe. If we visualise PSpice as a software breadboard, then the Probe can be compared to a
software oscilloscope.
REFERNCES
1. M.H.Rashid, Spice for Circuits and Electronics using PSPICE, PHI, 1995
2. P.W. Tuinenga, SPICE a Guide to circuit simulation and analysis using PSPICE,
PHI, 1990
3. Irwin J. D., Basic Engineering Circuit Analysis, Macmillan, 1990
4. Nilsson & Riedel, Using Computer Tools for Electric Circuits (5e), AW, 1996.
5. G. W. Roberts and A.S. Sedra, SPICE (2e), OUP, 1997
Dept. of E&C, NITK Surathkal 4
5. Linear Systems & Signals Laboratory
1.1 Getting Started
• Using Windows Explorer, create a folder EC09xx_yy in the directory
d:scslabdayofweek
• Invoke Capture Lite Edition OrCAD Capture window appears.
Steady state analysis
Objective: Familiarise with PSpice Circuit simulation environment
DC and AC steady state analysis using PSpice.
1.2 DC Steady state analysis
1. Find the load voltage and load current of the circuit shown in Fig. 1.2.1
Fig. 1.2.1
A. Drawing the schematic
File → New → Project ; Create a new project : Analog or Mixed A/D; Specify name of project
and location (your user directory) – Create a blank project - Worksheet appears
i. Get all components and place them in the worksheet .
Place → Part → Part - R (analog.olb library)
Place the resistor that appears at all the places where it is necessary on the schematic
by left mouse click. To turn the resistor by 90°, press Cntl+R. When all the five
resistors have been placed press ESC. The resistors are having labels R1, R2 …R5.
To change the resistance value double click on the value on the screen, type the value
required in value dialog box.
Similarly get the current sources (ISRC) and voltage source (VSRC) from the
library source.olb and place them on the schematic. To set the value for the sources
double click DC=, and type the value in the window provided and press Enter. We
need to bring GND also for reference. Place → Ground → Change its name to 0
ii. Connect all components as in circuit diagram Place → Wire
iii. Save the schematic in your directory
Dept. of E&C, NITK Surathkal 5
6. Linear Systems & Signals Laboratory
B. Analysis
i. Pspice Create netlist
ii. To set up a PSpice simulation, click on "PSpice" and then select "New Simulation
Profile". Enter a filename for the simulation, e.g., dc_bias. Click on "Create" and then
choose the "Bias Point" option in the window that pops up. Leave the checkmark
options blank. In Probe Window → Disable Display Probe Window
iii.Pspice Run
C. Results
If simulation is performed correctly, the results are displayed on the schematic. Use the "V",
"I" and "W" buttons on the horizontal menu bar to turn the voltage, current, and power results
on or off.
Load Current = 3A and load Voltage = 6V. Examine the output file Pspice View output
file and netlist file Pspice
View netlist created at the end of simulation.
2. Find the galvanometer current in the circuit of Fig. 1.2.2
Fig. 1.2.2
Remember to GND one of the terminals as all node voltages are measures with respect to
this node
3. For the circuit shown in Fig. 1.2.3
Vy (5V)
1 R1 2 R3
R2 800
1k
R4 R5
+ 3
200 Is
(20V) V3 100
(10V) 50 mA
Vx
Fig. 1.2.3
Obtain 1. Steady state node voltages, loop currents and hence verify KVL & KCL
2. Power drawn from all voltage sources
Dept. of E&C, NITK Surathkal 6
7. Linear Systems & Signals Laboratory
4. Find the node voltages v1, v2, v3 in the circuit given in Fig. 1.2.4. Also find the total
power dissipated in the circuit.
v1 25Ω v2 50Ω v3 20Ω
io
5Ω
2io
100Ω 200Ω 38.5V
5io
Fig. 1.2.4
The controlled sources are available in analog.olb library – E (VCVS), F (CCCS), G(VCCS),
and H (CCVS). Make appropriate connections.
The values of elements can be specified using scaling factors (upper or lower case):
T or Tera (= 1E12); G or Giga (= E9); MEG or Mega (= E6);
K or Kilo (= E3); M or Milli (= E-3); U or Micro (= E-6);
N or Nano (= E-9); P or Pico (= E-12) F of Femto (= E-15)
As an example, one can specify a capacitor of 225 picofarad in the following ways:
225P, 225p, 225pF; 225pFarad; 225E-12; 0.225N
5. Find the Thevenin equivalent circuit with respect to the terminals a,b for the circuit given
in Fig, 1.2.5
20Ω 160 io
a
4A
60Ω
io
80 Ω 40Ω
b
Fig. 1.2.5
Find VTH by measuring the Open Circuit Voltage – For open circuit : Insert a resistor of big
value, like 1 MEG and find the voltage at the terminal
Apply “Short Circuit Method” for RTH – For short circuit : Insert a resistor of very little
value, like 1u and find the current through this resistor
Troubleshooting tips
If an error window pops up when you try to simulate, you need to identify which pin is
“floating” i.e. not connected properly to the circuit and link it up with a wire.
When every connection seems OK but there is a consistent error message - the best way is to
erase all the wires, while keeping the elements, then re-wire.
Dept. of E&C, NITK Surathkal 7
8. Linear Systems & Signals Laboratory
6. DC Sweep Analysis
Study the effect of varying the voltage V1 in Fig. 1.2.6 from 0 to 20V in steps of 0.1V
Draw the schematic. Create a new simulation profile. Select DC Sweep. Enter the name
of the voltage source to be swept: V1. The start and end values and the step need to be
specified: 0, 20 and 0.1V, respectively. Run the simulation. PSpice will generate an
output file that contains the values of all voltages and currents in the circuit. PSpice has
a user-friendly interface to show the results of the simulations. Once the simulation is
finished a Probe window will open. From the TRACE menu select ADD TRACE and select
the voltages and current you like to display. You can also add traces using the
"Voltage/Current/Power Markers" and “ in the schematic.
10kΩ
1mA
V1
5uF
10kΩ
Fig. 1.2.6
You can assign names to nets or nodes using the Place Net Alias command
7. In the circuit given in Fig. 1.2.7 use PSpice to find the maximum power deliverable to RL.
1k
1V RL
Fig. 1.2.7
Define the value of RL as a parameter – Double click the value of resistor RL and in the
Value box enter {RL}. Note the curly braces are necessary. Next step is to define
parameter. Select Place/Part/PARAM (library – special.olb).
Double click on the PARAM part. This will open a spreadsheet like window showing
the PARAM definition. You will need to add a new column to this spread sheet. Click
on NEW COLUMN and enter for Property Name, RL, enter an initial value for the
resistor 2k. Select the RL column and click the DISPLAY button. You can now specify
what to display: select Name and Value.
Create a new simulation profile. Select DC Sweep. For Sweep Variable select Global
Parameter. In the Parameter Name box enter RL. The start and end values and the step
need to be specified: 100, 5k, 100 respectively. Run Simulation and plot Power across
RL vs RL.
Dept. of E&C, NITK Surathkal 8
9. Linear Systems & Signals Laboratory
1.3 AC Steady State Analysis
1. Find the output voltage Vo of the circuit of Fig. 1.3.1.
Fig 1.3.1
Draw the schematic of the given circuit.
• For AC Voltage source V1, get part VAC and set value AC = 11.3V 45DEG
• For AC Current source I1, get part IAC and set value AC = 4A 0DEG
• To measure output voltage, connect VPRINT1 (special.slb) to the output node. For the
symbol VPRINT1, set value of AC, MAG, and PHASE to any non-blank value, such
as Y, YES or 1.
• Analysis → Setup → AC Sweep → Enabled → Linear, Start frequency = 400, End
Freq. = 400, No of points = 1
• Analysis → Simulate → Examine output
Results: FREQ = 400 VM(C1) = 4.524E+00 VP(C1) = -7.599E+01
2. Find the potential difference between the nodes A and B of the circuit of Fig. 1.3.2
Fig 1.3.2
Analysis may be carried out assuming ω =1 rad/sec, ie. f =1/2π. At this frequency L=XL
and C=1/XC
Dept. of E&C, NITK Surathkal 9
10. Linear Systems & Signals Laboratory
1.4 Analysis of coupled circuits
1. Find the voltage across the capacitor in the circuit of Fig. 1.4.1.
Fig.1.4.1
- Draw the schematic of the given circuit.
- For coupled circuit, get part XFRM_LINEAR (analog.slb) and set value Coupling=0.4,
L1 = 5, L2 =5. The first node of L1 and L2 are dotted.
- To measure output voltage, use VPRINT1 (special.slb)
- In Simulation Profile Enable AC Sweep → Linear, Start Freq. = 0.159115, End Freq. =
.159115, No of points = 1
Results: FREQ = 1.591E-01 VM(C1) = 1.015E+01 VP(C1) = 2.397E+01
2. Find the current delivered by the source in the circuit of Fig. 1.4.2
Fig. 1.4.2
Dept. of E&C, NITK Surathkal 10