This document describes a lab report on modeling in SPICE. It includes:
1) Testing the validity of an NMOS transistor model by comparing hand calculations of drain currents to SPICE simulation results.
2) Finding accurate MOSFET model parameters by matching measured data to equations and simulations.
3) Evaluating a CMOS inverter model in SPICE by analyzing its digital characteristics.
4) Comparing CMOS and BJT TTL inverter models in SPICE to determine modeling usefulness.
A Temperature-insensitive Simple Current-mode Multiplier/Divider Employing On...IDES Editor
This article presents a new current-mode
multiplier/divider based on MO-CDTA (Multiple output
current conveyor transconductance amplifier). The circuit
description is very simple, its construction consists of only
one MO-CDTA. Without external passive elements, the
proposed circuit is then suitable for IC architecture. The
PSpice simulation and experimental results are depicted, and
agree well with the theoretical anticipation. From simulation
results, the maximum power consumption is approximately
2.14mW at ±2V power supply voltages.
This document discusses the challenges of verifying mixed-signal integrated circuits. It presents how Freescale used Cadence eManager and a variety of modeling and simulation techniques to verify a sensor IC. They took a progressive approach starting with digital simulations using wreal models for speed and then incorporating more accurate Verilog-AMS and transistor-level models. They were able to set up a single simulation environment in eManager to run analog, digital and mixed-signal simulations. The document discusses using control-oriented and data-oriented functional coverage to ensure the chip's functionality was verified.
The document discusses programming microcontrollers for embedded systems. It provides examples of interfacing multiple switches to a single pin of a microcontroller and configuring the microcontroller's analog-to-digital converter (ADC). The examples demonstrate starting and stopping the ADC, reading ADC values, and setting the ADC prescaler and reference voltages. Practical programming techniques are presented for reading sensor inputs using the ADC to acquire data from the real world.
Linear Ic Applications Jntu Model Paper{Www.Studentyogi.Com}guest3f9c6b
This document contains questions from past exam papers for the subject "Linear IC Applications". It includes 8 questions related to topics like differential amplifiers, op-amps, filters, oscillators, timers, DACs, ADCs and multiplexers. Students are required to answer any 5 questions out of the 8 questions provided. The questions test the students' understanding of circuit analysis and design of various applications using linear integrated circuits.
Analog & Digital Integrated Circuits (Question Bank)Mathankumar S
This document contains question banks for the subject Analog & Digital Integrated Circuits. It is divided into 5 units covering topics such as operational amplifiers, phase locked loops, ADCs and DACs, Boolean algebra, combinational logic circuits, sequential logic circuits and flip-flops. The question bank contains objective type questions to test knowledge as well as longer questions requiring explanations and circuit design to test comprehension. It aims to provide a comprehensive set of practice questions covering the key concepts of the subject.
This document describes an experiment to demonstrate pulse-code modulation (PCM) using an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The objectives are to encode and decode analog signals using PCM and demonstrate how the sampling rate affects the reproduction of analog signals. The experiment uses an 8-bit ADC to sample an analog input signal and convert it to an 8-bit digital code. The digital output is then converted back to an analog signal using an 8-bit DAC. A low-pass filter is used to smooth the staircase output of the DAC into a representation of the original analog input signal.
1) The experiment demonstrated pulse code modulation (PCM) encoding using an analog-to-digital converter (ADC) and decoding using a digital-to-analog converter (DAC).
2) The sampling frequency determined by the pulse generator was measured to be 250 kHz, which was higher than twice the analog input frequency, satisfying the Nyquist criterion.
3) After low-pass filtering the DAC output, the waveform was smoothed into a close approximation of the original analog input signal.
A Temperature-insensitive Simple Current-mode Multiplier/Divider Employing On...IDES Editor
This article presents a new current-mode
multiplier/divider based on MO-CDTA (Multiple output
current conveyor transconductance amplifier). The circuit
description is very simple, its construction consists of only
one MO-CDTA. Without external passive elements, the
proposed circuit is then suitable for IC architecture. The
PSpice simulation and experimental results are depicted, and
agree well with the theoretical anticipation. From simulation
results, the maximum power consumption is approximately
2.14mW at ±2V power supply voltages.
This document discusses the challenges of verifying mixed-signal integrated circuits. It presents how Freescale used Cadence eManager and a variety of modeling and simulation techniques to verify a sensor IC. They took a progressive approach starting with digital simulations using wreal models for speed and then incorporating more accurate Verilog-AMS and transistor-level models. They were able to set up a single simulation environment in eManager to run analog, digital and mixed-signal simulations. The document discusses using control-oriented and data-oriented functional coverage to ensure the chip's functionality was verified.
The document discusses programming microcontrollers for embedded systems. It provides examples of interfacing multiple switches to a single pin of a microcontroller and configuring the microcontroller's analog-to-digital converter (ADC). The examples demonstrate starting and stopping the ADC, reading ADC values, and setting the ADC prescaler and reference voltages. Practical programming techniques are presented for reading sensor inputs using the ADC to acquire data from the real world.
Linear Ic Applications Jntu Model Paper{Www.Studentyogi.Com}guest3f9c6b
This document contains questions from past exam papers for the subject "Linear IC Applications". It includes 8 questions related to topics like differential amplifiers, op-amps, filters, oscillators, timers, DACs, ADCs and multiplexers. Students are required to answer any 5 questions out of the 8 questions provided. The questions test the students' understanding of circuit analysis and design of various applications using linear integrated circuits.
Analog & Digital Integrated Circuits (Question Bank)Mathankumar S
This document contains question banks for the subject Analog & Digital Integrated Circuits. It is divided into 5 units covering topics such as operational amplifiers, phase locked loops, ADCs and DACs, Boolean algebra, combinational logic circuits, sequential logic circuits and flip-flops. The question bank contains objective type questions to test knowledge as well as longer questions requiring explanations and circuit design to test comprehension. It aims to provide a comprehensive set of practice questions covering the key concepts of the subject.
This document describes an experiment to demonstrate pulse-code modulation (PCM) using an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The objectives are to encode and decode analog signals using PCM and demonstrate how the sampling rate affects the reproduction of analog signals. The experiment uses an 8-bit ADC to sample an analog input signal and convert it to an 8-bit digital code. The digital output is then converted back to an analog signal using an 8-bit DAC. A low-pass filter is used to smooth the staircase output of the DAC into a representation of the original analog input signal.
1) The experiment demonstrated pulse code modulation (PCM) encoding using an analog-to-digital converter (ADC) and decoding using a digital-to-analog converter (DAC).
2) The sampling frequency determined by the pulse generator was measured to be 250 kHz, which was higher than twice the analog input frequency, satisfying the Nyquist criterion.
3) After low-pass filtering the DAC output, the waveform was smoothed into a close approximation of the original analog input signal.
This document is the final lab assignment for the course EE312 Embedded Microcontrollers at Colorado Technical University in Spring 2009. The lab covers modular programming with an MC68HC11 microcontroller board, demonstrating various instructions including load, add, subtract, store, multiply, divide, branch, jump, return, decrement, increment, rotate, shift, push, pull, transfer, clear, logic operations, and more. It is authored by Loren K. Schwappach and due on May 18, 2009.
This email encourages ECG employees to continue developing ethical behaviors and complying with the new code of conduct. It highlights the success of recent ethics training and the compliance hotline. It stresses that leaders must communicate and motivate ethical practices. All employees should aim for ethical conduct in their work, which benefits their careers and protects the company. Upcoming mandatory training called "Ethic Rock Star" will provide role-playing scenarios to further practice ethical decision making.
The document discusses the stakeholders of the SCRMP Project at HLR Inc. The SCRMP Project aims to create a standardized customer relationship management system. Key stakeholders include HLR Inc., customers, employees in various departments, the software developer, project leadership, and the IT department. The project sponsor is likely the Chief Information Officer who first initiated the project and is providing executive support. Proper identification of all stakeholders is important for project requirements and success.
The document describes designing and simulating an analog switch in L-Edit and PSpice. Key steps include:
1) Calculating the required widths and lengths of nFET and pFET devices to achieve an on-resistance of 400 ohms or less.
2) Laying out the design in L-Edit according to these dimensions.
3) Performing design rule checks and extracting the layout for PSpice simulation.
4) Simulating the switch in PSpice to verify switching operation, resistance, and bandwidth meet specifications.
Ee 352 lab 1 (tutorial) - schwappach - 15 oct 09Loren Schwappach
This document provides instructions for an individual lab tutorial on digital design using Aldec's Active-HDL software. The tutorial covers:
1) Creating a new workspace and design.
2) Using the Verilog source code wizard to generate a new source file for a 10-bit counter module.
3) Examining the top-level diagram, schematic, and state diagram generated for the counter design.
4) Simulating the design and debugging any issues.
This document assigns roles and responsibilities to team members for an IRTC billing system upgrade project. Terry is assigned as the team leader due to her technical background and experience managing prior projects. Robin is selected as the business analyst for her work on previous upgrades. Chris is the lead software engineer and will work closely with a vendor programmer. Jan is the end user/tester to represent customer needs and test requirements. The roles of each team member are described in detail, along with their relevant experience and expected time commitment to the project.
Gothic architecture originated in France in the early 13th century and was characterized by pointed arches, ribbed vaults, flying buttresses, and stained glass windows. One of the most famous examples is Notre Dame Cathedral in Chartres, which perfectly exemplifies Gothic design elements and features an elaborate floor plan laid out in the shape of a cross. Gothic cathedrals used architectural innovations to raise vaulted ceilings to unprecedented heights and fill the structures with colorful light from stained glass.
The document describes an 8-bit pipelined analog-to-digital converter (ADC) with a selectable resolution of 5-8 bits. The ADC was fabricated in a 0.13-micron CMOS process and achieves an effective number of bits of 6.10 in 8-bit mode with a 162 MHz input signal. Key aspects of the ADC include double sampling to relax amplifier settling times, redundant sign digit correction to compensate comparator offsets, and a two-stage op-amp design to provide sufficient gain and signal headroom given the low 1.2V supply voltage. Measured performance meets the requirements for medium resolution and sampling rate ADCs in modern synthetic aperture radar systems.
This lab report examines two multi-stage BJT amplifier circuits (cascade and cascode) through simulation, calculation, and physical experimentation. Hand calculations, PSpice simulation, and experimental results showed close agreement for voltages, currents, and gains. The cascade circuit used one NPN and one PNP transistor in common-emitter configurations. The cascode used two NPN transistors in a transconductance amplifier followed by a current buffer. Both circuits demonstrated voltage and current amplification as intended. Minor discrepancies between simulation, calculation and experiment were due to component tolerances and measurement errors.
The document provides information about the Linear Systems and Signals Laboratory course conducted at the National Institute of Technology Karnataka, Surathkal. It contains two modules - Circuit Simulation using PSPICE and Simulation using MATLAB/SIMULINK. The objectives of the course are to introduce circuit analysis using PSPICE and modeling/simulation of signals and systems using MATLAB and SIMULINK. The document describes the evaluation plan and weekly schedule of the course.
The manual is very useful for UG EEE students for the subject Power Electronics
By
M.MURUGANANDAM. M.E.,(Ph.D).,MIEEE.,MISTE,
Assistant Professor & Head / EIE,
Muthayammal Engineering College,
Rasipuram,
Namakkal-637 408.
Cell No: 9965768327
This document provides instructions for an embedded systems lab experiment involving controlling LED lights using a light dependent resistor (LDR) sensor and a PIC18F4550 microcontroller. The objectives are to learn how to design embedded systems circuits, initialize a microcontroller, and program the PIC18F4550 to control LEDs based on light intensity readings from the LDR sensor. Students will write a program to read analog voltage values from the LDR, map those values to 3 modes of LED operation, and switch the LEDs accordingly. They will test their designed circuit and program, and answer questions about varying the light intensity, measuring resistances and voltages for each mode.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time
variation on switching losses in a Zero Voltage Switching
(ZVS) synchronous buck converter (SBC) circuit. In high
frequency converter circuits, switching losses are
commonly linked with high and low side switches of SBC
circuit. They are activated externally by the gate driver
circuit. The duty ratio, dead time and resonant inductor
are the parameters that affect the efficiency of the circuit.
These variables can be adjusted for the optimization
purposes. The study primarily focuses on varying the
settings of input pulses of the MOSFETs in the resonant
gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter
circuit. Using the predetermined inductor of 9 nH, the
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and
compared to the findings from previous work. It has
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
SBC design.
An approach to design Flash Analog to Digital Converter for High Speed and Lo...VLSICS Design
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
Simulating Ideal and Non-ideal Behavior of N-Channel MOSFET using Python Prog...IRJET Journal
This document describes simulations of the ideal and non-ideal behavior of an N-channel MOSFET using Python programming. It first discusses the ideal behavior, modeling the three regions of operation - cutoff, linear, and saturation. It then discusses modeling non-ideal effects, including channel length modulation, body effect, and subthreshold conduction. The Python program uses Tkinter for a graphical interface to allow inputting parameters and viewing output graphs of drain current versus voltage to compare ideal and non-ideal device characteristics. The simulations help provide a more practical understanding of how parameters affect real-world MOSFET operation.
4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayannazrulanuar
The document summarizes a paper on Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL). It introduces 2PASCL, which uses adiabatic switching to reduce power dissipation. It describes the principle and analysis of 2PASCL, presents application circuits including a 4-bit adder and 4x4-bit multiplier, and discusses the LSI implementation of a 4x4-bit 2PASCL multiplier chip in a 1.2um CMOS process. Simulation and measurement results show the 2PASCL circuits dissipate 35-77% less power compared to equivalent CMOS designs.
This document compares level 1, 2, and 3 MOSFET models in SPICE simulations. It provides background on device modeling and outlines the key equations that define each model level. Level 1 is the simplest model and does not account for short channel effects. Level 2 includes mobility degradation and threshold voltage variations. Level 3 has similar accuracy to level 2 but faster simulation time and better convergence. Drain current versus drain-source voltage characteristics are plotted to show differences between the models.
This document describes a lab report for analyzing the characteristics of an NMOS inverter using the IRF-150 power MOSFET in PSpice. The objectives are to learn how to use PSpice and analyze key characteristics of the IRF-150 inverter circuit. The report includes the circuit schematics and simulation results for generating characteristic curves of the MOSFET, analyzing the voltage transfer function, frequency response, propagation delays, and maximum operating frequency of the circuit.
The manual is useful for PG students belongs to ME power Electronics and Drives
By
M.MURUGANANDAM. M.E.,(Ph.D).,MIEEE.,MISTE,
Assistant Professor & Head / EIE,
Muthayammal Engineering College,
Rasipuram,
Namakkal-637 408.
Cell No: 9965768327
Write your own generic SPICE Power Supplies controller modelsTsuyoshi Horigome
This document discusses writing generic SPICE models for power supply controllers. It begins by explaining that exact SPICE models may not exist or be compatible with the user's simulator. The solution is to write a generic model and adapt it to the specific controller. It then provides examples of using behavioral (B) elements to model nonlinear functions like comparators and logic gates in different simulators like ISspice, PSpice, and AWB. Guidelines are given for writing models step-by-step, including using subcircuits and descriptive names. Finally, it discusses modeling a constant frequency current mode PWM controller as an example application.
IRJET- Implementation of Low Power Flash ADC using Adiabatic Logic based Doub...IRJET Journal
This document describes the implementation of a low power flash analog-to-digital converter (ADC) using an adiabatic logic based double tail comparator. It first provides background on flash ADCs and their components. It then discusses resistor ladder networks, comparators including single tail, conventional double tail, and dynamic double tail comparator designs. It proposes using an adiabatic logic approach to design a double tail comparator for reduced power consumption. The flash ADC would combine the resistor ladder, adiabatic logic comparator, and a fat tree encoder. Simulation results showed the circuit could operate with a 1.2V supply voltage.
A 130-NM CMOS 400 MHZ 8-Bit Low Power Binary Weighted Current Steering DAC ijcisjournal
A low power low voltage 8-bit Digital to Analog Converter consisting of different current sources in binary
weighted array architecture is designed. The weights of current sources are depending on the binary
weights of the bits. This current steering DAC is suitable for high speed applications. The proposed DAC in
this paper has DNL, INL of ±0.04, ±0.05 respectively and the power consumption of 16.67mw.
This binary array architecture is implemented in CMOS 0.13µm 1P2M technology has good performances
in DNL, INL and area compared with other researches.
This document is the final lab assignment for the course EE312 Embedded Microcontrollers at Colorado Technical University in Spring 2009. The lab covers modular programming with an MC68HC11 microcontroller board, demonstrating various instructions including load, add, subtract, store, multiply, divide, branch, jump, return, decrement, increment, rotate, shift, push, pull, transfer, clear, logic operations, and more. It is authored by Loren K. Schwappach and due on May 18, 2009.
This email encourages ECG employees to continue developing ethical behaviors and complying with the new code of conduct. It highlights the success of recent ethics training and the compliance hotline. It stresses that leaders must communicate and motivate ethical practices. All employees should aim for ethical conduct in their work, which benefits their careers and protects the company. Upcoming mandatory training called "Ethic Rock Star" will provide role-playing scenarios to further practice ethical decision making.
The document discusses the stakeholders of the SCRMP Project at HLR Inc. The SCRMP Project aims to create a standardized customer relationship management system. Key stakeholders include HLR Inc., customers, employees in various departments, the software developer, project leadership, and the IT department. The project sponsor is likely the Chief Information Officer who first initiated the project and is providing executive support. Proper identification of all stakeholders is important for project requirements and success.
The document describes designing and simulating an analog switch in L-Edit and PSpice. Key steps include:
1) Calculating the required widths and lengths of nFET and pFET devices to achieve an on-resistance of 400 ohms or less.
2) Laying out the design in L-Edit according to these dimensions.
3) Performing design rule checks and extracting the layout for PSpice simulation.
4) Simulating the switch in PSpice to verify switching operation, resistance, and bandwidth meet specifications.
Ee 352 lab 1 (tutorial) - schwappach - 15 oct 09Loren Schwappach
This document provides instructions for an individual lab tutorial on digital design using Aldec's Active-HDL software. The tutorial covers:
1) Creating a new workspace and design.
2) Using the Verilog source code wizard to generate a new source file for a 10-bit counter module.
3) Examining the top-level diagram, schematic, and state diagram generated for the counter design.
4) Simulating the design and debugging any issues.
This document assigns roles and responsibilities to team members for an IRTC billing system upgrade project. Terry is assigned as the team leader due to her technical background and experience managing prior projects. Robin is selected as the business analyst for her work on previous upgrades. Chris is the lead software engineer and will work closely with a vendor programmer. Jan is the end user/tester to represent customer needs and test requirements. The roles of each team member are described in detail, along with their relevant experience and expected time commitment to the project.
Gothic architecture originated in France in the early 13th century and was characterized by pointed arches, ribbed vaults, flying buttresses, and stained glass windows. One of the most famous examples is Notre Dame Cathedral in Chartres, which perfectly exemplifies Gothic design elements and features an elaborate floor plan laid out in the shape of a cross. Gothic cathedrals used architectural innovations to raise vaulted ceilings to unprecedented heights and fill the structures with colorful light from stained glass.
The document describes an 8-bit pipelined analog-to-digital converter (ADC) with a selectable resolution of 5-8 bits. The ADC was fabricated in a 0.13-micron CMOS process and achieves an effective number of bits of 6.10 in 8-bit mode with a 162 MHz input signal. Key aspects of the ADC include double sampling to relax amplifier settling times, redundant sign digit correction to compensate comparator offsets, and a two-stage op-amp design to provide sufficient gain and signal headroom given the low 1.2V supply voltage. Measured performance meets the requirements for medium resolution and sampling rate ADCs in modern synthetic aperture radar systems.
This lab report examines two multi-stage BJT amplifier circuits (cascade and cascode) through simulation, calculation, and physical experimentation. Hand calculations, PSpice simulation, and experimental results showed close agreement for voltages, currents, and gains. The cascade circuit used one NPN and one PNP transistor in common-emitter configurations. The cascode used two NPN transistors in a transconductance amplifier followed by a current buffer. Both circuits demonstrated voltage and current amplification as intended. Minor discrepancies between simulation, calculation and experiment were due to component tolerances and measurement errors.
The document provides information about the Linear Systems and Signals Laboratory course conducted at the National Institute of Technology Karnataka, Surathkal. It contains two modules - Circuit Simulation using PSPICE and Simulation using MATLAB/SIMULINK. The objectives of the course are to introduce circuit analysis using PSPICE and modeling/simulation of signals and systems using MATLAB and SIMULINK. The document describes the evaluation plan and weekly schedule of the course.
The manual is very useful for UG EEE students for the subject Power Electronics
By
M.MURUGANANDAM. M.E.,(Ph.D).,MIEEE.,MISTE,
Assistant Professor & Head / EIE,
Muthayammal Engineering College,
Rasipuram,
Namakkal-637 408.
Cell No: 9965768327
This document provides instructions for an embedded systems lab experiment involving controlling LED lights using a light dependent resistor (LDR) sensor and a PIC18F4550 microcontroller. The objectives are to learn how to design embedded systems circuits, initialize a microcontroller, and program the PIC18F4550 to control LEDs based on light intensity readings from the LDR sensor. Students will write a program to read analog voltage values from the LDR, map those values to 3 modes of LED operation, and switch the LEDs accordingly. They will test their designed circuit and program, and answer questions about varying the light intensity, measuring resistances and voltages for each mode.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time
variation on switching losses in a Zero Voltage Switching
(ZVS) synchronous buck converter (SBC) circuit. In high
frequency converter circuits, switching losses are
commonly linked with high and low side switches of SBC
circuit. They are activated externally by the gate driver
circuit. The duty ratio, dead time and resonant inductor
are the parameters that affect the efficiency of the circuit.
These variables can be adjusted for the optimization
purposes. The study primarily focuses on varying the
settings of input pulses of the MOSFETs in the resonant
gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter
circuit. Using the predetermined inductor of 9 nH, the
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and
compared to the findings from previous work. It has
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
SBC design.
An approach to design Flash Analog to Digital Converter for High Speed and Lo...VLSICS Design
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
Simulating Ideal and Non-ideal Behavior of N-Channel MOSFET using Python Prog...IRJET Journal
This document describes simulations of the ideal and non-ideal behavior of an N-channel MOSFET using Python programming. It first discusses the ideal behavior, modeling the three regions of operation - cutoff, linear, and saturation. It then discusses modeling non-ideal effects, including channel length modulation, body effect, and subthreshold conduction. The Python program uses Tkinter for a graphical interface to allow inputting parameters and viewing output graphs of drain current versus voltage to compare ideal and non-ideal device characteristics. The simulations help provide a more practical understanding of how parameters affect real-world MOSFET operation.
4x4-bit 2PASCL Multiplier by Nazrul Anuar Nayannazrulanuar
The document summarizes a paper on Two-Phase Clocked Adiabatic Static CMOS Logic (2PASCL). It introduces 2PASCL, which uses adiabatic switching to reduce power dissipation. It describes the principle and analysis of 2PASCL, presents application circuits including a 4-bit adder and 4x4-bit multiplier, and discusses the LSI implementation of a 4x4-bit 2PASCL multiplier chip in a 1.2um CMOS process. Simulation and measurement results show the 2PASCL circuits dissipate 35-77% less power compared to equivalent CMOS designs.
This document compares level 1, 2, and 3 MOSFET models in SPICE simulations. It provides background on device modeling and outlines the key equations that define each model level. Level 1 is the simplest model and does not account for short channel effects. Level 2 includes mobility degradation and threshold voltage variations. Level 3 has similar accuracy to level 2 but faster simulation time and better convergence. Drain current versus drain-source voltage characteristics are plotted to show differences between the models.
This document describes a lab report for analyzing the characteristics of an NMOS inverter using the IRF-150 power MOSFET in PSpice. The objectives are to learn how to use PSpice and analyze key characteristics of the IRF-150 inverter circuit. The report includes the circuit schematics and simulation results for generating characteristic curves of the MOSFET, analyzing the voltage transfer function, frequency response, propagation delays, and maximum operating frequency of the circuit.
The manual is useful for PG students belongs to ME power Electronics and Drives
By
M.MURUGANANDAM. M.E.,(Ph.D).,MIEEE.,MISTE,
Assistant Professor & Head / EIE,
Muthayammal Engineering College,
Rasipuram,
Namakkal-637 408.
Cell No: 9965768327
Write your own generic SPICE Power Supplies controller modelsTsuyoshi Horigome
This document discusses writing generic SPICE models for power supply controllers. It begins by explaining that exact SPICE models may not exist or be compatible with the user's simulator. The solution is to write a generic model and adapt it to the specific controller. It then provides examples of using behavioral (B) elements to model nonlinear functions like comparators and logic gates in different simulators like ISspice, PSpice, and AWB. Guidelines are given for writing models step-by-step, including using subcircuits and descriptive names. Finally, it discusses modeling a constant frequency current mode PWM controller as an example application.
IRJET- Implementation of Low Power Flash ADC using Adiabatic Logic based Doub...IRJET Journal
This document describes the implementation of a low power flash analog-to-digital converter (ADC) using an adiabatic logic based double tail comparator. It first provides background on flash ADCs and their components. It then discusses resistor ladder networks, comparators including single tail, conventional double tail, and dynamic double tail comparator designs. It proposes using an adiabatic logic approach to design a double tail comparator for reduced power consumption. The flash ADC would combine the resistor ladder, adiabatic logic comparator, and a fat tree encoder. Simulation results showed the circuit could operate with a 1.2V supply voltage.
A 130-NM CMOS 400 MHZ 8-Bit Low Power Binary Weighted Current Steering DAC ijcisjournal
A low power low voltage 8-bit Digital to Analog Converter consisting of different current sources in binary
weighted array architecture is designed. The weights of current sources are depending on the binary
weights of the bits. This current steering DAC is suitable for high speed applications. The proposed DAC in
this paper has DNL, INL of ±0.04, ±0.05 respectively and the power consumption of 16.67mw.
This binary array architecture is implemented in CMOS 0.13µm 1P2M technology has good performances
in DNL, INL and area compared with other researches.
Assignment 1 Description Marks out of Wtg() Due date .docxfredharris32
Assignment 1
Description Marks out of Wtg(%) Due date
Assignment 1 200 20 28 August 2015
Part A: Comparators and Switching (5%)
(1) Signal limit detector
Use a 339 comparator, a single 74LS02 quad NOR gate and a +5V power supply only to
design a circuit which will detect when a voltage goes outside the range +2.5V to +3.5V
and such that an LED lights and stays lit. Provide a manual reset to extinguish the LED.
Design hints
1. The circuit has an analog input and a digital output so some form of comparator circuit
is required. There are two thresholds so two comparators are required, with the analog
input applied to both. This arrangement is sometimes known as a window detector.
2. Arrange the output of the comparators to be +5V logic levels, and combine the two
outputs logically to produce one signal which is for example, high for out-of-range, and
low for within-range.
3. Latch the change from in-range to out-of-range.
Design procedure
1. Start at the output and work backwards.
2. Select a latch circuit (flip-flop) and determine what combinations of inputs are needed to
latch and then reset it, ensuring that the LED is connected correctly with regard to both
logic and current flow.
3. Determine the logic needed to combine two comparator outputs in such a way as to
correctly operate the latch.
4. Choose comparator outputs which will correctly drive the logic. Remember that the
reference voltage at the input of the comparator may be at either the + or – input.
5. Choose resistors to provide the correct reference voltages.
Note: You will need to consult data for both the 74LS02 and the 339 (see data sheets).
Test
It is strongly recommended that you assemble and test your circuit.
(2) MOSFET Switching
Find out information on the operation of, and configuring of, MOSFETs to be used in
switching circuits. In particular note the differences between BJTs and MOSFETs in this
role. Draw up a table to highlight the differences and hence the pros and cons on each
device for particular situations (eg. Switching high-to-low or low-to-high (ie. P or N type),
high or low current switching, low or high voltage switching).
Consider the following BJT switching circuit. Analyse the operation of the circuit to
understand the parameters involved. Choose suitable replacement MOSFETs to be used
ELE2504 – Electronic design and analysis 2
instead of the output switching BJTs in the given circuit. Include any necessary circuit
changes for the new devices to operate so as to maintain the circuit’s required parameters.
Where Vcc = 12V and Relay resistance = 15Ω .
ELE2504 – Electronic design and analysis 3
Part B: Transistor amplifier design (6%)
Design and test a common emitter amplifier using the circuit shown and the selected
specifications.
Specifications
Get your own spec ...
This manual is very much useful for PG students belongs to ME Power Electronics and Drives
By
M.MURUGANANDAM. M.E.,(Ph.D).,MIEEE.,MISTE,
Assistant Professor & Head / EIE,
Muthayammal Engineering College,
Rasipuram,
Namakkal-637 408.
Cell No: 9965768327
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
The document discusses successive approximation analog-to-digital converters (ADCs). It outlines the converter type, provides an example of how successive approximation works using a 10-bit resolution, and discusses literature comparing published ADC designs. It also summarizes the market for ADC ICs, listing major manufacturers and comparing features of Texas Instruments' 6-channel SAR ADCs.
This document discusses the importance of signal integrity simulations for PCB design. It emphasizes that simulations provide solutions to improve performance and reduce costs when done with the right metrics and models. Case studies show how simulations can determine if certain design choices like termination resistors or microstrip vs stripline routing are needed. Good metrics for analysis include noise margin, timing margin, and waveform characteristics. Accurate models of transmission lines, I/O buffers, and packages are also key to get reliable simulation results.
The document provides an overview of the Ubuntu operating system. It discusses Ubuntu's history as a Debian-based Linux distribution first released in 2004. It covers Ubuntu's design principles including its use of the Linux kernel for process management, memory management, and file systems. It also addresses security topics like hacking threats and strategies for hardening Ubuntu systems. Basic commands and utilities included in Ubuntu are outlined.
This document describes the design and simulation of a CMOS NAND gate using L-Edit software. The objectives were to design a NAND gate with a propagation delay of less than 50 ns while carrying a 10 pF load. Calculations were done to determine transistor widths and lengths that would meet these specifications. The gate was designed in L-Edit and passed design rule checks without errors. The gate was then extracted for use in PSpice simulations. Simulations were run to analyze the voltage transfer function, propagation delay, and rise/fall times and compare the results to a commercially available Fairchild CD4011BC NAND gate.
This lab report describes simulations performed in PSpice on a CMOS inverter circuit designed in L-Edit. The objectives are to characterize the voltage transfer function, frequency response, propagation delay, rise/fall times, and output current of the CMOS inverter. Simulations are presented on the inverter's power consumption, small signal characteristics, digital frequency response, maximum operating frequency, and pulse response at various load capacitances. Results are compared to previous NMOS and power MOSFET circuits analyzed in prior labs.
This document is a lab report for analyzing the characteristics of an NMOS inverter circuit designed in L-Edit and simulated in PSpice. The objectives are to gain experience using PSpice and understand the characteristics of an NMOS inverter. The report includes the NMOS inverter design in L-Edit, PSpice simulations to generate characteristic curves, voltage transfer functions, frequency responses, and propagation delays. Results are compared to a previous lab that analyzed an IRF-150 MOSFET inverter circuit.
This lab report investigates the behavior of a simple AC circuit using a resistor and capacitor at various frequencies. Hand calculations using phasor analysis are performed and verified using PSpice simulations. The circuit is then built on a breadboard and measurements are taken with an oscilloscope. The results show the band passing behavior of the circuit due to different input frequencies, with higher frequencies being attenuated by the capacitor.
This lab report investigates calculating time constants and charging/discharging equations for simple and complex RC circuits. Experiments were conducted to verify the time constant equation using simple RC circuits with 10kΩ and 20kΩ resistors. A complex RC circuit was reduced to Thevenin equivalents and verified through measurements. Finally, a simple RC circuit was driven with 1kHz and 10kHz signals to demonstrate frequency response properties.
Ee343 signals and systems - lab 2 - loren schwappachLoren Schwappach
This lab report examines convolution using MATLAB. It defines an impulse response h[n] and uses it to convolve various input signals x[n], including a shifted impulse response, a unit step response, and a rectangular pulse, producing the corresponding output responses y[n]. The MATLAB code generates the input and output signals and plots the results. The output responses are verified by hand calculations of the convolution, showing MATLAB produces correct results. The lab demonstrates how MATLAB can efficiently perform and visualize discrete-time convolution.
Ee343 signals and systems - lab 1 - loren schwappachLoren Schwappach
This lab report examines using MATLAB to create and visualize continuous-time and discrete-time signals. The student first creates a discrete-time step function by defining values in a MATLAB array. They then plot a continuous-time sinusoidal function by defining the function and plotting it against time. Finally, they take the continuous-time function and represent it discretely in MATLAB by sampling the function at time intervals. The student was able to successfully complete all parts of the lab and visualize the signals in MATLAB.
This lab report examines a BJT amplifier circuit. The objectives were to design the circuit and understand its gain, input/output resistances, and frequency bandwidth. Calculations, PSpice simulations, and experimental results were completed. The calculations, simulations, and experiments all showed similar but not identical results, due to component tolerances and equipment calibration. The final circuit achieved a gain close to the target of 7.
This lab report investigates the design and implementation of a DC power supply in three stages. The first stage uses a bridge rectifier to convert AC to DC but has high ripple. The second stage adds a filter capacitor to reduce ripple. Measurements show ripple is reduced to within specifications. The third stage adds a Zener diode to regulate the output voltage to around 10V. Hand calculations, PSpice simulations, and measurements of the built circuit show the design works as intended at each stage. The lab demonstrates the use of diodes in power supply rectification and regulation.
This lab report examines two BJT circuits using an NPN transistor. The first is a common emitter circuit and the second adds an emitter resistor and voltage divider bias. The objective is to analyze, simulate, and test the circuits to understand BJT operation. Initial tests found inaccuracies due to using incorrect transistor beta values. Rechecking the beta improved results to within 10% of calculations. PSpice simulations had larger errors since its beta did not match the physical transistor. Overall the lab helped gain experience with BJT circuit design and analysis.
The document discusses feedback instability in electronic systems. It defines instability as negative feedback becoming positive feedback, causing the system to be unstable. The author provides equations to check for stability using a Nyquist plot or mathematically. Design considerations to add stability include decreasing gain, adding poles, and using compensating capacitors. The author then presents an original unstable 4-pole filter design and a modified stable design that decreases the gain and adds a pole.
This lab report describes building a curve tracer circuit using previous lab designs for an oscillator and integrator. The objectives were to create a 1 kHz oscillator, integrator, step generator, and reset circuit to form a complete curve tracer. Calculations and circuit diagrams are provided for the oscillator and integrator. The procedures outline building these components, with results showing the oscillator and integrator outputs matched expectations. The report discusses modifications made to instructor-provided step generator and reset circuit designs through experimentation in Multisim software.
This lab report describes the design and testing of two oscillators built using operational amplifiers, capacitors, and resistors. The first oscillator was designed to resonate at 200 Hz and the second at 25 kHz. Calculations were performed to determine the resistor values needed. Multisim software was used to simulate the circuits. For the 200 Hz oscillator, increasing the resistor value from the calculated value produced a better frequency result. The 25 kHz oscillator produced a distorted triangular wave rather than a clean square wave due to limitations of the op-amp. Worst case analyses showed the 200 Hz oscillator frequency varied from 164-175 Hz with 20% higher or lower resistor values.
This lab report summarizes experiments conducted with operational amplifiers configured as an inverter, integrator, and differentiator. Three inverting amplifier circuits were designed with gains of 1, 10, and 100. Multisim simulations show the circuits correctly inverted input signals and achieved the designed gains. Bode plots indicate bandwidth decreased as gain increased, but gain bandwidth product increased. Phase plots show the circuits initially produced a 180 degree phase shift but less at higher frequencies due to circuit poles.
The document discusses phase-locked loops (PLLs), including what they are, how they are modeled and operate, properties of PLLs, and applications. A PLL is a negative feedback system that automatically adjusts the frequency and phase of a control signal to match a reference signal. It consists of a phase detector, loop filter, and voltage-controlled oscillator. The document provides examples of modeling and simulating a PLL using Simulink. It also summarizes tests of a PLL design under different conditions and discusses other applications of PLLs beyond frequency demodulation.
Ee443 phase locked loop - paper - schwappach and brandyLoren Schwappach
This document discusses phase-locked loops (PLLs) and their application in frequency modulation (FM) signal demodulation. It contains the following key points:
1. A PLL consists of a voltage-controlled oscillator (VCO), phase detector, and loop filter. The phase detector compares the phase of the VCO output to the modulated input signal and produces an error voltage.
2. The loop filter removes high frequencies from the error voltage to control the VCO frequency. If the VCO and input signals are not phase-locked, the error voltage will adjust the VCO frequency up or down until they are synchronized.
3. When phase-locked, the VCO frequency matches the carrier frequency,
This document is a lab report describing frequency modulation and detection using MATLAB. It includes:
1) Frequency modulating a carrier signal with a message signal in MATLAB and plotting the modulated signal in time and frequency domains using different modulation indexes to demonstrate narrowband, wideband, and carrier-dropped scenarios.
2) Using Simulink to frequency modulate a square wave message onto a carrier signal with a VCO and partially demodulating using slope detection.
3) Generating white noise in MATLAB, plotting it in time and frequency domains, and finding its autocorrelation function.
This lab report demonstrates coherent detection of a message signal from a modulated signal using MATLAB. It shows how to generate a message signal, carrier signal, and their modulation to create a DSB-SC signal. Coherent detection is performed by multiplying the DSB-SC signal with a synchronized local oscillator. The effects of oscillator synchronization errors in frequency and phase are examined. Finally, filtering is applied to recover the original message signal. Simulink is also used to model the coherent detection process for sinusoidal and square wave inputs.
This lab report examines the frequency content of signals using MATLAB. It first analyzes a composite sinusoidal signal made up of two frequencies, plotting the magnitude and power spectrum. It shows the signal contains two peaks at the individual frequencies. It then analyzes a rectangular pulse signal, plotting the magnitude spectrum which takes the form of a sinc function as expected. It also plots the autocorrelation of the pulse signal. The lab report demonstrates using MATLAB to visualize frequency properties of signals.
Northern Engraving | Modern Metal Trim, Nameplates and Appliance PanelsNorthern Engraving
What began over 115 years ago as a supplier of precision gauges to the automotive industry has evolved into being an industry leader in the manufacture of product branding, automotive cockpit trim and decorative appliance trim. Value-added services include in-house Design, Engineering, Program Management, Test Lab and Tool Shops.
Connector Corner: Seamlessly power UiPath Apps, GenAI with prebuilt connectorsDianaGray10
Join us to learn how UiPath Apps can directly and easily interact with prebuilt connectors via Integration Service--including Salesforce, ServiceNow, Open GenAI, and more.
The best part is you can achieve this without building a custom workflow! Say goodbye to the hassle of using separate automations to call APIs. By seamlessly integrating within App Studio, you can now easily streamline your workflow, while gaining direct access to our Connector Catalog of popular applications.
We’ll discuss and demo the benefits of UiPath Apps and connectors including:
Creating a compelling user experience for any software, without the limitations of APIs.
Accelerating the app creation process, saving time and effort
Enjoying high-performance CRUD (create, read, update, delete) operations, for
seamless data management.
Speakers:
Russell Alfeche, Technology Leader, RPA at qBotic and UiPath MVP
Charlie Greenberg, host
Main news related to the CCS TSI 2023 (2023/1695)Jakub Marek
An English 🇬🇧 translation of a presentation to the speech I gave about the main changes brought by CCS TSI 2023 at the biggest Czech conference on Communications and signalling systems on Railways, which was held in Clarion Hotel Olomouc from 7th to 9th November 2023 (konferenceszt.cz). Attended by around 500 participants and 200 on-line followers.
The original Czech 🇨🇿 version of the presentation can be found here: https://www.slideshare.net/slideshow/hlavni-novinky-souvisejici-s-ccs-tsi-2023-2023-1695/269688092 .
The videorecording (in Czech) from the presentation is available here: https://youtu.be/WzjJWm4IyPk?si=SImb06tuXGb30BEH .
Introduction of Cybersecurity with OSS at Code Europe 2024Hiroshi SHIBATA
I develop the Ruby programming language, RubyGems, and Bundler, which are package managers for Ruby. Today, I will introduce how to enhance the security of your application using open-source software (OSS) examples from Ruby and RubyGems.
The first topic is CVE (Common Vulnerabilities and Exposures). I have published CVEs many times. But what exactly is a CVE? I'll provide a basic understanding of CVEs and explain how to detect and handle vulnerabilities in OSS.
Next, let's discuss package managers. Package managers play a critical role in the OSS ecosystem. I'll explain how to manage library dependencies in your application.
I'll share insights into how the Ruby and RubyGems core team works to keep our ecosystem safe. By the end of this talk, you'll have a better understanding of how to safeguard your code.
This talk will cover ScyllaDB Architecture from the cluster-level view and zoom in on data distribution and internal node architecture. In the process, we will learn the secret sauce used to get ScyllaDB's high availability and superior performance. We will also touch on the upcoming changes to ScyllaDB architecture, moving to strongly consistent metadata and tablets.
What is an RPA CoE? Session 1 – CoE VisionDianaGray10
In the first session, we will review the organization's vision and how this has an impact on the COE Structure.
Topics covered:
• The role of a steering committee
• How do the organization’s priorities determine CoE Structure?
Speaker:
Chris Bolin, Senior Intelligent Automation Architect Anika Systems
5th LF Energy Power Grid Model Meet-up SlidesDanBrown980551
5th Power Grid Model Meet-up
It is with great pleasure that we extend to you an invitation to the 5th Power Grid Model Meet-up, scheduled for 6th June 2024. This event will adopt a hybrid format, allowing participants to join us either through an online Mircosoft Teams session or in person at TU/e located at Den Dolech 2, Eindhoven, Netherlands. The meet-up will be hosted by Eindhoven University of Technology (TU/e), a research university specializing in engineering science & technology.
Power Grid Model
The global energy transition is placing new and unprecedented demands on Distribution System Operators (DSOs). Alongside upgrades to grid capacity, processes such as digitization, capacity optimization, and congestion management are becoming vital for delivering reliable services.
Power Grid Model is an open source project from Linux Foundation Energy and provides a calculation engine that is increasingly essential for DSOs. It offers a standards-based foundation enabling real-time power systems analysis, simulations of electrical power grids, and sophisticated what-if analysis. In addition, it enables in-depth studies and analysis of the electrical power grid’s behavior and performance. This comprehensive model incorporates essential factors such as power generation capacity, electrical losses, voltage levels, power flows, and system stability.
Power Grid Model is currently being applied in a wide variety of use cases, including grid planning, expansion, reliability, and congestion studies. It can also help in analyzing the impact of renewable energy integration, assessing the effects of disturbances or faults, and developing strategies for grid control and optimization.
What to expect
For the upcoming meetup we are organizing, we have an exciting lineup of activities planned:
-Insightful presentations covering two practical applications of the Power Grid Model.
-An update on the latest advancements in Power Grid -Model technology during the first and second quarters of 2024.
-An interactive brainstorming session to discuss and propose new feature requests.
-An opportunity to connect with fellow Power Grid Model enthusiasts and users.
Essentials of Automations: Exploring Attributes & Automation ParametersSafe Software
Building automations in FME Flow can save time, money, and help businesses scale by eliminating data silos and providing data to stakeholders in real-time. One essential component to orchestrating complex automations is the use of attributes & automation parameters (both formerly known as “keys”). In fact, it’s unlikely you’ll ever build an Automation without using these components, but what exactly are they?
Attributes & automation parameters enable the automation author to pass data values from one automation component to the next. During this webinar, our FME Flow Specialists will cover leveraging the three types of these output attributes & parameters in FME Flow: Event, Custom, and Automation. As a bonus, they’ll also be making use of the Split-Merge Block functionality.
You’ll leave this webinar with a better understanding of how to maximize the potential of automations by making use of attributes & automation parameters, with the ultimate goal of setting your enterprise integration workflows up on autopilot.
Conversational agents, or chatbots, are increasingly used to access all sorts of services using natural language. While open-domain chatbots - like ChatGPT - can converse on any topic, task-oriented chatbots - the focus of this paper - are designed for specific tasks, like booking a flight, obtaining customer support, or setting an appointment. Like any other software, task-oriented chatbots need to be properly tested, usually by defining and executing test scenarios (i.e., sequences of user-chatbot interactions). However, there is currently a lack of methods to quantify the completeness and strength of such test scenarios, which can lead to low-quality tests, and hence to buggy chatbots.
To fill this gap, we propose adapting mutation testing (MuT) for task-oriented chatbots. To this end, we introduce a set of mutation operators that emulate faults in chatbot designs, an architecture that enables MuT on chatbots built using heterogeneous technologies, and a practical realisation as an Eclipse plugin. Moreover, we evaluate the applicability, effectiveness and efficiency of our approach on open-source chatbots, with promising results.
Discover top-tier mobile app development services, offering innovative solutions for iOS and Android. Enhance your business with custom, user-friendly mobile applications.
inQuba Webinar Mastering Customer Journey Management with Dr Graham HillLizaNolte
HERE IS YOUR WEBINAR CONTENT! 'Mastering Customer Journey Management with Dr. Graham Hill'. We hope you find the webinar recording both insightful and enjoyable.
In this webinar, we explored essential aspects of Customer Journey Management and personalization. Here’s a summary of the key insights and topics discussed:
Key Takeaways:
Understanding the Customer Journey: Dr. Hill emphasized the importance of mapping and understanding the complete customer journey to identify touchpoints and opportunities for improvement.
Personalization Strategies: We discussed how to leverage data and insights to create personalized experiences that resonate with customers.
Technology Integration: Insights were shared on how inQuba’s advanced technology can streamline customer interactions and drive operational efficiency.
AppSec PNW: Android and iOS Application Security with MobSFAjin Abraham
Mobile Security Framework - MobSF is a free and open source automated mobile application security testing environment designed to help security engineers, researchers, developers, and penetration testers to identify security vulnerabilities, malicious behaviours and privacy concerns in mobile applications using static and dynamic analysis. It supports all the popular mobile application binaries and source code formats built for Android and iOS devices. In addition to automated security assessment, it also offers an interactive testing environment to build and execute scenario based test/fuzz cases against the application.
This talk covers:
Using MobSF for static analysis of mobile applications.
Interactive dynamic security assessment of Android and iOS applications.
Solving Mobile app CTF challenges.
Reverse engineering and runtime analysis of Mobile malware.
How to shift left and integrate MobSF/mobsfscan SAST and DAST in your build pipeline.
Skybuffer SAM4U tool for SAP license adoptionTatiana Kojar
Manage and optimize your license adoption and consumption with SAM4U, an SAP free customer software asset management tool.
SAM4U, an SAP complimentary software asset management tool for customers, delivers a detailed and well-structured overview of license inventory and usage with a user-friendly interface. We offer a hosted, cost-effective, and performance-optimized SAM4U setup in the Skybuffer Cloud environment. You retain ownership of the system and data, while we manage the ABAP 7.58 infrastructure, ensuring fixed Total Cost of Ownership (TCO) and exceptional services through the SAP Fiori interface.
LF Energy Webinar: Carbon Data Specifications: Mechanisms to Improve Data Acc...DanBrown980551
This LF Energy webinar took place June 20, 2024. It featured:
-Alex Thornton, LF Energy
-Hallie Cramer, Google
-Daniel Roesler, UtilityAPI
-Henry Richardson, WattTime
In response to the urgency and scale required to effectively address climate change, open source solutions offer significant potential for driving innovation and progress. Currently, there is a growing demand for standardization and interoperability in energy data and modeling. Open source standards and specifications within the energy sector can also alleviate challenges associated with data fragmentation, transparency, and accessibility. At the same time, it is crucial to consider privacy and security concerns throughout the development of open source platforms.
This webinar will delve into the motivations behind establishing LF Energy’s Carbon Data Specification Consortium. It will provide an overview of the draft specifications and the ongoing progress made by the respective working groups.
Three primary specifications will be discussed:
-Discovery and client registration, emphasizing transparent processes and secure and private access
-Customer data, centering around customer tariffs, bills, energy usage, and full consumption disclosure
-Power systems data, focusing on grid data, inclusive of transmission and distribution networks, generation, intergrid power flows, and market settlement data
The Department of Veteran Affairs (VA) invited Taylor Paschal, Knowledge & Information Management Consultant at Enterprise Knowledge, to speak at a Knowledge Management Lunch and Learn hosted on June 12, 2024. All Office of Administration staff were invited to attend and received professional development credit for participating in the voluntary event.
The objectives of the Lunch and Learn presentation were to:
- Review what KM ‘is’ and ‘isn’t’
- Understand the value of KM and the benefits of engaging
- Define and reflect on your “what’s in it for me?”
- Share actionable ways you can participate in Knowledge - - Capture & Transfer
[OReilly Superstream] Occupy the Space: A grassroots guide to engineering (an...Jason Yip
The typical problem in product engineering is not bad strategy, so much as “no strategy”. This leads to confusion, lack of motivation, and incoherent action. The next time you look for a strategy and find an empty space, instead of waiting for it to be filled, I will show you how to fill it in yourself. If you’re wrong, it forces a correction. If you’re right, it helps create focus. I’ll share how I’ve approached this in the past, both what works and lessons for what didn’t work so well.
Must Know Postgres Extension for DBA and Developer during MigrationMydbops
Mydbops Opensource Database Meetup 16
Topic: Must-Know PostgreSQL Extensions for Developers and DBAs During Migration
Speaker: Deepak Mahto, Founder of DataCloudGaze Consulting
Date & Time: 8th June | 10 AM - 1 PM IST
Venue: Bangalore International Centre, Bangalore
Abstract: Discover how PostgreSQL extensions can be your secret weapon! This talk explores how key extensions enhance database capabilities and streamline the migration process for users moving from other relational databases like Oracle.
Key Takeaways:
* Learn about crucial extensions like oracle_fdw, pgtt, and pg_audit that ease migration complexities.
* Gain valuable strategies for implementing these extensions in PostgreSQL to achieve license freedom.
* Discover how these key extensions can empower both developers and DBAs during the migration process.
* Don't miss this chance to gain practical knowledge from an industry expert and stay updated on the latest open-source database trends.
Mydbops Managed Services specializes in taking the pain out of database management while optimizing performance. Since 2015, we have been providing top-notch support and assistance for the top three open-source databases: MySQL, MongoDB, and PostgreSQL.
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Must Know Postgres Extension for DBA and Developer during Migration
4 ee600 lab2_grp
1. LAB 2: MODELING IN SPICE 1
Lab 2: Validity, Accuracy, Appropriateness, and Usefulness of Modeling in SPICE
L. Schwappach, T. Thede, D. Wehnes
EE600: Modern Solid State Devices
Colorado Technical University
15 September 2011
2. LAB 2: MODELING IN SPICE 2
Abstract
This lab report begins by testing the validity of an NMOS (MBreakN) transistor model built
using SPICE. Next, given measured data is matched to a model using appropriate MOSFET
theory and equations as necessary to identify accurate parameter values that will correctly fit the
measured results. Once the parameter values are identified and verified for accuracy using
SPICE the appropriateness of modeling is gauged by using models of an NMOS and PMOS
transistor to build a digital CMOS inverter using SPICE and analyzing the CMOS models digital
characteristics. Finally, the usefulness of modeling is obtained by comparing the CMOS model
digital characteristics to the model of a BJT TTL inverter also built using SPICE.
3. LAB 2: MODELING IN SPICE 3
Table of Contents
Objectives
Theory and Design Approaches / Trade-offs
Circuit Schematics
Analysis
Part a - Validity: Model of a MOSFET Transistor in SPICE
Equations and Given Parameter Values
Hand Calculation Results
SPICE Model Results
Validity Comparison of Model and Hand Calculation Results
Part b – Accuracy: Finding Parameters for Accurate MOSFET Modeling.
Equations and Measured Values
Hand Calculation Results
Using Results in SPICE to Create an Accurate Model
Accuracy Comparison of Model and Measured Values
Part c: Appropriateness: Modeling a CMOS inverter in SPICE
CMOS: DC Analysis
Function
Threshold Voltage
Noise Margins
Power Curve
CMOS: Time Domain Analysis
Propagation Delays
Rise and Fall Times
Max Switching Frequency
CMOS: Frequency Analysis
CMOS: Fanout Analysis
Table of Results
Conclusions
4. LAB 2: MODELING IN SPICE 4
Part d: Usefulness: Comparison of BJT TTL and CMOS Using SPICE Modeling
TTL: DC Analysis
Function
Threshold Voltage
Noise Margins
Power Curve
TTL: Time Domain Analysis
Propagation Delays
Rise and Fall Times
Max Switching Frequency
TTL: Frequency Analysis
Comparison of CMOS and TTL Results
Conclusions
5. LAB 2: MODELING IN SPICE 5
Lab 2: Validity, Accuracy, Appropriateness, and Usefulness of Modeling in SPICE
Objectives
The lab is divided into four parts with different objectives for each part as shown below:
A: The purpose of Lab 2A is to calculate by hand the drain currents Id for various values
of VGS and VDS for a MOSFET in the cut-off, linear and saturation regions of operations. These
calculations will be compared to a SPICE model to verify that the SPICE model is valid.
B: The purpose of Lab 2B is to determine the accuracy of the SPICE model. Measured
values of a MOSFET circuit will be used to hand calculate appropriate input values (VTO, k’
and LAMBDA) for the SPICE model to determine if it provides similar results.
C: The purpose of Lab 2C is to determine if the SPICE model is appropriate for design
efforts by evaluating the digital characteristics of a CMOS inverter. The characteristics to be
evaluated include the voltage transfer, power usage, pulse, frequency response and fanout.
D: The purpose of Lab 2D is to use SPICE modeling to compare two circuits to
determine the usefulness of the SPICE model. The CMOS inverter circuit in Lab 2C will be
compared to a BJT TTL inverter circuit by evaluating the characteristics of each circuit.
Theory and Design Approaches / Trade-offs
There are no specific design requirements for this project since it is not a design project,
but an evaluation of the validity, accuracy, appropriateness, and usefulness of the SPICE model
6. LAB 2: MODELING IN SPICE 6
Circuit Schematics
The schematics for each of the circuits developed in SPICE for each part of the Lab 2 are shown
below:
GND_0
Lab2a VDrain
PSpice Circuit 0Vdc
VGate NMOS
GND_0 I
MbreaknLab2a
0Vdc L = 1u
W = 14u
GND_0 R
1
0
GND_0
Figure 1: MOSFET SPICE NMOS Transistor Model for DC Analysis of Lab 2A
7. LAB 2: MODELING IN SPICE 7
GND_0
Lab2b VDrain
PSpice Circuit 0Vdc
VGate NMOS
GND_0 I
MbreaknLab2a
0Vdc L = 1u
W = 24u
GND_0 R
1
0
GND_0
Figure 2: Modified MOSFET SPICE NMOS Transistor Model for DC Analysis of Lab 2B
8. LAB 2: MODELING IN SPICE 8
GND_0
Vdd
Lab2c CMOS Inverter 5Vdc
PMOS
MbreakpPMOS
W = 24u
L = 1u
Vin
Out
GND_0
0Vdc
NMOS
MbreaknNMOS
GND_0 W = 14u
L = 1u C
90p
0
GND_0 GND_0
Figure 3: CMOS SPICE Model used for DC Analysis of Lab 2C
9. LAB 2: MODELING IN SPICE 9
GND_0
Vdd
Lab2c CMOS Inverter 5Vdc
PMOS
MbreakpPMOS
W = 24u
L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5 NMOS
PER = 10u MbreaknNMOS
PW = 5u W = 14u
TR = .01u L = 1u C
TF = .01u 90p
TD = 2u
GND_0
GND_0 GND_0
0
Figure 4: CMOS SPICE Model used for Time Domain Analysis of Lab 2C
10. LAB 2: MODELING IN SPICE 10
GND_0
Vdd
5Vdc
Lab2c CMOS Inverter
PMOS
MbreakpPMOS
W = 24u
L = 1u
Vin
Out
GND_0
1mVac
2.1771Vdc NMOS
MbreaknNMOS
W = 14u
L = 1u
GND_0 C1
90p
0
GND_0 GND_0
Figure 5: CMOS SPICE Model used for Frequency Analysis of Lab 2C
11. LAB 2: MODELING IN SPICE 11
GND_0
Vdd
5Vdc
Lab2c CMOS Inverter
PMOS PMOS2
MbreakpPMOS MbreakpPMOS
W = 24u W = 24u
L = 1u L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5
PER = 146.19u NMOS NMOS2
PW = 73.095u MbreaknNMOS MbreaknNMOS
TR = 1n W = 14u W = 14u
TF = 1n L = 1u L = 1u
TD = 2u GND_0 C1
90p
0
GND_0 GND_0 GND_0
Figure 6: CMOS SPICE Model used for Fanout Analysis of Lab 2C at
12. LAB 2: MODELING IN SPICE 12
GND_0
Vdd
5Vdc
Lab2c CMOS Inverter
PMOS PMOS2
MbreakpPMOS MbreakpPMOS
W = 24u W = 24u
L = 1u L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5
PER = 1.4619m NMOS NMOS2
PW = 730.95u MbreaknNMOS MbreaknNMOS
TR = 1n W = 14u W = 14u
TF = 1n L = 1u L = 1u
TD = 2u GND_0 C1
90p
0
GND_0 GND_0 GND_0
Figure 7: CMOS SPICE Model used for Fanout Analysis of Lab 2C at
13. LAB 2: MODELING IN SPICE 13
GND_0
Vdd
5Vdc
Lab2c CMOS Inverter
PMOS PMOS2
MbreakpPMOS MbreakpPMOS
W = 24u W = 24u
L = 1u L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5
PER = 14.619u NMOS NMOS2
PW = 7.3095u MbreaknNMOS MbreaknNMOS
TR = 1n W = 14u W = 14u
TF = 1n L = 1u L = 1u
TD = 2u GND_0 C1
90p
0
GND_0 GND_0 GND_0
Figure 8: CMOS SPICE Model used for Fanout Analysis of Lab 2C at
14. LAB 2: MODELING IN SPICE 14
Lab 2d BJT TTL
Vcc R R1 R3
5Vdc 4k 1.6k 130
Q4
Q2N3904
Vin
Q2
Q1 Q2N3904
Q2N3904 D2
0Vdc D1N4001
Out
CL
Q3 90p
Q2N3904
GND_0
R2
1k
0
GND_0
Figure 9: BJT TTL SPICE Model used for DC Analysis of Lab 2D
15. LAB 2: MODELING IN SPICE 15
Lab 2d BJT TTL
Vcc R R1 R3
5Vdc 4k 1.6k 130
Q4
Q2N3904
Vin
Q2
Q1 Q2N3904
V1 = 0 Q2N3904 D2
V2 = 5 D1N4001
PER = 10u
PW = 5u
TR = .01u Out
TF = .01u
TD = 2u
CL
Q3 90p
Q2N3904
GND_0
R2
1k
0
GND_0
Figure 10: BJT TTL SPICE Model used Time Domain Analysis of Lab 2D
16. LAB 2: MODELING IN SPICE 16
Lab 2d BJT TTL
Vcc R R1 R3
5Vdc 4k 1.6k 130
Q4
Q2N3904
Vin
Q2
Q1 Q2N3904
Q2N3904 D2
1mVac D1N4001
1.3925Vdc
Out
CL
Q3 90p
Q2N3904
GND_0
R2
1k
0
GND_0
Figure 11: BJT TTL SPICE Model used Frequency Analysis of Lab 2D
17. LAB 2: MODELING IN SPICE 17
Analysis
Lab 2A - Validity: Model of a MOSFET in SPICE
Equations and Given Parameter Values
A MOSFET transistor has 3 modes of operation: Cut-off mode, Triode or linear mode,
and saturation mode. The mode of operation is determined by the values of (the voltage
from the Gate to Source), (the Voltage from the Gate to Source), (the Threshold
Voltage). The following simplified equations can be utilized to calculate the effects of the drain
current .
When the transistor is in Cut-off mode:
Equation 1: MOSFET in Cut-off Mode
When the transistor is in Triode or Linear mode:
Equation 2: MOSFET in Triode Mode
When the transistor is in Saturation mode:
Where
Equation 3: MOSFET in Saturated Mode
18. LAB 2: MODELING IN SPICE 18
We were also provided with the following parameters:
Parameter values for &
VGS VDS
a) 0.5 V 3.2 V
b) 1.5 V 0.3 V
c) 1.5 V 1.0 V
d) 1.5 V 2.3 V
e) 3.0 V 0.5 V
f) 3.0 V 2.3 V
g) 3.0 V 5.0 V
h) 5.0 V 0.3 V
i) 5.0 V 5.0 V
Table 1: Table of Values Providing and
19. LAB 2: MODELING IN SPICE 19
Using the given values of , and ; the mode of operation was checked for each
row of Table 1 above. The results are shown by Table 2 below.
Modes of Operation
MODE
a) Cut-off
b) Linear
c) Saturated
d) Saturated
e) Linear
f) Saturated
g) Saturated
h) Linear
i) Saturated
Table 2: Modes of Operation
20. LAB 2: MODELING IN SPICE 20
Hand Calculation Results
Hand Calculations were then compiled using the appropriate formulas corresponding
with the various appropriate modes of operation and confirmed by all group members. These
results are displayed by Figure 12 below.
Figure 12: Hand Calculations for Lab 2A
21. LAB 2: MODELING IN SPICE 21
SPICE Model Results
Next a SPICE project file was created by modeling a NMOS MOSFET using a MbreakN
part in SPICE as shown by Figure 1 in the schematics section. The attributes of the MbreakN
were then modified to contain and display the correct width and length values of the model
. The model for the part was then modified for the correct given model parameter
values as shown by Figure 13.
Figure 13: Model Parameters Used to Modify MbreakN (NMOS) Transistor in Lab 2A
A SPICE DC analysis simulation was ran for analyzing whether or not the model
developed in SPICE would correctly provide the same drain current results calculated using
the fundamental theory and formulas for a MOSFET device. The results are shown in Figure
14.
22. LAB 2: MODELING IN SPICE 22
Figure 14: Spice DC Analysis Results for Lab 2A
Validity Comparison of Model and Hand Calculation Results
The hand calculation results were next compared against the SPICE models results to
determine the validity of the SPICE model NMOS MOSFET. The comparison results are shown
in Table 3.
23. LAB 2: MODELING IN SPICE 23
Validity Comparison
Hand Calculated SPICE Model
% error
ID ID
a) 0 3.21 pA NA
b) 6.615 µA 6.7041 µA 1%
c) 8.052 µA 8.2291 µA 2%
d) 8.513 µA 8.6898 µA 2%
e) 55.125 µA 56.358 µA 2%
f) 127.701 µA 139.021 µA 8%
g) 140.01 µA 154.292 µA 10%
h) 72.765 µA 73.728 µA 1%
i) 526.68 µA 617.23 µA 17%
Table 3: Comparison of Model and Hand Calculations
The model closely matched the hand calculated results in the cut-off and linear or triode
regions (%error was less than 3%). The only significant amount of error 10% and 17% was
observed in the extremely saturated regions at large values of . These differences in values
could be accounted for the fact that SPICE uses additional equations and factors in its
calculations. With such small percent error, it is our conclusion that this SPICE model is a valid
model. We have also gained confidence in using SPICE for modeling NMOS MOSFET devices.
24. LAB 2: MODELING IN SPICE 24
Lab 2B – Accuracy: Finding Parameters for Accurate MOSFET Modeling
Equations and Measured Values
The MOSFET Equations 1-3 were again used along with given measured values and
currents through a MOSFET in order to develop a more accurate MOSFET model using SPICE.
The given measured voltages and currents are shown by Table 4.
Validity Comparison
VGS VDS ID
a) 0.5 V 0.5 V 0.51 pA
b) 0.5 V 2.5 V 2.51 pA
c) 0.5 V 5V 5 pA
d) 1.5 V 0.5 V 895 nA
e) 1.5 V 1V 1 µA
f) 1.5 V 2.5 V 1 µA
g) 3V 0.5 V 3.5778 µA
h) 3V 2.5 V 9.153 µA
i) 3V 5V 9.26 µA
j) 5V 0.5 V 7.15 µA
k) 5V 2.5 V 27 µA
l) 5V 5V 33 µA
Table 4: Measured Values for Lab 2B
Hand Calculation Results
In order to create an accurate model our group first needed to identify the mode of
operation that each row of Table 4 above was in. Since we did not know the value of ,we
needed to provide a range of values for . Thus we assumed that was in the range of (0.5 V
< < 1.5 V). Using this range it was discovered that rows g and j were most likely linear
while row I was most likely saturated. With W/L’s ratio given as 24 we were able to use the
25. LAB 2: MODELING IN SPICE 25
linear equation (Equation 2) with the data from rows g and j using linear algebra (substitution
method) in order to solve for a common value of and that could be utilized in SPICE.
Figure 15: Hand Calculation Results for finding Vt and K’ in Lab 2B
26. LAB 2: MODELING IN SPICE 26
From the hand calculated results using data that followed the linear equations for a n-
channel MOSFET we obtained a VT (VTO) of 746.865 mV and (KP) of 148.842 nA/V2.
Now by using both of these values with the formula for a MOSFET in saturation (Equation 3)
and the data from row i (most likely to be saturated) we could find (LAMBDA) as shown by
Figure 16 below.
Figure 16: Hand Calculation Results for finding in Lab 2B
The value of (LAMBDA) was calculated to be .0077342/V.
27. LAB 2: MODELING IN SPICE 27
Using Results in SPICE to Create an Accurate Model
Using these values a new MOSFET model was created (Figure 2) this time providing a
W (width) of 24 um and a L (length) of 1 um. The model for the MbreakN was changed using
the calculated values for LAMBDA, KP, and VTO. A DC Sweep simulation was then
completed to see how the SPICE model approximated the premeasured values. The results are
shown in Figure 17 below.
Figure 17: SPICE Simulation Results for NBreakN (NMOS) Model used in Lab 2B
28. LAB 2: MODELING IN SPICE 28
Accuracy Comparison of Model and Measured Values
The values provided as measured data were then evaluated against the results obtained by
the SPICE model simulation. This comparison is showed by Table 5 below.
Measured drain SPICE model
%
VGS VDS current drain current
error
ID ID
a) 0.5 V 0.5 V 0.51 pA 510 fA 0
b) 0.5 V 2.5 V 2.51 pA 2.51 pA 0
c) 0.5 V 5V 5 pA 5.01 pA 0
d) 1.5 V 0.5 V 895 nA 902.142 nA 1
e) 1.5 V 1V 1 µA 1.0209 µA 2
f) 1.5 V 2.5 V 1 µA 1.0327 µA 3
g) 3V 0.5 V 3.5778 µA 3.5983 µA 1
h) 3V 2.5 V 9.153 µA 9.2427 µA 1
i) 3V 5V 9.26 µA 9.4177 µA 2
j) 5V 0.5 V 7.15 µA 7.233 µA 1
k) 5V 2.5 V 27 µA 27.343 µA 1
l) 5V 5V 33 µA 33.557 µA 2
Table 5: Comparison of SPICE Model and Given Measured Values
From the comparison results, it seems our SPICE model created by fitting the values of
VTO, KP, and LAMBDA to actual measured data was ninety eight percent accurate at modeling
the results provided by given measured values. Thus, this model acted as a highly accurate
(<5% error) model of our real world NMOS MOSFET. It is now apparent that SPICE can
achieve results with an even greater accuracy when the SPICE model uses parameters that best-
fit the real world device. Overall, this is portion of the lab was a success in modeling and in
showing how SPICE models can handle accuracy and complexity.
29. LAB 2: MODELING IN SPICE 29
Lab 2C: Appropriateness: Modeling a CMOS inverter in SPICE
DC Analysis
Function
A CMOS inverter was developed in SPICE (Figure 3) to examine the digital characteristics of
the circuit using the given values shown in Figure 18 and Figure 19 below.
Figure 18: Model Parameters for MbreakN (PMOS) MOSFET used for Lab 2C
Figure 19: Model Parameters for MbreakN (NMOS) MOSFET used for Lab 2C
A plot of the transfer characteristics was then created in SPICE for Vout vs. Vin as shown
in Figure 20 on the next page. From the results it is observed that when a logic low (0) input (0
V) is provided to the circuit a logic high (1) output (5 V) results. Likewise when a logic high (1)
input (5 V) is provided a logic low (0) output (0 V) results. Thus the circuit is functioning as an
inverter.
30. LAB 2: MODELING IN SPICE 30
Inverter Truth Table
In Out
0 1
1 0
Table 6: Inverter Truth Table
Threshold Voltage
There are several ways to identify the circuit’s logic threshold or switching point. One
method used is to draw a line with a slope of one across the output results. For an inverter this is
the point where Vin equals Vout and occurs for this CMOS inverter circuit at 2.1771 V making
this value our switching point also known as voltage threshold VT=2.1771 V as shown by Figure
20 on the next page.
Figure 20: DC Analysis Plots for Vout vs. Vin
31. LAB 2: MODELING IN SPICE 31
Noise Margins
The noise margins for the circuit can also be found using the previously identified (VinA
(low), Vout(high)) and (VinA (high), Vout(low)) points in Figure 20 by finding the values
where the slope of Vout equals -1 (identified in the top plot of Figure 20). The Logic Noise
Margin is the difference between what the circuit outputs as a valid logic voltage and what the
circuit expects to see as a valid logic voltage. The two equations used to find noise margins are:
Noise Margin High = NMH = Vout(high) – Vin(high)
Equation 4: Noise Margin High
Noise Margin Low = NML = Vin(low) – Vout(low)
Equation 5: Noise Margin Low
The higher the noise margins, the better the circuit will be able to handle a diverse range
of logic values. You can find Vout(high), Vout(low), and thus Vin(low), and Vin(high) by using
the method previously mentioned (where slope of Vout equaled -1) or by estimating and using
minimum numbers for high output and maximum numbers for the low output. Since Vout(high)
= 4.7138 V and Vin(high) = 2.5164 V, NMH is 2.197 V. Since Vin(low) = 1.740 V and
Vout(low) = 347mV, NML is 1.393 V. Ideal noise margins would be approximately 2.5 V for
this inverter circuit. Thus the CMOS inverter circuit has a good NMH and a poor NML.
32. LAB 2: MODELING IN SPICE 32
Power Curve
The power used was next analyzed next using the plot in Figure 21 showing power vs.
Vin. As shown in the figure, the power used at Vin = 0 V and Vin = 5 V are both at 25 pW with
the maximum power used when the circuit is switching (inverting) Vin = 2.2020 of 240 µW.
This is an advantage for CMOS, since nearly all of the power used is during the relatively small
time taken for switching.
Figure 21: DC Analysis Plot for Power vs. Vin for CMOS Inverter for Lab 2C
33. LAB 2: MODELING IN SPICE 33
CMOS Time Domain Analysis
Propagation Delays
The circuit was modified as shown by Figure 4 with a 5 us digital pulse (10 µs period, 2
µs delay and 0.01 µs rise and fall times). The low to high propagation delay time for this circuit
(tPLH) is calculated by taking the time at the point the output has risen to fifty percent of the
inputs maximum range plus the inputs minimum value and subtracting the time at which the
input voltage had dropped to fifty percent of its maximum range plus the inputs minimum value.
The high to low propagation delay time for this circuit (tPHL) is calculated by taking the time at
the point the output has dropped to fifty percent of the inputs maximum range plus the inputs
minimum value and subtracting the time at which the input voltage had risen to fifty percent of
its maximum range plus the inputs minimum value. The total propagation delay is the sum of the
two propagation delays (tP = tPLH + tPHL). The following formulas were used for calculating the
propagation delay times. The results are shown by Figure 22 on the next page.
Equation 6: Propagation Delay Low to High
Equation 7: Propagation Delay High to Low
Equation 8: Total Propagation Delay
34. LAB 2: MODELING IN SPICE 34
‘
Figure 22: Pulse Analysis Plot for tPLH and tPHL of CMOS Inverter used in Lab 2C
From the results show by Figure 22 tPLH =721 ns and tPHL = 396 ns. The total
propagation delay tP = 1.117 µs.
35. LAB 2: MODELING IN SPICE 35
Rise and Fall Times
The rise time for this circuit is calculated by taking the time at the point the output has
risen from its minimum to ninety percent of its maximum output range plus the outputs
minimum and subtracting the time at which the output has risen from its minimum to ten percent
of the maximum output range plus its minimum. The fall time for this circuit is calculated by
taking the time at the point the output has fallen from its maximum to ten percent of its
maximum output range plus the outputs minimum and subtracting the time at which the output
has fallen from its maximum to ninety percent of the maximum output range plus its minimum.
These are defined by the following formulas:
Equation 9: Rise Time
Equation 10: Fall Time
36. LAB 2: MODELING IN SPICE 36
Figure 23: Pulse Analysis Plot for tR and tF of CMOS Inverter used in Lab 2C
From the results show by Figure 23 tR =1.688 µs and tF = 969 ns.
Max Switching Frequency
The maximum switching frequency for a circuit is normally defined by the time it takes
the circuit to rise and fall from to its maximum and minimum output values. This is normally
computed using the circuits rise and fall times as shown by the formula:
Equation 9: Max Switching Frequency
Using this formula fmax = 376 kHz.
37. LAB 2: MODELING IN SPICE 37
CMOS Frequency Analysis
The power supply in the SPICE model was changed for the next part of the analysis as
shown by Figure 5 and a frequency analysis of the circuit was completed by biasing the circuit
at the threshold voltage. The corner frequency (-3db) of this circuit occurred at f3dB = 6.84 kHz
as shown by Figure 24. The corner frequency represents the -3dB point at which the power is
reduced to ½ of the maximum and the voltage gain is reduced to .707 of maximum.
Figure 24: Frequency Analysis Plot for CMOS Inverter used in Lab 2C
38. LAB 2: MODELING IN SPICE 38
CMOS Fanout Analysis
The pulse input in the SPICE model was changed for the next part of the analysis as
shown in Figure 6 with a second inverter added driven by the output of the first inverter using
the same power supply with a Period of (1/f3dB) = 146.2 µs and PW=73.1 µs. A time domain
analysis of this circuit is shown by Figure 25 below. The pulse input was then modified for a
Period of (1/(.1*f3dB)) = 1.462 ms and PW=731 µs as shown by Figure 7. A time domain
analysis of this circuit is shown by Figure 26 on the next page. The pulse input was then
modified for a Period of (1/(10*f3dB)) = 14.62 µs and PW=7.31 µs as shown by Figure 8. A
time domain analysis of this circuit is shown by Figure 27 on the next page.
Figure 25: Results for CMOS Inverter w/2nd Inverter Added and Period at 1/f3dB.
39. LAB 2: MODELING IN SPICE 39
Figure 26: Results for CMOS Inverter w/2nd Inverter Added and Period at 1/(.1*f3dB).
Figure 27: Results for CMOS Inverter w/2nd Inverter Added and Period at 1/(10*f3dB).
40. LAB 2: MODELING IN SPICE 40
It is apparent from Figures 25-27 that the CMOS inverter creates good output pulses
when the frequency is at (Figure 25) or below (Figure 26) the f3dB point. However as the
output rectangular pulse quickly fails to retain its shape once the frequency is driven beyond the
f3dB frequency.
Table of Results
Ideal This
Evaluation Procedure Parameter
Inverter Inverter
Transfer
VThreshold 2.5 V 2.1771 V
Characteristic
NMH 2.5 V 2.197 V
Noise Margins
NML 2.5 V 1.393 V
P @ VinA = 0
0W 25 pW
V
Power Used P @ VinA = 5
0W 25 pW
V
PMax 0W 240 uW
tPHL 0s 396 ns
Propagation Delays tPLH 0s 721 ns
tP 0s 1.117 us
Rise Time tR 0s 1.688 us
Fall Time tF 0s 969 ns
3dB Corner Frequency F3dB inf. 6.84 kHz
Max Frequency
(Using P-delay fMax inf. 376 kHz
method)
Dual Inverter Pulse Digital Pulse
Perfect Good
Output at f3dB Quality
Dual Inverter Pulse Digital Pulse
Perfect Excellent
Output at .1*f3dB Quality
Dual Inverter Pulse Digital Pulse
Perfect Poor
Output at 10*f3dB Quality
Table 7: CMOS Results
41. LAB 2: MODELING IN SPICE 41
Part C Conclusions:
In summary, SPICE provided an appropriate model for analyzing the real world CMOS
inverter. Overall, this portion of the lab was a success in modeling and in showing how SPICE
modeling can provide a variety of appropriate analyses results for evaluating integrated circuits.
It took only a few hours in a group to complete all of part 2’s analyses in SPICE making it a
much more efficient use of time than would have occurred by measuring each result physically.
Aspiring engineers need to understand and use the SPICE in order to conduct quality IC
evaluations. The CMOS inverter studied in this section offers great advantages in power over
the TTL inverter studied in Lab 1 and has a good NMH. However the NML, propagation delays,
rise and fall times were worse than the TTL inverter. It was also observed that the CMOS circuit
responded poorly when an additional CMOS circuit was added and the clock frequency was
pushed higher than the f3dB frequency. As a result this CMOS circuit will not function at as
high of speeds as the TTL circuit and has poor fanout.
42. LAB 2: MODELING IN SPICE 42
Lab 2D: Usefulness: Comparison of BJT TTL and CMOS Using SPICE Modeling
DC Analysis
Function
A BJT TTL inverter was developed in SPICE (Figure 9) to obtain the DC characteristics
of the circuit so they can be used to compare the circuit with the CMOS inverter in Lab 2C.
A plot of the transfer characteristics was then created in SPICE for Vout vs. Vin as shown
in Figure 28 on the next page. From the results it is observed that when a logic low (0) input (0
V) is provided to the circuit a logic high (1) output (5 V) results. Likewise when a logic high (1)
input (5 V) is provided a logic low (0) output (0 V) results. Thus the circuit is functioning as an
inverter.
Inverter Truth Table
In Out
0 1
1 0
Table 8: Inverter Truth Table
Threshold Voltage
There are several ways to identify the circuit’s logic threshold or switching point. One
method used is to draw a line with a slope of one across the output results. For an inverter this is
the point where Vin equals Vout and occurs for this CMOS inverter circuit at 1.3925 V making
this value our switching point also known as voltage threshold VT=1.3925 V as shown by Figure
28 on the next page.
43. LAB 2: MODELING IN SPICE 43
Figure 28: DC Analysis Plots for Vout vs. Vin for BJT TTL Inverter for Lab 2D
44. LAB 2: MODELING IN SPICE 44
Noise Margins
The noise margins for the circuit can also be found using the previously identified (Vin
(low), Vout(high)) and (Vin (high), Vout(low)) points in Figure 28 by finding the values where
the slope of Vout equals -1 (identified in the top plot of Figure 28). The Logic Noise Margin is
the difference between what the circuit outputs as a valid logic voltage and what the circuit
expects to see as a valid logic voltage. Once again Equation 4 and Equation 5 were used to
compute noise margins.
Since Vout(high) = 4.7423 V and Vin(high) = 1.4370 V, NMH is 3.305 V. Since
Vin(low) = 606 mV and Vout(low) = 23 mV, NML = 583 mV. Ideal noise margins would be
balanced at approximately 2.5 V for this inverter circuit. Thus the TTL inverter circuit has a
great NMH and a very poor NML.
45. LAB 2: MODELING IN SPICE 45
Power Curve
The power used was next analyzed next using the plot in Figure 29 showing power vs.
Vin. As shown in the figure, the power used at Vin = 0 is 5.386 mW and the power used at Vin
= 5 is 16.772 mW with the maximum power used when the circuit is switching (inverting) at Vin
= 1.43 V is 165 mW. This is a disadvantage of TTL, even when the circuit is not switching it
uses several milliwatts of power.
Figure 29: DC Analysis Plot for Power vs. Vin for BBJT TTL Inverter for Lab 2D
46. LAB 2: MODELING IN SPICE 46
TTL Time Domain Analysis
Propagation Delays
The circuit was modified as shown by Figure 10 with a 5 us digital pulse (10 µs period, 2
µs delay and 0.01 µs rise and fall times) matching the values used for the CMOS inverter. Once
again Equations 6-8 were used for calculating the propagation delay times. The simulation
results are shown by Figure 30.
‘
Figure 30: Pulse Analysis Plot for tPLH and tPHL of TTL Inverter used in Lab 2D
From the results show by Figure 30 tPLH =267 ns and tPHL = 3 ns. The total propagation
delay tP = 270 ns.
47. LAB 2: MODELING IN SPICE 47
Rise and Fall Times
The rise times for the TTL circuit were calculated using Equation 9 and Equation 10,
the formulas for rise and fall time. The simulation results are displayed by Figure 31 below.
Figure 31: Pulse Analysis Plot for tR and tF of CMOS Inverter used in Lab 2C
From the results show by Figure 31 tR =35.4 ns and tF = 4 ns.
48. LAB 2: MODELING IN SPICE 48
Max Switching Frequency
Using Equation 9 to compute the maximum frequency the TTL circuit has fmax = 25.4
MHz.
TTL Frequency Analysis
The power supply in the SPICE model was changed for the next part of the analysis as
shown by Figure 11 and a frequency analysis of the circuit was completed by biasing the circuit
at the threshold voltage. The corner frequency (-3db) of this circuit occurred at f3dB = 18.9 MHz
as shown by Figure 32 below.
Figure 32: Frequency Analysis Plot for TTL Inverter used in Lab 2D
49. LAB 2: MODELING IN SPICE 49
Comparison of CMOS and TTL Results
Ideal CMOS TTL
Evaluation Procedure Parameter
Inverter Inverter Inverter
Transfer
VThreshold 2.5 V 2.177 V 1.393 V
Characteristic
NMH 2.5 V 2.197 V 3.305 V
Noise Margins
NML 2.5 V 1.393 V 583 mV
P @ VinA = 0
0W 25 pW 5.386 mW
V
Power Used P @ VinA = 5
0W 25 pW 16.773 mW
V
PMax 0W 240 uW 165 mW
tPHL 0s 396 ns 3 ns
Propagation Delays tPLH 0s 721 ns 267 ns
tP 0s 1.117 us 3 ns
Rise Time tR 0s 1.688 us 35.4 ns
Fall Time tF 0s 969 ns 4 ns
3dB Corner Frequency F3dB inf. 6.84 kHz 18.9 MHz
Max Frequency
(Using P-delay fMax inf. 376 kHz 25.4 MHz
method)
Table 9: Comparison of CMOS and TTL Circuits
Table 9 shows a comparison of the characteristics for the BJT TLL inverter with the
CMOS inverter from Lab 2C. As shown in the table, the BJT TTL inverter is must faster with a
significantly lower rise time, fall time and propagation delays and is able to handle faster clock
speeds. The CMOS inverter makes up for its lack of speed by using significantly less power and
only using that power during switching. Therefore, if speed is the most important circuit
characteristic, the BJT TTL inverter would win. However, if minimum power usage is the most
important characteristic, the CMOS inverter would win. Finally the TTL has a much smaller
NML than the CMOS inverter making the device less resistant to noise interference.
50. LAB 2: MODELING IN SPICE 50
Conclusion for Lab 2D:
In summary, SPICE provided a valid, accurate, appropriate and useful model for
analyzing the BJT TTL and CMOS inverters. This portion of the lab was a success in modeling
and in showing how SPICE modeling can provide a variety of useful analyses for comparing
integrated circuits. Overall this lab demonstrated the power and features of modeling using
SPICE.