This document describes a technique called "multi-supply digital layout" that allows reliable back-annotation between digital blocks powered by different voltage supplies. It presents a design flow that uses standard CAD tools from RTL to layout. Digital blocks are grouped into voltage regions separated by isolation rings. Level shifter cells are used for voltage conversion at region interfaces. Libraries are generated for level shifters to integrate them into the digital flow for synthesis, simulation, and test. Floorplanning scripts automate placement of cells into the appropriate voltage regions.
Design and implemation of an enhanced dds based digitalManoj Kollam
This paper proposes the design and implementation of an enhanced direct digital synthesis (DDS)-based digital modulator that supports multiple modulation schemes. The design enhances the basic DDS architecture with minimal additional hardware to provide user selection of different modulation techniques using a single unit. The modulator architecture consists of a phase accumulator, phase-to-amplitude converter, and other digital logic blocks. The design is implemented on a Spartan-3A FPGA using VHDL and can generate various modulated output signals for software-defined radio applications.
This document compares different architectures for implementing the discrete cosine transform (DCT) in an image compression system for low power applications. It summarizes four architectures: a baseline 2D DCT architecture, a row/column distributed arithmetic approach, a fully pipelined architecture, and analyzes their power consumption and speed. The row/column approach provides a 24.4% power savings over the baseline, while the fully pipelined architecture provides 16.4% savings. The fully pipelined architecture also achieves the highest throughput of 4.703 GHz.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
This document discusses an FPGA implementation of a four phase code design using a modified genetic algorithm. It summarizes the key aspects of the implementation as follows:
1) The proposed architecture efficiently implements a modified genetic algorithm on an FPGA to identify good pulse compression sequences based on discrimination factor.
2) Pulse compression techniques in radar allow long pulses to achieve high energy while maintaining the range resolution of short pulses. The receiver compresses the long signal into a narrow signal.
3) The criteria for good pulse compression sequences include high merit factor and discrimination factor. Merit factor measures quality by comparing main lobe energy to side lobe energy. Discrimination factor compares the main peak to maximum side lobes.
Hardware Implementation of Genetic Algorithm Based Digital Colour Image Water...IDES Editor
This document describes a hardware implementation of a genetic algorithm based digital color image watermarking system. The system embeds a watermark image into the luminance channel (Y channel) of a host color image after converting the image from RGB to YUV color space. A genetic algorithm is used to determine optimal intensity values in the host image for embedding the watermark image bits invisibly. The proposed design is implemented as a custom integrated circuit for real-time watermarking of images as they are captured by a digital camera. Synthesis results show that the design can operate at 5ns clock speed and consumes a maximum power of 73.84mW when implemented on an Altera Cyclone II FPGA.
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
This document outlines 29 potential projects for university students to undertake with SUPARCO. The projects range from designing components of small satellites to analyzing aerodynamic properties to developing encryption systems. SUPARCO will provide funding and engineering support for selected projects. Students will gain hands-on experience working on challenges relevant to SUPARCO's objectives.
Design and implemation of an enhanced dds based digitalManoj Kollam
This paper proposes the design and implementation of an enhanced direct digital synthesis (DDS)-based digital modulator that supports multiple modulation schemes. The design enhances the basic DDS architecture with minimal additional hardware to provide user selection of different modulation techniques using a single unit. The modulator architecture consists of a phase accumulator, phase-to-amplitude converter, and other digital logic blocks. The design is implemented on a Spartan-3A FPGA using VHDL and can generate various modulated output signals for software-defined radio applications.
This document compares different architectures for implementing the discrete cosine transform (DCT) in an image compression system for low power applications. It summarizes four architectures: a baseline 2D DCT architecture, a row/column distributed arithmetic approach, a fully pipelined architecture, and analyzes their power consumption and speed. The row/column approach provides a 24.4% power savings over the baseline, while the fully pipelined architecture provides 16.4% savings. The fully pipelined architecture also achieves the highest throughput of 4.703 GHz.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
This document discusses an FPGA implementation of a four phase code design using a modified genetic algorithm. It summarizes the key aspects of the implementation as follows:
1) The proposed architecture efficiently implements a modified genetic algorithm on an FPGA to identify good pulse compression sequences based on discrimination factor.
2) Pulse compression techniques in radar allow long pulses to achieve high energy while maintaining the range resolution of short pulses. The receiver compresses the long signal into a narrow signal.
3) The criteria for good pulse compression sequences include high merit factor and discrimination factor. Merit factor measures quality by comparing main lobe energy to side lobe energy. Discrimination factor compares the main peak to maximum side lobes.
Hardware Implementation of Genetic Algorithm Based Digital Colour Image Water...IDES Editor
This document describes a hardware implementation of a genetic algorithm based digital color image watermarking system. The system embeds a watermark image into the luminance channel (Y channel) of a host color image after converting the image from RGB to YUV color space. A genetic algorithm is used to determine optimal intensity values in the host image for embedding the watermark image bits invisibly. The proposed design is implemented as a custom integrated circuit for real-time watermarking of images as they are captured by a digital camera. Synthesis results show that the design can operate at 5ns clock speed and consumes a maximum power of 73.84mW when implemented on an Altera Cyclone II FPGA.
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
This document outlines 29 potential projects for university students to undertake with SUPARCO. The projects range from designing components of small satellites to analyzing aerodynamic properties to developing encryption systems. SUPARCO will provide funding and engineering support for selected projects. Students will gain hands-on experience working on challenges relevant to SUPARCO's objectives.
This document discusses the I2C bus protocol and its implementation on an FPGA to interface with low speed peripheral devices. It also provides background on VLSI design, including the evolution of integration density over time, the VLSI design flow from behavioral to layout representations, and historical context on increasing processing power needs driving advances in integration technologies. The I2C protocol allows communication between multiple chips using only two pins, addressing the need for lower pin counts as chip sizes decrease. The document implements I2C on an FPGA to interface with a DS1307 peripheral and synthesizes it on a Spartan 3E chip.
It's my ppt of disseration defense at 2012_06_04. Please give me some feedback so I can improve my ppt skills. Feel free to discuss any problem with me. Thank you!
This document presents a comparative analysis of digital image watermarking techniques in the frequency domain using MATLAB Simulink. It discusses watermarking using discrete cosine transform (DCT) and discrete wavelet transform (DWT). For DCT, the image is divided into blocks and DCT is applied before embedding the watermark in middle frequency coefficients. For extraction, the same process is reversed. For DWT, the image is decomposed into sub-bands before embedding the watermark into the low-high frequency sub-band. Extraction follows the reverse process. The document also proposes a technique using both DCT and DWT that embeds a watermark into DCT coefficients of DWT sub-bands for increased robust
DWT-DCT-SVD Based Semi Blind Image Watermarking Using Middle Frequency BandIOSR Journals
This document summarizes a research paper that proposes a semi-blind image watermarking technique using discrete wavelet transform (DWT), discrete cosine transform (DCT), and singular value decomposition (SVD). The technique embeds a watermark in the middle frequency band of the DWT domain of a host image. It modifies the singular values of the DCT coefficients of the middle frequency band using singular values of the DCT transformed watermark. The watermark can then be extracted from the watermarked image using inverse processes. The technique was tested on various attacks and showed robustness, with correlation values between the extracted and original watermarks ranging from 0.5308 to 0.9665 and PSNR values indicating impercept
A Novel Digital Watermarking Technique for Video Copyright Protection cscpconf
This paper proposes a novel digital video watermarking technique that embeds both visible and invisible watermarks for improved copyright protection. The invisible watermark is embedded using discrete wavelet transform (DWT) in the high-high (HH) subband coefficients of video frames. The visible watermark is embedded partially in video frames depending on user input location. Experimental results on a gray-scale video show the embedded watermarks can be extracted after attacks like salt and pepper noise, Gaussian noise, and median filtering, with peak signal-to-noise ratios above 28 dB, demonstrating the technique's robustness.
This document provides information on the curriculum for the first semester of the M.E. Embedded System Technologies program at Anna University, Chennai. It includes a list of 5 theory courses and 1 elective course offered in the semester, along with their course codes, titles, contact hours, and credits. It also lists 3 elective courses that can be chosen for the semester. The document then provides detailed syllabus information for 2 of the theory courses: MA9216 Applied Mathematics for Electrical Engineers and ET9211 Advanced Digital System Design.
A Video Watermarking Scheme to Hinder Camcorder PiracyIOSR Journals
This document describes a video watermarking scheme to prevent camcorder piracy in movie theaters. The scheme embeds watermarks in video frames so that any compliant video player cannot play the video if recorded in a theater. The watermarking technique is robust to geometric distortions like rotation and scaling. It also prevents loss of quality from lossy compression formats. The scheme uses an integer wavelet transform for the watermark embedding and extraction processes, making it computationally efficient and lossless. Experimental results show the scheme can withstand various attacks like filtering, noise addition, resizing and rotation while accurately extracting the embedded watermarks.
This document discusses using video compression techniques to compress multichannel neural signals. It proposes using a multiwavelet transform to decorrelate the signals, followed by vector quantization to exploit correlations between electrodes. Motion estimation and compensation are also used to reduce redundancy between successive neural frames by determining motion vectors, similar to how video compression analyzes frame-to-frame motion. The goal is to significantly reduce the large amounts of neural data for easier wireless transmission without degrading quality.
Advance Digital Video Watermarking based on DWT-PCA for Copyright protectionIJERA Editor
This document presents a digital video watermarking technique based on discrete wavelet transform (DWT) and principal component analysis (PCA). It begins with an introduction to digital watermarking and an overview of spatial and transform domain watermarking methods. The document then describes DWT and PCA in more detail. It presents a watermarking scheme that uses DWT to decompose video frames into frequency subbands, and embeds a watermark into the principal components of the low frequency subband after applying PCA. Experimental results on a test video show the watermarked frames have no visible quality differences from the original and the watermark is robust to various attacks. The technique achieves imperceptibility measured by high peak signal-to-
A Coarse-Grained Reconfigurable Wavelet Denoiser Exploiting the Multi-Dataflo...MDC_UNICA
In the last few years, efficient resource management turned out to be one of the major challenges for hardware designers. Strategies of reusability through reconfiguration have demonstrated interesting potentials to address it, providing also power and area minimization. The Multi-Dataflow Composer (MDC) tool has been presented to the scientific community to automatically build-up runtime coarse-grained reconfigurable platforms. Originally conceived in the field of Reconfigurable Video Coding (RVC), the MDC allows achieving attractive results also for hardware designers operating in different application fields. In this work, we intend to demonstrate the potential orthogonality of the MDC approach with respect to the RVC domain. A runtime reconfigurable wavelet denoiser, targeted for biomedical applications, has been developed and prototyped onto an FPGA Development Board Spartan 3E 1600. Impressive results in terms of resource minimization have been achieved with respect to more traditional solutions.
LaWzer, a still image codec designed by L. GuillemotLudovic Guillemot
LAWZER, A STILL IMAGE CODEC DESIGNED BY L. GUILLEMOT
THE LAWZER PROJECT MATERIALIZES 10 YEARS OF SCIENTIFIC CONTRIBUTIONS IN IMAGE COMPRESSION AND SOURCE CODING.
LaWzer is a personal project, a showcase for the skills and interests of its designer, Ludovic Guillemot, and a way to celebrate a regular activity in research with academic partners.
LAWZER IS A STILL IMAGE CODEC allowing to efficiently encode digital images at the desired size. LaWzer 1.0 has been developed (in C++) between July 2013 and August 2014. It includes works previously published as well as new coding algorithms specially designed for LaWzer.
LAWZER TECHNOLOGY IS BASED ON LATTICE VECTOR QUANTIZATION (LVQ) AND WAVELET TRANSFORM.
In (very) few words, LVQ is a blockwise approach i.e. the basic elements of the coding process are vectors of data. This is a highly efficient approach but usually renowned for the algorithmic complexity involved by operations on n-dimensional objects. LaWzer focuses on reversing this reputation while still improving the rate-distortion trade-off.
Because compression is a must in the big data era, we believe that some applications could be in need of a fast and efficient vectorwise compression scheme.
LAWZER V1.0 IS A PROOF OF CONCEPT.
The most challenging task was to develop a real-life codec, i.e. showing that processing n-dimensional objects was no more a technical hurdle for the execution speed. Various algorithms have been designed and implemented to reach this goal: quantizers and lossless coding, statistical estimation in wavelet domain, numerical optimization, etc.
WORK IN PROGRESS:
The first phase of the project is now achieved. One have a complete compression scheme which produces compressed files (“.law”) with short execution times (short means of the order of few seconds for very big images). But much more can be done, further versions will include enhanced coding algorithm, new functionalities (color, watermarking, etc.), code optimization, etc.
1) The document discusses modeling techniques for active components in digital systems to accurately capture their dynamic behavior at high speeds.
2) Traditional SPICE models and transmission line equivalents are not suitable for simulating circuits with hundreds of elements due to slow simulation times and convergence problems.
3) The modeling approach presented uses primitives from the DWN simulator to create behavioral models of active components based on time domain reflectometer (TDR) measurements, allowing for much faster simulations while maintaining accuracy.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal for Research in Applied Science & Engineeringpriyanka singh
This document describes a method for embedding a secret watermark image into a QR code image using discrete wavelet transform. The watermark embedding process involves:
1) Performing a two-level discrete wavelet transform on the QR code image to create sub-bands
2) Converting the watermark image (e.g. a logo) to a binary sequence and generating a pseudo-random sequence with a secret key
3) Embedding the watermark bits into one of the high frequency sub-bands by modifying pixel values
4) Performing inverse discrete wavelet transform to get the watermarked QR code image
The watermark can then be extracted without the original QR code by estimating the original pixel values and
The document discusses DCT/IDCT concepts and applications. It provides an introduction to DCT and IDCT, explaining that they are used widely in video and audio compression. It describes the DCT and IDCT functions and how they work to transform signals between spatial and frequency domains. Examples of one-dimensional and two-dimensional DCT/IDCT equations are also given. Finally, common applications of DCT/IDCT compression techniques are listed, such as in DVD players, cable TV, graphics cards, and medical imaging systems.
The document presents an efficient FPGA implementation of convolution that reduces processing time using hardware computing. It implements the discrete linear convolution of two finite length sequences. The existing system uses DSP processors that consume more power and require more chip area with low speed. The proposed system implements convolution using VLSI architecture, consuming less power and requiring less chip area with high speed. It also works for signed and unsigned numbers and reduces processing time.
The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.
Design and Performance Evaluation Of Modulation Techniques Suitable For ADSL ...Ash Milan
This document discusses modulation techniques for ADSL modems. It begins with an abstract that introduces ADSL and the goal of evaluating modulation techniques to achieve high bandwidth.
The body of the document is divided into two main sections. The first section provides background on ADSL technology, including defining an ADSL modem and explaining how transmission rates vary based on distance from the local exchange.
The second section discusses modulation schemes used in ADSL modems, including phase-shift keying (PSK), quadrature amplitude modulation (QAM), and their basic receiver block diagrams. It provides equations to describe these modulation techniques.
This document discusses the challenges of verifying mixed-signal integrated circuits. It presents how Freescale used Cadence eManager and a variety of modeling and simulation techniques to verify a sensor IC. They took a progressive approach starting with digital simulations using wreal models for speed and then incorporating more accurate Verilog-AMS and transistor-level models. They were able to set up a single simulation environment in eManager to run analog, digital and mixed-signal simulations. The document discusses using control-oriented and data-oriented functional coverage to ensure the chip's functionality was verified.
The MC13783 is an integrated circuit that provides power management and audio functionality for portable devices. It includes a battery charger, voltage regulators, audio codecs, amplifiers, and other features to support full device functionality while optimizing system size and bill of materials. Key features include power management, a 13-bit voice codec, stereo recording and playback, and a processor interface. The document describes the various blocks and features implemented on the MC13783 chip.
Re usable continuous-time analog sva assertionsRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
This document discusses the I2C bus protocol and its implementation on an FPGA to interface with low speed peripheral devices. It also provides background on VLSI design, including the evolution of integration density over time, the VLSI design flow from behavioral to layout representations, and historical context on increasing processing power needs driving advances in integration technologies. The I2C protocol allows communication between multiple chips using only two pins, addressing the need for lower pin counts as chip sizes decrease. The document implements I2C on an FPGA to interface with a DS1307 peripheral and synthesizes it on a Spartan 3E chip.
It's my ppt of disseration defense at 2012_06_04. Please give me some feedback so I can improve my ppt skills. Feel free to discuss any problem with me. Thank you!
This document presents a comparative analysis of digital image watermarking techniques in the frequency domain using MATLAB Simulink. It discusses watermarking using discrete cosine transform (DCT) and discrete wavelet transform (DWT). For DCT, the image is divided into blocks and DCT is applied before embedding the watermark in middle frequency coefficients. For extraction, the same process is reversed. For DWT, the image is decomposed into sub-bands before embedding the watermark into the low-high frequency sub-band. Extraction follows the reverse process. The document also proposes a technique using both DCT and DWT that embeds a watermark into DCT coefficients of DWT sub-bands for increased robust
DWT-DCT-SVD Based Semi Blind Image Watermarking Using Middle Frequency BandIOSR Journals
This document summarizes a research paper that proposes a semi-blind image watermarking technique using discrete wavelet transform (DWT), discrete cosine transform (DCT), and singular value decomposition (SVD). The technique embeds a watermark in the middle frequency band of the DWT domain of a host image. It modifies the singular values of the DCT coefficients of the middle frequency band using singular values of the DCT transformed watermark. The watermark can then be extracted from the watermarked image using inverse processes. The technique was tested on various attacks and showed robustness, with correlation values between the extracted and original watermarks ranging from 0.5308 to 0.9665 and PSNR values indicating impercept
A Novel Digital Watermarking Technique for Video Copyright Protection cscpconf
This paper proposes a novel digital video watermarking technique that embeds both visible and invisible watermarks for improved copyright protection. The invisible watermark is embedded using discrete wavelet transform (DWT) in the high-high (HH) subband coefficients of video frames. The visible watermark is embedded partially in video frames depending on user input location. Experimental results on a gray-scale video show the embedded watermarks can be extracted after attacks like salt and pepper noise, Gaussian noise, and median filtering, with peak signal-to-noise ratios above 28 dB, demonstrating the technique's robustness.
This document provides information on the curriculum for the first semester of the M.E. Embedded System Technologies program at Anna University, Chennai. It includes a list of 5 theory courses and 1 elective course offered in the semester, along with their course codes, titles, contact hours, and credits. It also lists 3 elective courses that can be chosen for the semester. The document then provides detailed syllabus information for 2 of the theory courses: MA9216 Applied Mathematics for Electrical Engineers and ET9211 Advanced Digital System Design.
A Video Watermarking Scheme to Hinder Camcorder PiracyIOSR Journals
This document describes a video watermarking scheme to prevent camcorder piracy in movie theaters. The scheme embeds watermarks in video frames so that any compliant video player cannot play the video if recorded in a theater. The watermarking technique is robust to geometric distortions like rotation and scaling. It also prevents loss of quality from lossy compression formats. The scheme uses an integer wavelet transform for the watermark embedding and extraction processes, making it computationally efficient and lossless. Experimental results show the scheme can withstand various attacks like filtering, noise addition, resizing and rotation while accurately extracting the embedded watermarks.
This document discusses using video compression techniques to compress multichannel neural signals. It proposes using a multiwavelet transform to decorrelate the signals, followed by vector quantization to exploit correlations between electrodes. Motion estimation and compensation are also used to reduce redundancy between successive neural frames by determining motion vectors, similar to how video compression analyzes frame-to-frame motion. The goal is to significantly reduce the large amounts of neural data for easier wireless transmission without degrading quality.
Advance Digital Video Watermarking based on DWT-PCA for Copyright protectionIJERA Editor
This document presents a digital video watermarking technique based on discrete wavelet transform (DWT) and principal component analysis (PCA). It begins with an introduction to digital watermarking and an overview of spatial and transform domain watermarking methods. The document then describes DWT and PCA in more detail. It presents a watermarking scheme that uses DWT to decompose video frames into frequency subbands, and embeds a watermark into the principal components of the low frequency subband after applying PCA. Experimental results on a test video show the watermarked frames have no visible quality differences from the original and the watermark is robust to various attacks. The technique achieves imperceptibility measured by high peak signal-to-
A Coarse-Grained Reconfigurable Wavelet Denoiser Exploiting the Multi-Dataflo...MDC_UNICA
In the last few years, efficient resource management turned out to be one of the major challenges for hardware designers. Strategies of reusability through reconfiguration have demonstrated interesting potentials to address it, providing also power and area minimization. The Multi-Dataflow Composer (MDC) tool has been presented to the scientific community to automatically build-up runtime coarse-grained reconfigurable platforms. Originally conceived in the field of Reconfigurable Video Coding (RVC), the MDC allows achieving attractive results also for hardware designers operating in different application fields. In this work, we intend to demonstrate the potential orthogonality of the MDC approach with respect to the RVC domain. A runtime reconfigurable wavelet denoiser, targeted for biomedical applications, has been developed and prototyped onto an FPGA Development Board Spartan 3E 1600. Impressive results in terms of resource minimization have been achieved with respect to more traditional solutions.
LaWzer, a still image codec designed by L. GuillemotLudovic Guillemot
LAWZER, A STILL IMAGE CODEC DESIGNED BY L. GUILLEMOT
THE LAWZER PROJECT MATERIALIZES 10 YEARS OF SCIENTIFIC CONTRIBUTIONS IN IMAGE COMPRESSION AND SOURCE CODING.
LaWzer is a personal project, a showcase for the skills and interests of its designer, Ludovic Guillemot, and a way to celebrate a regular activity in research with academic partners.
LAWZER IS A STILL IMAGE CODEC allowing to efficiently encode digital images at the desired size. LaWzer 1.0 has been developed (in C++) between July 2013 and August 2014. It includes works previously published as well as new coding algorithms specially designed for LaWzer.
LAWZER TECHNOLOGY IS BASED ON LATTICE VECTOR QUANTIZATION (LVQ) AND WAVELET TRANSFORM.
In (very) few words, LVQ is a blockwise approach i.e. the basic elements of the coding process are vectors of data. This is a highly efficient approach but usually renowned for the algorithmic complexity involved by operations on n-dimensional objects. LaWzer focuses on reversing this reputation while still improving the rate-distortion trade-off.
Because compression is a must in the big data era, we believe that some applications could be in need of a fast and efficient vectorwise compression scheme.
LAWZER V1.0 IS A PROOF OF CONCEPT.
The most challenging task was to develop a real-life codec, i.e. showing that processing n-dimensional objects was no more a technical hurdle for the execution speed. Various algorithms have been designed and implemented to reach this goal: quantizers and lossless coding, statistical estimation in wavelet domain, numerical optimization, etc.
WORK IN PROGRESS:
The first phase of the project is now achieved. One have a complete compression scheme which produces compressed files (“.law”) with short execution times (short means of the order of few seconds for very big images). But much more can be done, further versions will include enhanced coding algorithm, new functionalities (color, watermarking, etc.), code optimization, etc.
1) The document discusses modeling techniques for active components in digital systems to accurately capture their dynamic behavior at high speeds.
2) Traditional SPICE models and transmission line equivalents are not suitable for simulating circuits with hundreds of elements due to slow simulation times and convergence problems.
3) The modeling approach presented uses primitives from the DWN simulator to create behavioral models of active components based on time domain reflectometer (TDR) measurements, allowing for much faster simulations while maintaining accuracy.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal for Research in Applied Science & Engineeringpriyanka singh
This document describes a method for embedding a secret watermark image into a QR code image using discrete wavelet transform. The watermark embedding process involves:
1) Performing a two-level discrete wavelet transform on the QR code image to create sub-bands
2) Converting the watermark image (e.g. a logo) to a binary sequence and generating a pseudo-random sequence with a secret key
3) Embedding the watermark bits into one of the high frequency sub-bands by modifying pixel values
4) Performing inverse discrete wavelet transform to get the watermarked QR code image
The watermark can then be extracted without the original QR code by estimating the original pixel values and
The document discusses DCT/IDCT concepts and applications. It provides an introduction to DCT and IDCT, explaining that they are used widely in video and audio compression. It describes the DCT and IDCT functions and how they work to transform signals between spatial and frequency domains. Examples of one-dimensional and two-dimensional DCT/IDCT equations are also given. Finally, common applications of DCT/IDCT compression techniques are listed, such as in DVD players, cable TV, graphics cards, and medical imaging systems.
The document presents an efficient FPGA implementation of convolution that reduces processing time using hardware computing. It implements the discrete linear convolution of two finite length sequences. The existing system uses DSP processors that consume more power and require more chip area with low speed. The proposed system implements convolution using VLSI architecture, consuming less power and requiring less chip area with high speed. It also works for signed and unsigned numbers and reduces processing time.
The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.
Design and Performance Evaluation Of Modulation Techniques Suitable For ADSL ...Ash Milan
This document discusses modulation techniques for ADSL modems. It begins with an abstract that introduces ADSL and the goal of evaluating modulation techniques to achieve high bandwidth.
The body of the document is divided into two main sections. The first section provides background on ADSL technology, including defining an ADSL modem and explaining how transmission rates vary based on distance from the local exchange.
The second section discusses modulation schemes used in ADSL modems, including phase-shift keying (PSK), quadrature amplitude modulation (QAM), and their basic receiver block diagrams. It provides equations to describe these modulation techniques.
This document discusses the challenges of verifying mixed-signal integrated circuits. It presents how Freescale used Cadence eManager and a variety of modeling and simulation techniques to verify a sensor IC. They took a progressive approach starting with digital simulations using wreal models for speed and then incorporating more accurate Verilog-AMS and transistor-level models. They were able to set up a single simulation environment in eManager to run analog, digital and mixed-signal simulations. The document discusses using control-oriented and data-oriented functional coverage to ensure the chip's functionality was verified.
The MC13783 is an integrated circuit that provides power management and audio functionality for portable devices. It includes a battery charger, voltage regulators, audio codecs, amplifiers, and other features to support full device functionality while optimizing system size and bill of materials. Key features include power management, a 13-bit voice codec, stereo recording and playback, and a processor interface. The document describes the various blocks and features implemented on the MC13783 chip.
Re usable continuous-time analog sva assertionsRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
Verification Of 1 M+ Transistors Mixed Signal IcRégis SANTONJA
This document discusses verification techniques for a mixed-signal integrated circuit containing over 1 million transistors used in cellular and multimedia applications. It describes creating block-level testbenches first before integrating them into a chip-level testbench. Verification goals have expanded from just functional verification to also consider signal integrity and power consumption to avoid issues during fabrication. A verification matrix is used to ensure all specification aspects are tested through simulation before production.
This document is a resume for Regis Santonja, a 39-year-old French national with over 15 years of experience leading verification teams for mixed-signal integrated circuits. He currently works as a Mixed-Signal IC Verification Leader at Freescale, where he leads international teams and drives verification methodology. Prior to this, he held several engineering and leadership roles in digital design and verification at companies including Motorola, CSTI, LSI Logic, and others.
Verilog Ams Used In Top Down Methodology For Wireless Integrated CircuitsRégis SANTONJA
The document discusses using the VerilogAMS language and top-down methodology for wireless integrated circuit designs. Specifically, it discusses:
1) Using the top-down methodology to allow for general functionality verification early in the design process by analyzing the ASIC from top to bottom before individual block implementation.
2) Describing the steps of behavioral modeling of blocks using VerilogA, replacing blocks with transistor-level designs, and simulating the entire design with mixed behavioral and transistor-level blocks.
3) Noting that the top-down methodology can be applied whether the design has a large analog/small digital portion or large digital/small analog portion.
Re usable continuous-time analog sva assertions - slidesRégis SANTONJA
This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
VLSI DESIGN
The document discusses VLSI (Very Large Scale Integration) design. It begins by defining VLSI as integrating thousands of transistors into a single chip. It then discusses the evolution of integration levels from SSI to VLSI and beyond. The rest of the document outlines the VLSI design flow including system specification, architectural design, functional design, logic design, circuit design, physical design, fabrication, packaging and testing. Transistor modeling considerations and basic MOS transistor operation modes such as cut-off, triode and saturation are also summarized.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
This presentation is a short introduction to issues in Hardware-Software Codesign. It discusses definition of codesign, its significance, design issues in Hardware-software codesign, Abstraction levels, Duality of harware and software
The document discusses the Chameleon Chip, a reconfigurable processor that can rewire itself dynamically to adapt to different software tasks. It contains reconfigurable processing fabric divided into slices that can be reconfigured independently. Algorithms are loaded sequentially onto the fabric for high performance. The chip architecture includes an ARC processor, memory controller, PCI controller, and programmable I/O. Its applications include wireless base stations, wireless local loops, and software-defined radio.
The document discusses VLSI design and a high-speed parallel multiplier project. It begins with an introduction to VLSI design including its history and various integrations from SSI to VLSI. It then provides an overview and motivation for the multiplier project. The project aims to implement efficient high-speed multiplication using Booth encoding, Wallace tree adders, and carry look-ahead adders to reduce the number of partial products and accelerate their accumulation. The document outlines the organization of the project report and chapters on Booth algorithms, Wallace trees, and carry look-ahead addition.
This document discusses the implementation methodology for a dual-mode GPS receiver. Key points include:
1. The receiver was developed using a structured custom design flow in 130nm CMOS technology with less than $25M of funding.
2. It includes multiple GPS processing blocks operating at different clock speeds from 16-96MHz and uses 44 independent power domains.
3. Significant effort was placed on minimizing both static and dynamic power through techniques like clock gating, optimized logic synthesis, and characterizing custom memory macros.
4. Circuit simulations were performed throughout the design process to predict and verify power consumption before and after layout.
5. Over 400 clock domains were implemented with multiple levels of gating
Under Water Wireless Control Using Zigbee For Transmissions SystemsIJERA Editor
The aim of this project is to develop under water communication system using the zigbee protocol stack. A robot can be defined as a programmable, self-controlled device consisting of electronic, electrical, or mechanical units. An industrial robot is officially defined by as an automatically controlled, reprogrammable, multipurpose, manipulator, programmable in three or more axes. Robots are especially desirable for certain work functions because, unlike humans, they never get tired. They can endure physical conditions that are uncomfortable or even dangerous; they can operate in airless conditions.
This document provides an overview of a project that implemented image filtering using VHDL on an FPGA board. It discusses designing filters like average, Sobel, Gaussian, and Laplacian filters. Cache memory and a processing unit were developed to hold pixel values and apply filter kernels. Different methods for multiplication in the convolution process were evaluated. Results showed the output images after applying each filter both in software and on the FPGA board. In conclusion, FPGAs provide reconfigurable, accelerated processing for image applications like filtering compared to general purpose computers.
Effect on Substation Engineering Costs of IEC61850 & System Configuration ToolsSchneider Electric
Change management, software configuration training, and human error all impact the cost associated with substation automation engineering. Object-oriented engineering approaches as defined in the IEC 61850 standard represent significant cost savings when compared to traditional methods using hardwire and Distributed Network Protocol (DNP3). New multivendor system configuration tools are described that further reduce substation automation engineering costs.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
This document discusses the design and implementation of a sequential state machine using integrated circuit techniques. It begins with an introduction that provides an overview of digital systems and sequential system design. It then discusses various logic design techniques for implementing sequential circuits, including programmable logic devices (PLDs), gate arrays, and standard cell-based systems. The rest of the document will discuss the design process for a sequential state machine and its implementation using these techniques.
Chi2011 Case Study: Interactive, Dynamic SparklinesLeo Frishberg
This document describes the development of interactive sparklines to help electronic engineers debug circuits. Sparklines condense hundreds of data points into a small visual space. Initially designed for static displays, the author's team created interactive sparklines to assist with debugging circuits in real-time. Through user research, they identified engineers' needs for fast, accurate data acquisition and visualizations that quickly detect problems. The team developed iterative designs based on user feedback to refine the sparklines for interactive debugging of high-speed serial data circuits.
Implementation of resource sharing strategy for power optimization in embedde...Alexander Decker
This document discusses the implementation of a resource sharing strategy to optimize power in embedded processors. The strategy is implemented at the hardware level in the decode stage of a 32-bit RISC processor with a 4-stage pipeline. By redefining some instructions to share common resources like adders and decoders, unnecessary switching activity is reduced, lowering dynamic power consumption. Power analysis shows the modified design consumes 3mW less power, a 2.65% improvement, across different clock frequencies compared to the original design. The proposed strategy successfully optimizes power through hardware-level resource sharing.
This document discusses challenges and requirements for low-power design and verification. It begins with an overview of how leakage is significantly increasing due to process scaling and how active power is now a major portion of power budgets. New strategies are needed to address process variations and enhance scaling approaches. The verification flows must support multi-voltage domain analysis and rule-based checking across voltage states while capturing island ordering and microarchitecture sequence errors. Low-power implementation introduces challenges for design representation, implementation across tools, and verification. Methodologies and design flows must be adapted to account for power and ground nets becoming functional signals.
This document contains a summary of Het Shah's resume. It lists his contact information, work experience of over 1 year at eInfochips working on chip design projects, educational background including a B.E. degree, and professional skills including languages and EDA tools. It also summarizes several chip design projects he worked on related to physical design, block placement, routing, timing closure, and power optimization.
Application scenarios in streaming oriented embedded-system designMr. Chanuwan
This document introduces the concept of application scenarios for streaming-oriented embedded system design. It defines application scenarios as sets of similar operation modes grouped by their resource usage. The document outlines a three-step methodology for incorporating application scenarios into the design process: 1) discovering scenarios by identifying and clustering similar operation modes, 2) deriving predictors to determine the active scenario, and 3) exploiting scenarios to optimize design aspects like energy efficiency. It also discusses different ways to classify and discover scenarios, and provides examples of how previous works have used scenarios to optimize memory usage, voltage scaling, and multi-task scheduling.
High performance energy efficient multicore embedded computingAnkit Talele
The document discusses high-performance energy efficient multicore embedded computing. It describes the challenges of achieving both high performance and low power consumption. Several approaches are examined at the architectural level, including heterogeneous multicore processors, cache partitioning, and wireless interconnects. Hardware-assisted middleware approaches like power gating and software approaches like task scheduling and migration are also covered. Finally, examples of commercial high-performance energy efficient multicore processors are provided. The document concludes that high-performance energy efficient computing is an important research area with applications from consumer electronics to supercomputing.
1. The document presents a simulation of a low power analog channel decoder for error correction implemented in 65nm CMOS technology.
2. The decoder uses analog circuitry operating in the sub-threshold region to perform decoding, allowing for ultra-low power operation below 40uW for throughput up to 2.5Mbps.
3. The decoder architecture includes an analog decoding core that implements the sum-product algorithm, digital interfaces for input and output, and a digital controller to manage timing.
DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSORVLSICS Design
Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream
to get increased throughput, and it lessens the total time to complete the work. . The major objective of this
architecture is to design a low power high performance structure which fulfils all the requirements of the
design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E
XC3E 1600e device with Xilinx tool.
What is an RPA CoE? Session 1 – CoE VisionDianaGray10
In the first session, we will review the organization's vision and how this has an impact on the COE Structure.
Topics covered:
• The role of a steering committee
• How do the organization’s priorities determine CoE Structure?
Speaker:
Chris Bolin, Senior Intelligent Automation Architect Anika Systems
zkStudyClub - LatticeFold: A Lattice-based Folding Scheme and its Application...Alex Pruden
Folding is a recent technique for building efficient recursive SNARKs. Several elegant folding protocols have been proposed, such as Nova, Supernova, Hypernova, Protostar, and others. However, all of them rely on an additively homomorphic commitment scheme based on discrete log, and are therefore not post-quantum secure. In this work we present LatticeFold, the first lattice-based folding protocol based on the Module SIS problem. This folding protocol naturally leads to an efficient recursive lattice-based SNARK and an efficient PCD scheme. LatticeFold supports folding low-degree relations, such as R1CS, as well as high-degree relations, such as CCS. The key challenge is to construct a secure folding protocol that works with the Ajtai commitment scheme. The difficulty, is ensuring that extracted witnesses are low norm through many rounds of folding. We present a novel technique using the sumcheck protocol to ensure that extracted witnesses are always low norm no matter how many rounds of folding are used. Our evaluation of the final proof system suggests that it is as performant as Hypernova, while providing post-quantum security.
Paper Link: https://eprint.iacr.org/2024/257
HCL Notes and Domino License Cost Reduction in the World of DLAUpanagenda
Webinar Recording: https://www.panagenda.com/webinars/hcl-notes-and-domino-license-cost-reduction-in-the-world-of-dlau/
The introduction of DLAU and the CCB & CCX licensing model caused quite a stir in the HCL community. As a Notes and Domino customer, you may have faced challenges with unexpected user counts and license costs. You probably have questions on how this new licensing approach works and how to benefit from it. Most importantly, you likely have budget constraints and want to save money where possible. Don’t worry, we can help with all of this!
We’ll show you how to fix common misconfigurations that cause higher-than-expected user counts, and how to identify accounts which you can deactivate to save money. There are also frequent patterns that can cause unnecessary cost, like using a person document instead of a mail-in for shared mailboxes. We’ll provide examples and solutions for those as well. And naturally we’ll explain the new licensing model.
Join HCL Ambassador Marc Thomas in this webinar with a special guest appearance from Franz Walder. It will give you the tools and know-how to stay on top of what is going on with Domino licensing. You will be able lower your cost through an optimized configuration and keep it low going forward.
These topics will be covered
- Reducing license cost by finding and fixing misconfigurations and superfluous accounts
- How do CCB and CCX licenses really work?
- Understanding the DLAU tool and how to best utilize it
- Tips for common problem areas, like team mailboxes, functional/test users, etc
- Practical examples and best practices to implement right away
Taking AI to the Next Level in Manufacturing.pdfssuserfac0301
Read Taking AI to the Next Level in Manufacturing to gain insights on AI adoption in the manufacturing industry, such as:
1. How quickly AI is being implemented in manufacturing.
2. Which barriers stand in the way of AI adoption.
3. How data quality and governance form the backbone of AI.
4. Organizational processes and structures that may inhibit effective AI adoption.
6. Ideas and approaches to help build your organization's AI strategy.
In the realm of cybersecurity, offensive security practices act as a critical shield. By simulating real-world attacks in a controlled environment, these techniques expose vulnerabilities before malicious actors can exploit them. This proactive approach allows manufacturers to identify and fix weaknesses, significantly enhancing system security.
This presentation delves into the development of a system designed to mimic Galileo's Open Service signal using software-defined radio (SDR) technology. We'll begin with a foundational overview of both Global Navigation Satellite Systems (GNSS) and the intricacies of digital signal processing.
The presentation culminates in a live demonstration. We'll showcase the manipulation of Galileo's Open Service pilot signal, simulating an attack on various software and hardware systems. This practical demonstration serves to highlight the potential consequences of unaddressed vulnerabilities, emphasizing the importance of offensive security practices in safeguarding critical infrastructure.
Programming Foundation Models with DSPy - Meetup SlidesZilliz
Prompting language models is hard, while programming language models is easy. In this talk, I will discuss the state-of-the-art framework DSPy for programming foundation models with its powerful optimizers and runtime constraint system.
Monitoring and Managing Anomaly Detection on OpenShift.pdfTosin Akinosho
Monitoring and Managing Anomaly Detection on OpenShift
Overview
Dive into the world of anomaly detection on edge devices with our comprehensive hands-on tutorial. This SlideShare presentation will guide you through the entire process, from data collection and model training to edge deployment and real-time monitoring. Perfect for those looking to implement robust anomaly detection systems on resource-constrained IoT/edge devices.
Key Topics Covered
1. Introduction to Anomaly Detection
- Understand the fundamentals of anomaly detection and its importance in identifying unusual behavior or failures in systems.
2. Understanding Edge (IoT)
- Learn about edge computing and IoT, and how they enable real-time data processing and decision-making at the source.
3. What is ArgoCD?
- Discover ArgoCD, a declarative, GitOps continuous delivery tool for Kubernetes, and its role in deploying applications on edge devices.
4. Deployment Using ArgoCD for Edge Devices
- Step-by-step guide on deploying anomaly detection models on edge devices using ArgoCD.
5. Introduction to Apache Kafka and S3
- Explore Apache Kafka for real-time data streaming and Amazon S3 for scalable storage solutions.
6. Viewing Kafka Messages in the Data Lake
- Learn how to view and analyze Kafka messages stored in a data lake for better insights.
7. What is Prometheus?
- Get to know Prometheus, an open-source monitoring and alerting toolkit, and its application in monitoring edge devices.
8. Monitoring Application Metrics with Prometheus
- Detailed instructions on setting up Prometheus to monitor the performance and health of your anomaly detection system.
9. What is Camel K?
- Introduction to Camel K, a lightweight integration framework built on Apache Camel, designed for Kubernetes.
10. Configuring Camel K Integrations for Data Pipelines
- Learn how to configure Camel K for seamless data pipeline integrations in your anomaly detection workflow.
11. What is a Jupyter Notebook?
- Overview of Jupyter Notebooks, an open-source web application for creating and sharing documents with live code, equations, visualizations, and narrative text.
12. Jupyter Notebooks with Code Examples
- Hands-on examples and code snippets in Jupyter Notebooks to help you implement and test anomaly detection models.
Connector Corner: Seamlessly power UiPath Apps, GenAI with prebuilt connectorsDianaGray10
Join us to learn how UiPath Apps can directly and easily interact with prebuilt connectors via Integration Service--including Salesforce, ServiceNow, Open GenAI, and more.
The best part is you can achieve this without building a custom workflow! Say goodbye to the hassle of using separate automations to call APIs. By seamlessly integrating within App Studio, you can now easily streamline your workflow, while gaining direct access to our Connector Catalog of popular applications.
We’ll discuss and demo the benefits of UiPath Apps and connectors including:
Creating a compelling user experience for any software, without the limitations of APIs.
Accelerating the app creation process, saving time and effort
Enjoying high-performance CRUD (create, read, update, delete) operations, for
seamless data management.
Speakers:
Russell Alfeche, Technology Leader, RPA at qBotic and UiPath MVP
Charlie Greenberg, host
How information systems are built or acquired puts information, which is what they should be about, in a secondary place. Our language adapted accordingly, and we no longer talk about information systems but applications. Applications evolved in a way to break data into diverse fragments, tightly coupled with applications and expensive to integrate. The result is technical debt, which is re-paid by taking even bigger "loans", resulting in an ever-increasing technical debt. Software engineering and procurement practices work in sync with market forces to maintain this trend. This talk demonstrates how natural this situation is. The question is: can something be done to reverse the trend?
TrustArc Webinar - 2024 Global Privacy SurveyTrustArc
How does your privacy program stack up against your peers? What challenges are privacy teams tackling and prioritizing in 2024?
In the fifth annual Global Privacy Benchmarks Survey, we asked over 1,800 global privacy professionals and business executives to share their perspectives on the current state of privacy inside and outside of their organizations. This year’s report focused on emerging areas of importance for privacy and compliance professionals, including considerations and implications of Artificial Intelligence (AI) technologies, building brand trust, and different approaches for achieving higher privacy competence scores.
See how organizational priorities and strategic approaches to data security and privacy are evolving around the globe.
This webinar will review:
- The top 10 privacy insights from the fifth annual Global Privacy Benchmarks Survey
- The top challenges for privacy leaders, practitioners, and organizations in 2024
- Key themes to consider in developing and maintaining your privacy program
Have you ever been confused by the myriad of choices offered by AWS for hosting a website or an API?
Lambda, Elastic Beanstalk, Lightsail, Amplify, S3 (and more!) can each host websites + APIs. But which one should we choose?
Which one is cheapest? Which one is fastest? Which one will scale to meet our needs?
Join me in this session as we dive into each AWS hosting service to determine which one is best for your scenario and explain why!
The Microsoft 365 Migration Tutorial For Beginner.pptxoperationspcvita
This presentation will help you understand the power of Microsoft 365. However, we have mentioned every productivity app included in Office 365. Additionally, we have suggested the migration situation related to Office 365 and how we can help you.
You can also read: https://www.systoolsgroup.com/updates/office-365-tenant-to-tenant-migration-step-by-step-complete-guide/
Freshworks Rethinks NoSQL for Rapid Scaling & Cost-EfficiencyScyllaDB
Freshworks creates AI-boosted business software that helps employees work more efficiently and effectively. Managing data across multiple RDBMS and NoSQL databases was already a challenge at their current scale. To prepare for 10X growth, they knew it was time to rethink their database strategy. Learn how they architected a solution that would simplify scaling while keeping costs under control.
[OReilly Superstream] Occupy the Space: A grassroots guide to engineering (an...Jason Yip
The typical problem in product engineering is not bad strategy, so much as “no strategy”. This leads to confusion, lack of motivation, and incoherent action. The next time you look for a strategy and find an empty space, instead of waiting for it to be filled, I will show you how to fill it in yourself. If you’re wrong, it forces a correction. If you’re right, it helps create focus. I’ll share how I’ve approached this in the past, both what works and lessons for what didn’t work so well.
[OReilly Superstream] Occupy the Space: A grassroots guide to engineering (an...
Multi Supply Digital Layout
1. SAME 2001
Session 2: DEA METHODOLOGY
MULTI-SUPPLY DIGITAL LAYOUT
Regis Santonja, Motorola
Volker Wahl, Motorola
Toulouse
silicon. Back-annotated simulations and static
timing analysis allow the designer to ensure that all
the timing constraints of the design are met.
Abstract
2. Example of timing constraints: the
In this paper, the principle of a technique called
quot;multi-supply digital layoutquot; is described. The use setup time
of this technique allows a reliable backannotation
between digital blocks that are NOT powered off Usually, there are two levels of complexity for
the same supplies, within an analog top-cell. The calculating the timing constraints of a flip-flop :
supplies do not have to have the same voltage
levels, thanks to the integration of level shifters for a) Before layout, when the clock is considered
voltage adaptation within the digital layout. It is perfect (no skew),
also applicable in systems where a supply can be
turned off while another one stays alive. This b) After layout, when a clock skew shows up.
technique also optimizes the die size with no extra
efforts, reduces the layout phase and optimizes scan Dealing with a multiple supply layout adds another
insertion and ATPG. level of complexity because we need level shifters
on some data and clock paths. The diagram below
Index Terms – Layout, level shifter, back- summarizes the situation.
annotation, scan, low power, multiple supplies,
standard cells.
Level
I. Introduction
shifters
The goal of this paper is to present why and how to
make a multiple supply digital layout.
We will present a flow which covers all the steps
from the RTL design down to the layout, using only Where δclk(i) is the delay for the clock root driver to the pin of flip-flop i,
standard CAD tools. We will also compare this δck2q is the transition time of the flip-flop, δd is the data path delay and Tclk
is the clock period.
technique with the existing literature on the subject,
and explain why it is best suited towards our needs In order for the layout tool to generate a balanced
in terms of resulting area, layout development time, clock tree, one needs to have a logical and a timing
and scan test. model for the level shifters. The level shifters are
presented in section III.4.
1. What is post-layout back-annotation ?
3. Why do we need several power
It is the process of calculating the cell delays based supplies in a design?
on the final routing, and putting these delays into
the cell models for simulation or static timing
There are two reasons for using several power
analysis.
supplies, both of which are necessary for power
management chips. This kind of circuit is very
Back-annotation is needed in order to ensure that
common in mobile phones. They are used for
the functionality is kept from RTL design down to
SAME 2001, November 15th 2001 1
2. regulating and distributing the power supplies to the In section V, we present a program which generates
other chips in the telephone. scripts for Silicon Ensemble. In section VI, we
present our multiple voltage clock tree solution.
Finally, section VII presents a possibility for
a) Reducing Power Consumption
enhancing the flow in the future.
Reducing the power consumption of portable
II. Prior Art
devices such as mobile phones, PDAs or portable
PCs has become one of the most important goals of
the semiconductor industry. As exposed in section 1. Interfacing circuits that operate at
II.3. of this paper, using several power supplies is
different voltage levels.
one of the most effective techniques to reduce
power consumption.
On analog-oriented chips where several digital
blocks powered off different supplies have to be
b) Interfacing circuits that operate at laid out on the same silicon, the traditional way to
different voltage levels. do this was to design and layout the digital blocks
separately, place them as macro cells in the analog
The second reason for using several power supplies top cell of the chip, then use an analog router such
is to interface circuits that operate at several as IC Craftsman to interconnect the blocks.
voltages. Power management chips include a variety
of programmable functions (such as an audio
codec, an ADC used to monitor the supply levels, a
touch screen interface, a USB, an RS232 port,
etc…). The most effective technique is to have each
of these functions controlled by a logic powered off
the same voltage which is required for the
function’s interface.
A simplified example of how a power management
chip can be in the heart of a multiple supply system
is presented below: we have a processor with inputs
and outputs operating at 1.8V and a core at 2.5V. This method had the following disadvantages:
The power management chip communicates through
its serial interface (SPI) operating at 1.8V with an a) There was no way to use the inter-block
embedded real time clock powered off an external connections' parasitics and generate a standard
Lithium cell at 3.2V. SDF file for back-annotation.
b) Three digital layouts had to be done separately
with no way to globally re-order the scan chain.
c) Three tools and environments had to be used:
Silicon Ensemble, Cadence Framework II
(Virtuoso) and IC Craftsman.
d) Tools such as IC Craftsman and Virtuoso from
Cadence are analog tools and not familiar to
most of the digital designers.
2. Sophisticated layout techniques found
in the literature.
The authors in [1] [2] [3] [4] and [5] have already
proposed some techniques to layout multiple supply
The organization of this paper is the following. In circuits. However, they have started from a different
section II, we present the prior art in multiple situation: they have a single supply circuit and want
supply layout and show why it is not adapted to our to save power by multiplying the number of its
needs. In section III, we present our layout solution. supplies. For doing this, they split the circuit at the
In section IV we present the design flow and how to gate level and assign to each gate the power supply
integrate the analog level shifters in the digital flow. which best matches its timing requirements, with no
SAME 2001, November 15th 2001 2
3. respect to the function implemented, in such a way they do not have the same ground. The picture
that a given function can be spread over several below represents two inverters. We can see that
supplies. As the number of connections within a without the isolation, vss1 and vss2 would short
function is statistically much bigger than the number together.
of connections between the functions, this method
(called gate-level voltage scaling) generates a lot of
routing between the supplies. Because of this, these
authors have developed sophisticated techniques in
order to minimise the routing. However, the
drawback is that the placement algorithm has to be
modified. For example, Chingwei Yeh and Yin- Note that there is a minimum ring width and
Shuin Kang in [1] and [4] have proposed a distance required between the rings.
modification of the simulated annealing by
introducing a new cost function associated with
2. Layout style
voltage clustering.
In opposition to the prior art, our starting point is to
These methods cannot be used for our designs, as
develop a chip which is already, by nature, a
we require to use standard CAD tools.
multiple supply circuit. In fact, we could say that
another type of voltage scaling technique
3. How can we reduce power by using (architecture voltage scaling) was used at the
multiple supplies? system level, resulting in the definition of a chip in
which all the functions (control, real time clock, SPI
This technique - called gate level voltage scaling - interface etc…) have been assigned to a voltage
consists in using a low supply voltage for the parts supply. For this reason, we do not encounter the
of the circuit that do not suffer from the implied same issues than these authors concerning the
transistor performance degradation, and keep a routing. Thus, our layout solution has the following
higher voltage level for the critical paths of the advantages:
circuit. Effectively, lowering the voltage is the most
effective technique for reducing CMOS power • it is the simplest,
consumption because the latter is proportional to • it works fine with standard cell-based layout
the square of the supply voltage. tools (no need to modify the placement
algorithm),
4. What about clock distribution? • it includes all the necessary level shifters,
• it makes it easy to isolate the voltage regions
Many papers have been published since 1990 about from each other with a negligible impact on the
generating a zero skew clock tree [7]. Various overall area,
algorithms have been proposed for single supply, as • cells can be abutted in each voltage region as in
well as for dual supply circuits [2] [8]. However, in usual single-supply layouts.
[2], Usami et al. propose a clock tree structure
where the leaves have to be in the low voltage These last two points can result in significant area
region: the tree does not reach the flip-flops in the savings compared to the prior art. And if we
other region. compare to section II.1, the listed disadvantages
have disappeared:
We’ll see in section VII. that we propose a
technique allowing a given clock tree to drive flip- a) We can now generate a single standard SDF
flops in both low and high voltage regions. file for back-annotation. All the inter-region
connections are taken into account.
III. Our layout solution b) Only one digital layout had to be done with the
possibility to globally re-order the scan chain.
1. Supplies isolation within the epi c) Only one layout tool is used: Silicon Ensemble,
and no analog tool.
d) Silicon Ensemble is familiar to most of the
Because we are in a mixed-signal environment, we
digital designers.
have to pay attention to the transitions in the digital
domain that might generate commutation noise on
In practice, we grouped the cells powered by the
sensitive analog blocks. For this reason, the digital
same voltage in 3 voltage regions, as presented
has to be surrounded by an isolation ring. In the
below. Note that the three regions are separated by
same manner, we isolate the digital blocks operating
the necessary isolation ring.
at different voltages from each other, especially if
SAME 2001, November 15th 2001 3
4. 4. The signal goes from a low voltage to
a high voltage
Whenever a gate has to drive the input of another
gate operating at a higher voltage, a voltage
conversion is needed at the interface. Connecting
the low voltage signal directly to the high voltage
gate is not acceptable, even though it would be the
Two issues have to be taken into account when a
simplest solution. The simulation plot below shows
signal goes from one voltage to another one:
this situation with two inverters, the first one being
operating at a lower supply than the second one.
3. The signal goes from a high voltage to When a falling edge is presented at the input of the
a low voltage first inverter, there is a static current consumption in
the second inverter because its PMOS is weakly
The first issue that can show up is associated with opened.
antenna diodes that can allow a static current to
flow from the high to the low voltage region. output Curent in second
Effectively, charge-collecting antennas are formed inverter
during wafer processing when an interconnect (field
input
poly or metal) is connected to a poly gate that does 50 µA
no yet have an electrical connection to diffusion. A
connection to diffusion is typically completed at the 130 mV
top level of metal, so conductors below the top level
of metal are generally considered responsible for
damage from collecting charge during plasma
processing. Therefore, antenna area ratio design
rules are commonly used in the semiconductor
The solution we adopted is to use a dual cascode
industry to ensure that the remaining charges do not
voltage switch (DCVS), which I call a “level
damage circuits [6].
shifter” in this paper. However, a usual level shifter
as presented in [3] has its output undefined
Many companies in the industry add systematically
whenever the input supply is turned off. For this
antenna diodes in their standard cells that are
reason, we have added a 2-input AND gate in order
connected on all input pins of the gates. These
to force the output low and a NMOS in order to cut
antenna diodes are either connected to the supply
any current which could flow to the ground as
(P-type diode) or to the ground (N-type diode),
shown below. The NMOS and the AND gate are
depending on the area cost for the cell.
controlled by a signal which is low when the input
As a consequence, the voltage supply is switched off.
type of the diodes
appears to be random,
leading to the risk of
having a static current
from the higher to the
lower voltage flowing
through a P-type diode,
as presented on the right.
In order to avoid this leakage, we can take
advantage from the cells which happen to have only
N-type antenna diodes, such as all the simple
buffers in the technology we used. The inserted cell
has to be powered off the low supply as presented
on the Figure below.
SAME 2001, November 15th 2001 4
5. layout of the cell. The second file is the TFL
The level shifter’s
(Timing Library File). It can be automatically
layout has been done
derived from the Design Compiler’s library using
in such a way that it
the syn2tlf program provided by Cadence. The TLF
looks like a standard
file is needed for CT-Gen (the Clock-Tree
cell’s layout except
Generator) in order to estimate the clock skew and
that it is “dual-rail”
the insertion delay of the clock tree.
as shown on the
right.
Silicon Ensemble generates a post-layout netlist
which includes the level shifters, and an RC file
which contains the list of all the capacitors and
IV. Design Flow and Libraries resistances of the routed nets. These two files can
then be read by the delay calculator which generates
The principle of the technique presented here is to a SDF file used for the back-annotation. The delay
avoid the need of using analog tools and tool calculator can be Design Compiler or Primetime
environments from RTL down to the layout. CAD from Synopsys, or any internal tool (quite often
tools all have to be digital and standard. In order to foundries have their own golden delay calculator).
stay in a pure digital environment, we had to write
all the digital libraries for the level shifters, just as V. Automated floorplan and
those that are used for normal standard cells:
placement
1. Verilog (HDL description)
A small program has been developed in order to
ease the floorplan generation. Based on the number
The verilog model of a standard level shifter is
of level shifters and the desired utilization
similar to the one of a buffer. In our case, the model
percentage of each voltage region, it proposes a
we used is similar to a 2-inputs AND gate. RTL
selection of floorplans with different aspect ratios
design is performed as usual, without any reference
for which it generates Silicon Ensemble scripts that
to the power supplies. The level shifters are
will initialize the floorplan, place the level shifters
instantiated within the RTL code.
automatically and route the horizontal and vertical
power stripes as represented below.
2. Design Compiler (Synthesis)
The level shifter’s timing parameters (fall/rise slew
rate and fall/rise transition delays) under all the
necessary PVT (process, voltage and temperature)
corners have been extracted from Spice simulations.
A Design Compiler .lib file has been generated and
compiled to a .db file so that the synthesis will treat
the level shifter as a standard cell.
3. Fastscan (ATPG)
A Fastscan model of the level shifters has been
Finally, the cells are gathered in groups, and each
generated, too, so that we can automatically
group is assigned to a region, so that the placement
generate scan patterns for the production test.
tool will locate each cell in the correct region.
Fastscan does not need any timing information. The
logical function is a 2-inputs AND gate, as for the
VI. Clock tree synthesis
verilog. From there, Fastscan treats the level shifter
as if it was a digital cell. Running ATPG is easier
The clock tree structure with dual supply voltages
because we can read the complete design in
presented in [2] handles clock domains in which all
Fastscan, rather than generating a set of scan
the flip-flops are only allowed to operate at the low
vectors for each region. In addition, the fault
voltage while meeting the timing constraints.
coverage is most probably higher.
We propose here a technique allowing a given clock
4. Silicon Ensemble (Place&Route)
tree to drive flip-flops in both low and high voltage
regions. However, the clock tree generator is not
Silicon Ensemble needs 2 library files for the level
allowed to place clock buffers in a voltage region
shifter. The first one is the LEF and is a view of the
which is different from the clock’s root driver.
SAME 2001, November 15th 2001 5
6. Effectively, we have to avoid that a clock buffer SDF file for each region, and merging them together
gets placed in a voltage region that is turned off if with a simple PERL script.
the corresponding branch is supposed to drive
functions that are in use (powered on). The dashed VIII. References
line on the diagram below symbolizes a dead branch
of the clock tree, which makes some functions in [1] Chingwei Yeh and Yin-Shuin Kang, Cell-Based
voltage regions 1 and 3 fail if voltage 2 is turned Layout Techniques Supporting Gate-Level Voltage
off. Scaling for Low Power. IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, Vol. 8 No.
5, October 2000.
[2] Kimiyoshi Usami, Mitsunori Igarashi, Fumihiro
Minami, Takashi Ishikawa, Masahiro Kanazawa,
Makoto Ichida, and Kazutaka Nogami, Automated
Low-Power Technique Exploiting Multiple Supply
Voltages Applied to a Media Processor. IEEE
Journal of solid-state Circuits, Vol.33, No.3, March
1998.
[3] C.Yeh and M.-C. Chang, Gate-level voltage
scaling for low-power design using multiple supply
The correct placement of the clock tree buffers is voltages. IEE Proc. Circuits Devices Syst., Vol.
managed by several steps, automated in a Unix shell 146, No. 6, December 1999.
script. There are as many CT-Gen runs as voltage
regions. The diagram below presents an example of [4] Chigwei Yeh, Yin-Shuin Kang, Shan-Jih Shieh,
a clock tree generation in voltage region 3: all Jinn-Shyan Wang, Layout Techniques Supporting
possible “holes” in the rows of regions 1 and 2 are the Use of Dual Supply Voltages for Cell-Based
filled with dummy filler cells. Then all cells in these Designs. Design Automation Conference, 1999.
regions are assigned the FIXED property in the Proceedings. 36th , 1999
DEF file (Silicon Ensemble ASCII database).
Finally, CT-Gen is launched. [5] Yi-Jong Yeh and Sy-Yen Kuo, An Optimization-
based low-power voltage scaling technique using
multiple supply voltages. Circuits and Systems,
2001. ISCAS 2001. The 2001 IEEE International
Symposium on , Volume: 5, 2001.
[6] Martin Polzl, A Strategy to Detect Charge
Damaging Process Steps within a Multilayer
Metallization Technology. 1997 2nd International
Symposium on Plasma Process-Induced Damage.
[7] G. E. Tellez and M. Sarrafzadeh, Clock period
constrained minimal buffer insertion in clock trees.
In Proceedings of the IEEE/ACM International
Once all the clock trees have been generated, the
Conference on Computer-Aided Design, 1994.
routing can be launched as for a usual layout, and
RC parasitics file can be generated as in the
[8] Jatuchai Pangjun and Sachim S. Sapatnekar,
standard way.
Clock Distribution Using Multiple Voltages in Low
Power Electronics and Design, 1999. Proceedings.
VII. Future enhancements 1999 International Symposium on , 1999.
By the chosen flow, all voltage regions will be [9] Alain Guyot and Sélim Abou-Samra, Low
back-annotated using the same PVT conditions, Power CMOS Digital Design in ICM’98, December
because only one SDF file is generated. A region 14-16 1998.
could impose its own voltage range (best case,
worst case) to the others, even if the latter have [10] Anantha P. Chandrakasan, Samuel Sheng, and
weaker voltage constraints. This problem could be Robert W. Brodersen, Low-Power CMOS Digital
eliminated by splitting the RC file, generating an Design in IEEE Journal of Solid-State Circuits. Vol.
27, No. 4, April 1992.
SAME 2001, November 15th 2001 6