1) Digital to analog converters (DACs) convert digital input signals into analog output signals. Common DAC circuit types include weighted resistor DACs, R-2R ladder DACs, switched current-source DACs, and switched-capacitor DACs.
2) R-2R ladder DACs use only two resistor values (R and 2R) which makes them easy to manufacture with less errors compared to weighted resistor DACs.
3) DAC resolution refers to the fineness of output voltage changes for each change in the least significant bit of the digital input. Higher resolution DACs allow for finer detail in the approximated analog output signal
The content is related to Analog electronics. The prEsentation contains ADC process, Sampling and holding, Quantizing and encoding, Flash ADC, Pipeline ADC etc.
The content is related to Analog electronics. The prEsentation contains ADC process, Sampling and holding, Quantizing and encoding, Flash ADC, Pipeline ADC etc.
This presentation contributes towards understanding the periodic function of a Laplace Transform. A sum has been included to relate the method for this topic and a video also so that the learning can be easy.
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Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
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Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
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This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
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Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
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Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
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👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
3. 2.1 – Sample & Hold (S&H) Circuit - continued
Control Signal
Rate of change of the output voltage when the control signal is in
the hold state ‐ due to leakage current.
4. 2.1 – Sample & Hold (S&H) Circuit - continued
Ideally =0 & it should be too small.
needed for the capacitance to achieve 0.993 Vi ≈ 0.7 % error.
5. 2.2 – Analogue-to-Digital (ADC)
DC level
n bits O/P
I/P Quantizer Encoder
Full Scale
ADC
After Sampling; the amplitude of the analogue samples is quantized & encoded using
either uniform or non-uniform quantization & encoding depending on the application
6. 2.3 – Quantization
• The quantizing operation approximates each sample value to the
nearest level in a finite set of discrete levels/values, known as
quantization levels.
• This approximation introduces quantization error. Therefore, once
quantized, the instantaneous values of the signals are lost, and can
never be reconstructed exactly.
Continuous signal values Discrete signal values
at discrete times at discrete times
Quantizer
7. 2.3 – Quantization (cont.)
• Quantization principle is based on that any human sense
(ear & eye) can only detect finite intensity differences.
as an ultimate receiver
There are 2 types of quantization:
1. Uniform quantization: biomedicine, audio systems.
2. Nonuniform quantization: communication systems for the need to compress
signals.
8. 2.3.1 – Uniform Quantization & Encoding
• The full scale range of the I/P signal is divided into 2n values; (n is the number of ADC bits).
• Each analogue sample is assigned to one of the 2n values by truncation.
• The difference between two adjacent values is called ‘Quantum’ or step size (a)
Vmax
111 3.5 a
110
e 2.5 a
n = 8 levels
Signal level
1.5 a
0.5 a 0
-0.5 a
010 -1.5 a VFSR
001
a -2.5 a
000
-3.5 a -Vmax
Unipolar (+Vm or ‐ Vm)
polar (±Vm)
FSR: Vmax - Vmin (swing). Mid‐tread Quantizer.
L: number of quantization levels L= 2n – 1
L= 2n Mid‐rise Quantizer.
n increases for audio applications as the ear is more sensitive than the eye.
9. 2.3.1 – Uniform Quantization & Encoding - Continued
Quantization Transfer Characteristics
Mid‐
tread
a=Q
Truncation leads to quantization noise
• Quantization noise is random & follows a zero-
mean uniform distribution (pdf). a/2
0
- a/2
Quantization Noise
11. 2.3.1 – Uniform Quantization & Encoding - Continued
rms
Not detected by ADC
12. 2.4 – Digital-to-Analogue Converter (DAC)
• What is a digital to analog converter (DAC)?
– Converts digital input signal to an analog output
signal
Bn-1 B0
1 0 0 0 1 1 1 Va
0 1 0 1 0 0 0
0 0 1 1 0 1 1 DAC
1 1 1 1 1 0 1 Circuit Symbol
B0
LSB
B1
B2
n: word‐length
MSB
13. 2.4 – Digital-to-Analogue Converter (DAC)…Cont.
• D/A conversion can be achieved
using a number of different
methods such as:
– The Weighted-Resistor DAC
– The Ladder Network (The R-2R Ladder DAC)
– The Switched Current-Source DAC
– The Switched-Capacitor DACs
14. 2.4.1 – Weighted Resistor DAC
Rf = R
∑I i
R 2R 4R 8R Vo
Most • summing amplifier
Significant
Bit
Least
Significant Bit
VREF
Large n very large R
16. 2.4.1 – Weighted Resistor DAC - continued
Advantage
– Easy principle (low bit DACs)
Disadvantages
– Requirement of several
different precise input
resistor values: one unique
value per binary input bit.
(High bit DACs)
– Larger resistors ~ more error.
– Precise large resistors –
expensive. VREF
17. 2.4.2 – R-2R Ladder Type DAC
R-2R Ladder Network
18. 2.4.2 – R-2R Ladder Type DAC (Cont.)
D 0 × 2 0 + D1 × 21 + D 2 × 2 2 + D 3 × 2 3
Vo = 4
Vref
2
Example: Circuit with 0110 input
19. 2.4.2 – R-2R Ladder Type DAC - continued
VREF
MSB
LSB
20. 2.4.2 – R-2R Ladder Type DAC - continued
• The less significant the bit, the more resistors the signal must
pass through before reaching the op‐amp
• The current is divided by a factor of 2 at each node
LSB MSB
21. 2.4.2 – R-2R Ladder Type DAC - continued
Rf ⎛ B2 B1 B0 ⎞
VOUT = VREF⎜ + + ⎟
R ⎝2 4 8⎠
Rf
22. 2.4.2 – R-2R Ladder Type DAC - continued
• Question:
– Input = (101)2
– VREF = 10 V
– R = 2 kΩ
– Rf = 2R
R R R 2R
R 2R 2R 2R
I0 I0
Op-Amp input
VREF VREF
“Ground”
B0 B2
23. 2.4.2 – R-2R Ladder Type DAC - continued
• Only two resistor values‐ R and 2R
• Does not need the kind of precision as Binary
weighted DACs
• Easy to manufacture
• More popular
• Less errors
24. 2.5– DAC Resolution
• Resolution: is the amount of variance in
output voltage for every change of the LSB in
the digital input.
• How closely can we approximate the desired
output signal(Higher Res. = finer detail=smaller
Voltage divisions)
• A common DAC has a 8 ‐ 12 bit Resolution
VRef
Resolution = VLSB =
2n
25. 2.5– DAC Resolution (Cont.)
• Voltage
Vref
resolution:
2n
Voltage step example : for 10 bit resolution. So n=10
if Vref = 10V
voltage step : 10V/1024 = 10mV
26. 2.5– DAC Resolution (Cont.)
Poor Resolution(1 bit) Better Resolution(3 bit)
Vout Vout
Desired Analog Desired Analog signal
signal
111
110 110
2 Volt. Levels
1
8 Volt. Levels
101 101
100 100
011 011
010 010
001 001
0 0 000
000
Digital Input Approximate Digital Input
Approximate
output output