8086 Introduction

ARCHITECTURE OF THE 8086 MICROPROCESSOR
The architecture of 8086 microprocessor employ parallel processing that is, they are implemented
with several simultaneously operating processing units. Figure illustrates the internal architecture
of the 8086 and 8086 microprocessors. They contain two processing units: the Bus Interface Unit
(BIU) and the Execution Unit (EU). Each unit has dedicated functions and both operate at the same
time. In essence, this parallel processing effectively makes the fetch and execution of instructions
independent operations. This results in efficient use of the system bus and higher performance for
8086/8086 microcomputer systems.
The bus interface unit is the 8086’s connection to
the outside world. By interface, we mean the path
by which it connects to external devices. The BIU’s
responsible for performing all external bus
operations, such as instruction fetching, reading
and writing of data operands for memory and
inputting or outputting data for input/output
peripherals. These information transfers take place
over the system bus. This bus includes an 16-bit
bidirectional data transfer, a 20-bit address bus, and
the signals needed to control transfers over the bus.
The BIU is not only responsible for performing bus
operations; it also performs other functions related
to instruction and data acquisition. It is responsible
for instruction queuing and address generation.
To implement these functions, the BIU contains the
segment registers, the instruction pointer, the
address generation adder, bus control logic, and an
instruction queue. Figure shows the bus interface
unit of 8086 in more detail. The BIU uses a mechanism known as an instruction queue to implement
a pipelined architecture. This queue permits the 8086 to pre-fetch up to 6 bytes of instruction code.
Whenever the queue is not full that is, it has room for at least 2 more bytes, and, at the same time,
the execution unit is not asking it to read or write data from memory the BIU is free to look ahead
in the program by pre-fetching the next sequential instructions. Pre-fetched instructions are held in
the first-in first-out (FIFO) queue. Whenever a byte is loaded at the input end of the queue, it is
automatically shifted up through the FIFO to the empty location nearest the output. Here the code
is held until the execution unit is ready to accept it. Since instructions are normally waiting in the
queue, the time needed to fetch many instructions of the microcomputer's program is eliminated.
If the queue is full and the EU is not requesting access to data in memory, the BIU does not need to
perform any bus operations. These intervals of no bus activity, which occur between bus
operations, are known as idle states.
The execution unit is responsible for decoding and executing instructions. It consists of the
arithmetic logic unit (ALU), status and control flags, general-purpose registers, and temporary-
operand registers. The EU accesses instructions from the output end of the instruction queue and
data from the general-purpose registers or memory. It reads one instruction byte after the other
from the output of the queue, decodes them, generates data addresses if necessary, passes them
to the BIU and requests it to perform the read or write operations to memory or I/O, and performs
Unit 1

the operation specified by the instruction. The ALU performs the arithmetic, logic, and shift
operations required by an instruction. During execution of the instruction, the EU may test the
status and control flags, and updates these flags based on the results of executing the instructions.
If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to the top
of the queue,
SOFTWARE MODEL OF THE 8086 MICROPROCESSOR
The purpose of developing a software model is to help the programmer in understanding the
operation of the microcomputer system from a software point of view. To be able to program
microprocessor, one does not need to know all of its hardware architectural features. For instance,
we do not necessarily need to know the function of the signals at its various pins their electrical
connection or their electrical switching characteristics. The function, interconnection, and
operation of the internal circuits of the microprocessor also may not need to be considered.
00000 External
Memory
Address Space
Code Segment
Data Segment
Stack
Segment
Extra Segment
FFFFF
0000
I/O Address
Space
FFFF
What is important to the programmer is to know the various registers within the device and to
understand their purpose, functions, operating capabilities, and limitations. Furthermore, it is
essential that the programmer knows how external memory and input/output peripherals are
organized, how information is arranged in registers, memory, and input/output, and how memory
and I/O are addressed to obtain instructions and data. This information represents the software
architecture of the processor. Unlike the architectures the software architecture changes only
slightly from generation to generation of processor.
The software model illustrates the software architecture of the 8086 microprocessor. Looking at
this diagram, we see that it includes 13 16-bit internal registers: the instruction pointer (IP), four
data registers (AX, BX, CX, and DX), two pointer registers (BP and SP), two index registers (SI and
DI), and four segment registers (CS, DS, SS, and ES). In addition, there is another register called the
status register (SR), with nine of its bits implemented as status and control flags.
Figure also shows that the 8086 architecture implements independent memory and input/output
address spaces. Here the memory address space is 1,048,576 bytes (1 Mbyte) in length and the I/O
address space is 65,536 bytes (64Kbytes) in length.
MEMORY ADDRESS SPACE AND DATA ORGANIZATION
As shown in Figure the 8086 microcomputer supports 1 M-byte of external memory. This memory
space is organized from a software point of view as individual bytes-of data stored at consecutive

addresses over the address range 0000016 to FFFFF16. Therefore, memory in 8086-based
microcomputer is actually organized as 8-bit byte, not as 16-bit words.
The 8086 can access any two consecutive bytes as a word of data. In this case, the lower-addressed
byte is the least significant byte of the word, and the higher-addressed byte is its most significant
byte. Figure shows how a word of data is stored in memory.
To permit efficient use of memory, words of data can be stored at what are called even or odd
addressed word boundaries. The least significant bit of the address determines the type of word
boundary. If this bit is 0, the word is at an even-address boundary that is, a word at an even-
address boundary corresponds to two consecutive bytes, with the least significant byte located at
an even address.
000
A word of data stored at an even-address boundary is said to be an aligned word that is, all aligned
words are located at an address that is a multiple of 2. On the other hand, a word of data stored at
an odd address boundary is called a misaligned word. Figure shows some aligned and misaligned
words of data.
The double word is another data form that can be processed by the 8086 microcomputer. A double
word corresponds to four consecutive bytes of data stored in memory; an example of double-word
data is a pointer. A pointer is a two-word address element that is used to access data or code in
memory. The word of this pointer that is stored at the higher address is called the segment base
address and the word at the lower address is called the offset.
Just like for words, a double word of data can be aligned or misaligned. An aligned double word is
located at an address that is a multiple of 4.
DATA TYPES
The preceding section identified the fundamental data formats of the 8086 as the byte (8 bits),
word (16 bits), and double word (32 bits). It also showed how each of these elements is stored in
memory. The next step is to examine the types of data that can be coded into these formats for
processing.
The 8086 microprocessor directly processes data expressed in a number of different data types. Let
us begin with the integer data type. The 8086 can process data as either unsigned or signed integer

numbers; each type of integer can be either byte-wide or word-wide. Figure represents an unsigned
byte integer; this data type can be used to represent decimal numbers in the range 0 through 255.
The unsigned word-integer is shown in Fig. it can be used to represent decimal numbers in the
range 0 through 65,535.
MSB LSB
D7 D0
MSB LSB
D15 D0
MSB LSB
D7 D0
MSB LSB
D15 D0
Sign Bit
The signed byte integer and signed word integer in Figs. are similar to the unsigned integer data
types just introduced; however, here the most significant bit is a sign bit. A zero in this bit position
identifies a positive number. For this reason, the signed integer byte can represent decimal
numbers in the range +127 to +128, and the signed integer word permits numbers in the range
+32,767 to +32,768, respectively.
MSB LSB MSB LSB
D7-D4=0000 D3-D0 D7-D4 D3-D0
BCD Digit0 BCD Digit 1 BCD Digit0
The 8086 can also process data that is coded as binary-coded decimal (BCD) numbersBCD data can
be stored in either unpacked or packed form. For instance, the unpacked BCD byte in Fig. shows
that a single BCD digit is stored in the four least significant bits, and the upper four bits are set to 0.
Figure shows a byte with packed BCD digits. Here two BCD numbers are stored in a byte. The upper
four bits represent the most significant digit of a two-digit BCD number.
Information expressed in ASCII (American Standard Code for Information Interchange) can also be
directly processed by the 8086 microprocessor.
SEGMENT REGISTERS AND MEMORY SEGMENTATION
Even though the 8086 has a 1 Mbyte address space, not all the memory is active at one time.
Actually, the 1 Mbytes of memory are partitioned into 64Kbyte segments. A segment represents an
independently addressable unit of memory consisting of 64K consecutive byte-wide storage
locations. Each segment is assigned base address that identifies its starting point that is, its lowest
address.
CS
Code Segment
SS
Stack Segment
DS Data Segment
ES
Extra Segment

Only four of these 64Kbyte segments are active at a time: the code segment, stack segment, data
segment, and extra segment. The segments of memory that are active, as shown in Fig. are
identified by the values of addresses held in the 8086's four internal segment registers: CS (code
segment), SS (stack segment), DS (data segment), and ES(extra segment). Each of these registers
contains a 16-bit base address that points to the lowest addressed location of the segment in
memory. Four segments give a maximum of 256Kbytes of active memory. Out of this 64K are for
program storage (code), 64Kbytes are for a stack, and 128Kbytes are for data storage.
The values held in these registers are referred to as the current-segment register values; for
example, the value in CS points to the first word-wide storage location in the current code segment.
Code is always fetched from memory as words, not as bytes.
Figure illustrates the segmentation of memory. In this diagram, the 64Kbyte segments are
identified with letters such as A, B, and C. The data segment (DS) register contains the value B.
Therefore, the second 64Kbyte segment of memory from the top, labeled B, acts as the current
data-storage segment. This is one of the segments in which data that are to be processed by the
microcomputer are stored. For this reason, this part of the microcomputer's memory address space
must contain read/write storage locations that can be accessed by instructions as storage locations
for source and destination operands. CS selects segment E as the code segment. It is this segment
of memory from which instructions of the program are currently being fetched for execution. The
stack segment (SS) register contains H, thereby selecting the 64Kbyte segment labeled as H for use
as a stack. Finally, the extra segment (ES) register is loaded with value J such that segment J of
memory functions as a second 64Kbyte data storage segment)
The segment registers are said to be user accessible. This means that the programmer can change
contents using software. Therefore, for a program to gain access to another part of memory, one
simply has to change the value of the appropriate register or registers. For instance, a new data
space, with up to 128Kbytes, is brought in simply by changing the values in DS and ES.
There is one restriction on the value assigned to a segment as a base address: it must reside on a
16-byte address boundary. This is because increasing the 16-bit value in a segment register by 1
actually increases the corresponding memory address by 16; examples of valid base addresses are
0000016, 0001016, and 0002016. Other than this restriction, segments can be set up to be
contiguous, adjacent, disjointed, or even overlapping.
DEDICATED, RESERVED AND GENERAL-USE MEMORY
Any part of the 8086 microcomputer's 1 Mbyte address space
can be implemented for the user's access; however, some
address locations have dedicated functions and should not be
used as general memory for storage of data or instructions of
a program. Let us now look at these reserved, dedicated use,
and general-use parts of memory.
Figure shows the reserved, dedicated-use, and general-use
parts of the 8086's address space. Storage locations from
address 0000016 to 0001316 are dedicated, and those from
address 0001416 to 0007F16 are reserved. These 128 bytes of
memory are used for storage of pointers to interrupt service
routines. The dedicated part is used to store the pointers for
the 8086's internal interrupts and exceptions. On the other
hand, the reserved locations are saved to store pointers that

are used by the user defined interrupts. The word of this pointer at the higher address is called the
segment base address and the word at the lower address is the offset. Therefore, this section of
memory contains up to 32 pointers.
The part of the address space labeled open in Fig. is general-use memory and is where data or
instructions of the program are stored. General-use area of memory is the range from addresses
8016 through FFFEF16.
At the high end of the memory address space is another reserved pointer area, located from
address FFFFC16 through FFFFF16. These four memory locations are reserved for use with future
products and should not be used. Intel Corporation has identified the 12 storage locations from
address FFFFO16 through FFFFB16 as dedicated for functions such as storage of the hardware reset
jump instruction. For instance, address FFFF016 is where the 8086 begins execution after receiving a
reset
INSTRUCTION POINTER
IP is also 16 bits in length and identifies the location of the next word of instruction code to be
fetched from the current code segment of memory. The IP is similar to a program counter;
however, it contains the offset of the next word of instruction code instead of its actual address.
This is because IP and CS are both 16 bits in length, but a 20-bit address is needed to access
memory. Internal to the 8086, the offset in IP is combined with the current value in CS to generate
the address of the instruction code. Therefore, the value of the address for the next code access is
often denoted as CS:IP.
During normal operation, the 8086 fetches instructions from the code segment of memory, stores
them in its instruction queue, and executes them one after the other. Every time a word of code is
fetched from memory, the 8086 updates the value in IP such that it points to the first byte of the
next sequential word of code that is, IP is incremented by 2. Actually, the 8086 pre-fetches up to
four bytes of instruction code into its internal code queue and holds them there waiting for
execution.
After an instruction is read from the output of the instruction queue, it is decoded; if necessary,
operands are read from either the data segment of memory or internal registers. Next, the
operation specified in the instruction is performed on the operands and the result is written back to
either an internal register or a storage location in memory. The 8086 is now ready to execute the
next instruction in the code queue.
Executing an instruction that loads a new value into the CS register changes the active code
segment; thus, any 64Kbyte segment of memory can be used to store the instruction code.
DATA REGISTERS
8086 has four general-purpose data registers. During program execution, they hold temporary
values of frequently used intermediate results. Software can read, load, or modify their contents.
Any of the general-purpose data registers can be used as the source or destination of an operand
during an arithmetic operation such as ADD or a logic operation such as AND. For instance, the
values of two pieces of data, A and B, could be moved from memory into separate data registers
and operations such as addition, subtraction, and multiplication performed on them. The
advantage of storing these data in internal registers instead of memory during processing is that
they can be accessed much faster.

The four registers, known as the data registers, are shown in more detail in Fig. They are referred to
as the accumulator register (A), the base register (B), the count register (C), and the data register
(D). These names imply special functions they are meant to perform for the 8086 microprocessor.
Figure summarizes these operations. String and loop operations use the C register; therefore, it is
given the name count register. Another example of the dedicated use of data registers is that all
input/output operations must use accumulator register AL or AX for data.
Each of these registers can be accessed either as a
whole (16 bits) for word data operations or as two 8-bit
registers for byte-wide data operations. An X after the
register letter identifies the reference of a register as a
word; for instance, the 16-bit accumulator is referenced
as AX. Similarly, the other three word registers are
referred to as BX, CX, and DX.
On the other hand, when referencing one of these
registers on a byte-wide basis, following the register
name with the letter H or L, respectively, identifies the
high byte and low byte. For the A register, the most
significant byte is referred to as AH and the least
significant byte as AL; the other byte-wide register pairs are BH and BL, CH and CL, and DH and DL.
When software places a new value in one byte of a register, say AL, the value in the other byte (AH)
does not change. This ability to process information in either byte location permits more efficient
use of the limited register resources of the 8086 microprocessor.
Actually, some of the data registers may also store address information such as a base address or
an input/output address; for example, BX could hold a 16-bit base address.
POINTER AND INDEX REGISTERS
The software model has four other general purpose registers and two index registers. Thev store
what are called offset addresses. An offset address represents the displacement of a storage
location in memory from the segment base address in a segment register, that is, it is used as a
pointer or index to select a specific storage location within a segment of memory. Software uses
the value held in an index register to reference data in memory relative to the data segment or
extra segment register, and a pointer register to access memory locations relative to the stack
segment register.
Just as for the data registers, the values held in these registers can be read, loaded, or modified
through software. This is done prior to executing the instruction that references the register for
address offset. Unlike the general-purpose data registers, the pointer and index registers are only
accessed as words. To use the offset address in a register, the instruction simply specifies the
register that contains the value.
Here is an example using two pointer registers, the stack pointer (SP) and base pointer (BP). The
values of SP and BP are used as offsets from the current value of SS during the execution of
instructions that involve the stack segment of memory and permit easy access to the locations in
the stack part of memory. That is, combining SP with SS as SS:SP resulting in an address that points
to the top of the stack.
BP is also used as offset relative to SS, but it is generating address using different addressing mode,
called base addressing mode or base indexed addressing mode. One common use of BP is to
Register Operations
AX Word multiply, word divide,
word I/O
AL Byte multiply, byte divide,
byte I/O, translate, decimal
arithmetic
AH Byte multiply, byte divide
BX Translate
CX String operations, loops
CL Variable shift and rotate
DX Word multiply, word divide,
indirect I/O

reference parameters that are passed to a subroutine by way of the stack. In this case, instructions
are included in the subroutine that use based addressing to access the values of parameters from
the stack.
The index registers are used to hold offset addresses for instructions that access data stored in the
data segment of memory and are automatically combined with the value in the DS or ES register
during address calculation. In instructions that involve the indexed addressing, the source index (SI)
register holds an offset address that identifies the location of a source operand, and the destination
index (DI) holds an offset for a destination operand.
Earlier we pointed out that any of the data registers can be used as the source or destination of an
operand during an arithmetic operation such as ADD, or a logic operation such as AND. However,
for some operations, an operand that is to be processed may be located in memory instead of the
internal register. In this case, an index address is used to identify the location of the operand in
memory; for example, string instructions use the index registers to access operands in memory. SI
and DI, respectively, are the pointers to the source and destination locations in memory.
STATUS REGISTER
The status register is also called the flags register. It is a 16-bit register within the 8086. Figure
shows the organization of this register in more detail. Nine of its bits are implemented. Six of these
bits represent status flags: the carry flag (CF), parity flag (PF), auxiliary carry flag (AF), zero flag (ZF),
sign flag (SF), and overflow flag (OF). The logic state of these status flags indicate conditions that
are produced as the result of executing an instruction that is, after executing an instruction, such as
ADD, specific flag bits are reset (logic 0) or set (logic 1) based on the result that is produced.
Let us first summarize the operation of these flags:
1 The carry flag (CF): CF is set if there is a carry-out or a borrow-in for the most significant bit
of the result during the execution of an instruction. Otherwise, CF is reset.
2 The parity flag (PF): PF is set if the result produced by the instruction has even parity that is,
if it contains an even number of bits at the 1 logic level. If parity is odd, PF is reset.
3 The auxiliary carry flag (AF): AF is set if there is a carry-out from the low nibble into the high
nibble or a borrow-in from the high nibble into the low nibble of the lower byte in a 16-bit
word. Otherwise, AF is reset.
4 The zero flag (ZF): ZF is set if the result produced by an instruction is zero. Otherwise, ZF is
reset.
5 The sign flag (SF): The MSB of the result is copied into SF. Thus, SF is set if the result is a
negative number or reset if it is positive.
6 The overflow flag (OF): When OF is set, it indicates that the signed result is out of range. If
the result is not out of range, OF remains reset.
The other three implemented flag bits the direction flag (DF), the interrupt enable flag (IF), and the
trap flag (TF) are control flags. These three flags provide control functions of the 8086 as follows:

7 The trap flag (TF): If TF is set, the 8086 goes into the single-step mode of operation. When in
the single-step mode, it executes an instruction and then jumps to a special service routine
that may determine the effect of executing the instruction. This type of operation is very
useful for debugging programs.
8 The interrupt flag (IF): For the 8086 to recognize maskable interrupt requests at its interrupt
(INT) input, the IF flag must be set. When IF is reset, requests at INT are ignored and the
maskable interrupt interface is disabled.
9 The direction flag (DF): The logic level of DF determines the direction in which string
operations will occur. When set, the string instruction automatically decrements the
address; therefore, the string data transfers proceed from high address to low address. On
the other hand, resetting DF causes the string address to be incremented that is, data
transfers proceed from low address to high address.
GENERATING A MEMORY ADDRESS
A segment base and an offset describe a logical address in the 8086 microcomputer system. As Fig.
shows, both the segment base and offset are 16-bit quantities, since all registers and memory
locations used in address calculations are 16 bits long. However, the physical address that is used to
access memory is 20 bits in length. The generation of the physical address involves combining a 16-
bit offset value that is located in the instruction pointer, a base register, an index register, or a
pointer register and a 16-bit segment base value that is located in one of the segment registers.
The source of the offset value depends on which type of memory reference is taking place. It can be
the base pointer (BP) register, stack pointer (SP) register, base (BX) register, source index (SI)
register, destination index (DI) register, or instruction pointer (IP). An offset can even be formed
from the contents of several of these registers. On the other hand, the segment base value always
resides in one of the segment registers: CS, DS, SS, or ES.
For instance, when an instruction acquisition
takes place, the source of the segment base
value is always the code segment (CS)
register, and the source of the offset value is
always the instruction pointer (IP). This
physical address can be denoted as CS:IP. On
the other hand, if the value of a variable is
written to memory during execution of an
instruction, typically the segment base value
is specified by the data segment (DS) register and the offset value by the destination index (DI)
register that is, the physical address is given as DS:DI. A provision called the segment-override
prefix is used to change the segment from which the variable is accessed; for example, a prefix
could be used to make a data access occur in which the segment base is in the ES register.
Another example is the stack address that is needed when pushing parameters onto the stack. This
physical address is formed from the values of the segment base in the stack segment (SS) register
and offset in the stack pointer (SP) register and is described as SS:SP.
Figure shows how a segment base value in a segment register and an offset value are combined to
form a physical address. The value in the segment register is shifted left by four bit positions, with
its LSBs filled with zeros. This gives a segment address, the location where the segment starts. The
offset value is then added to the 16 LSBs of the shifted segment value. The result of this addition is
the 20-bit physical address.

Actually, many different logical addresses map to the same physical address location in memory.
Simply changing the segment base value in the segment register and its corresponding offset does
this.
THE STACK
The stack is implemented in the memory of the 8086 microprocessor, and it is used for temporary
storage of information such as data or addresses. For instance when a call instruction is executed,
8086 automatically pushes the current values in CS and IP onto the stack. As part of the subroutine,
the contents of other registers may also be saved on the stack by executing PUSH instruction. Near
the end of the subroutine, POP instructions are included to pop values from the stack back into
their corresponding internal registers. At the end of the subroutine, a RET instruction causes the
values of CS and IP to be popped off the stack and put back into the internal register where they
originally resided.
The stack is 64Kbytes long and is organized from a software point of view as 32K words. Figure
shows that the segment base value in the SS register points to the lowest address word in the
current stack. The contents of the SP and BP register offset into the stack segment of memory.
Looking at Fig. we see that SP contains an offset value that points to a storage location in the
current stack segment. The address obtained from the contents of SS and SP (SS:SP) is the physical
address of the last storage location in the stack to which data were pushed. This memory address is
known as the top of the stack. At the micro computer's startup, the value in SP is initialized to
FFFE16. Combining this value with the current value in SS gives the highest-addressed word location
in the stack (SS:FFFE16) that is, the bottom of the stack.
The 8086 can push data and address
information onto the stack from its
internal registers or a storage location in
memory. Data transferred to and from
the stack are word-wide, not byte-wide.
Each time a word is to be pushed onto the
top of the stack, the value in SP is first
automatically decremented by two, and
then the contents of the register are
written into the stack part of memory.
Therefore, the stack grows down in
memory from the bottom of the stack,
which corresponds to the physical
address SS:FFFE16, toward the end of the
stack, which corresponds to the physical
address obtained from SS and offset
000016 (SS:000016).
When a value is popped from the top of the stacks the reverse of this sequence occurs. The physical
address defined by SS and SP points to the location of the last value pushed onto the stack. Its
contents are first popped off the stack and put into the specific register within the 8086; then SP is
automatically incremented by two. The top of the stack then corresponds to the address of the
previous value pushed onto the stack.
Any number of stacks may exist in an 8086 microcomputer. Simply changing the value in the SS
register brings in a new stack. Although many stacks can exist, only one can be active at a time.

INPUT/OUTPUT ADDRESS SPACE
The 8086 has separate memory and input/output (I/O) address spaces. The I/O address space is the
place where I/O interfaces, such as printer and monitor ports, are implemented. Figure shows a
map of the 8086's I/O address space. Notice that this address range is from 000016 to FFFF16. This
represents 64Kbyte addresses; therefore, unlike memory, I/O addresses are only 16 bits long. Each
of these addresses corresponds to one byte-wide I/O port.
0000 I/O Address
Space
FFFF
The part of the map from address 000016 through 00FF16 is referred
to as page 0. Certain of the 8086's I/O instructions can perform only
input or output data-transfer operations to I/O devices located in this
part of the I/O address space. Other I/O instructions can input or
output data for devices located anywhere in the I/O address space.
I/O data transfers can be byte-wide or word-wide. Notice that the
eight locations from address 00F816 through 00FF16 are specified as
reserved by Intel Corporation and should not be used
ADDRESSING MODES OF 8086
Addressing mode indicates a way of locating data or operands. Depending upon the data types
used in the instruction and the memory addressing modes, any instruction may belong to one or
more addressing modes or some instruction may not belong to any of the addressing modes. Thus
the addressing modes describe the types of operands and the way they are accessed for executing
an instruction.
According to the flow of instruction execution, the instructions may be categorized as (i) Sequential
control flow instructions and (ii) Control transfer instructions.
Sequential control flow instructions are the instructions which after execution, transfer control to
the next instruction appearing immediately after it (in the sequence) in the program. For example,
the arithmetic, logical, data transfer and processor control instructions are sequential control flow
instructions.
The control transfer instructions, on the other hand, transfer control to some predefined address or
the address somehow specified in the instruction, after their execution. For example, INT, CALL, RET
and JUMP instructions fall under this category.
The addressing modes for sequential and control transfer instructions are explained as follows:
Immediate
In this type of addressing, immediate data is a part of instruction, and appears in the form of
successive byte or bytes.
Example: MOV AX, 0005H
In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit in
size.
Direct
In the direct addressing mode, a 16-bit memory address (offset) is directly specified in the
instruction as a part of it.
Example: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address may be
computed using 5000H as the offset address and content of DS as segment address. The effective
address here is (10H)X(DS) + 5000H
Register
In the register addressing mode, the data is stored in a register and it is referred using the particular
register. All the registers, except IP, may be used in this mode. ,
Example: MQV BX, AX.
Register Indirect
Sometimes, the address of the memory location which contains data or operand is determined in
an indirect way, using the offset registers. This mode of addressing is known as register indirect
mode. In this addressing mode, the offset address of data is in either BX or SI or DI registers. The
default segment is either DS or ES. The data is supposed to be available at the address pointed to by
the content of any of the above registers in the default data segment.
Example: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address is in BX. The effective
address of the data is given as (10H)X(DS)+[BX].
Indexed
In this addressing mode, offset of the operand is stored in one of the index registers. DS is the
default segment for index registers SI and DI. In case of string instructions DS and ES are default
segments for SI and DI respectively. This mode is a special case of the above discussed register
indirect addressing mode.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS. The effective address, in this case, is
computed as (10H)X(DS)+[SI].
Register Relative
In this addressing mode, the data is available at an effective address formed by adding an 8-bit or
16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default
(either DS or ES) segment. The example given below explains this mode.
Example: MOV AX, 50H[BX]
The effective address of the data is given as (10H)X(DS)+50H+[BX].
Base Indexed
The effective address of data is formed, in this addressing mode, by adding content of a base
register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default
segment register may be ES or DS.
Example: MOV AX, [BX] [SI]
Here, BX is the base register and SI is the index register. The effective address of the data is given as
(10H)X(DS)+[BX]+[SI].

Relative Based Indexed
The effective address is formed by adding an 8 or 16-bit displacement with the sum of contents of
any one of the base registers (BX or BP) and any one of the index registers, in a default segment.
Example: MOV AX, 50H [BX][SI]
Here, 50H is an immediate displacement, BX is a base register and SI is an index register. The
effective address of the data is given as (10H)X(DS)+[BX]+[SI]+50H.
For the control transfer instructions, the addressing modes depend upon whether the destination
location is within the same segment or in a different one. It also depends upon the method of
passing the destination address to the processor. Basically, there are two addressing modes for the
control transfer instructions, viz. inter-segment and intra-segment addressing modes.
If the location to which the control is to be transferred lies in a different segment other than the
current one, the mode is called inter-segment mode. If the destination location lies in the same
segment, the mode is called intra-segment mode.
Figure shows the modes for control transfer instructions.
Intrasegment Direct
In this mode, the address to which the control is to be transferred lies in the same segment in
which the control transfer instruction lies and appears directly in the instruction as an immediate
displacement value. In this addressing mode, the displacement is computed relative to the content
of the instruction pointer IP.
The effective address to which the control will be transferred is given by the sum of 8 or 16 bit
displacement and current content of IP. In case of jump instruction, if the signed displacement (d) is
of 8 bits( i.e. -128< d <+127), we term it as short jump and if it is of 16 bits (i.e. -32768<d<+32767),
it is termed as long jump.
Example: JMP SHORT LABEL
LABEL lies within -128 to +127 from the current IP content. Thus SHORT LABEL is 8-bit signed
displacement.
A 16-bit target address of a label indicates that it lies within - 32768 to + 32767. But a problem
arises when one requires a forward jump at a relative address greater than 32767 or backward
jump at relative address - 32768; in the same segment. Suppose current contents of IP are 5000H
then a forward jump may be allowed at all the displacement DISP so that IP + DISP = FFFFH or DISP
= FFFF - 5000 = AFFFH. Thus forward jumps may be allowed for all 16-bit displacement values from
Modes for control
transfer
instructions
Intersegment
Intersegment direct
Intersegment indirect
Intrasegment
Intrasegment indirect
Intrasegment direct

0000H to AFFFH. If displacement exceeds AFFFH i.e. from B000H to FFFFH, then all such jumps will
be treated as backward jumps. All such jumps are called NEAR PTR jumps and coded as below.
JMP NEAR PTR LABEL
Intrasegment Indirect
In this mode, the displacement to which the control is to be transferred, is in the same segment in
which the control transfer instruction lies, but it is passed to the instruction indirectly. Here, the
branch address is found as the content of a register or a memory location. This addressing mode
may be used in unconditional branch instructions.
Example: JMP [BX]
Jump to effective address stored in Bx. JMP [ BX + 5000H ]
Intersegment Direct
In this mode, the address to which the control is to be transferred, is in different segment. This
addressing mode provides a means of branching from one code segment to another code segment.
Here CS and IP of the destination are specified directly in the instruction.
Example JPM 5000H : 2000H
Jump to effective address 2000H in segment 5000H
Intersegment Indirect
In this mode, the address to which the control is to be transferred lies in a different segment and it
is passed to the instruction indirectly, i.e. contents of a memory block containing four bytes, i.e.
IP(LSB), IP(MSB), CS(LSB) and CS(MSB) sequentially. The starting address of the memory block may
be referred using any of the addressing modes, except immediate mode.
Example: JMP [2000H]
Jump to an address in the other segment specified at effective address 2000H in DS, that points to
the memory block.

MINIMUM-MODE AND MAXIMUM-MODE SYSTEMS
The 8086 microprocessor can be configured to work in either of two modes: the minimum mode or
the maximum mode. The minimum mode is selected by applying logic 1 to the MN/MX input.
Minimum mode 8086 systems are typically smaller and contain single microprocessor. Connecting
MN/MX pin to logic 0 selects maximum mode of operation. This configures the 8086 system for use
in larger systems and with multiple processors. This mode-selection feature lets the 8086 better
meet the needs of a wide variety of system requirements.
Depending on the mode of operation selected, the assignments for a number of the pins on the
microprocessor package are changed. As Fig. shows, the pin functions of the 8086 specified in
parentheses pertain to a maximum-mode system,
The signals of the 8086 microprocessor common to both modes of operation, those unique to
minimum mode and those unique to maximum mode, are listed in Fig. Here we find the name,
function, and type for each signal. For example, the signal RD is in the common group. It functions
as a read control output and is used to signal memory or I/O devices when the 8086 's systembus is
set up to read in data. Moreover, note that the signals hold request (HOLD) and hold acknowledge
(HLDA) are produced only in the minimum-mode system. If the 8086 is set up for maximum mode,
they are replaced by the request/grant bus access control lines RQ/GT0 and RQ/GT1
MINIMUM-MODE INTERFACE SIGNALS
When minimum mode operation is selected, the 8086 itself provides all the control signals needed
to implement the memory and I/O interfaces. Figure shows block diagrams of a minimum-mode
configuration of the 8086. The minimum-mode signals can be divided into the following basic
groups: address/data bus, states, control, interrupt, and DMA.
Unit 2
Common signals
Name Function Type
AD7-
AD0
Address/data bus Bidirectional
, 3-state
A15-A8 Addressbus Output,
3-state
A19/S6-
A16/S3
Address/status Output,
3-state
MN/MX Minimum/ maximum
Mode control
Input
RD Read control Output,
3-state
TEST Wait on test control Input
READY Wait state control Input
RESET System reset input
NMI Non-maskable
Interrupt request
input
INTB Interrup t request Input
CLK System clock input
Vcc +5V Input
GND Ground
Minimum mode signals (MN/MX=Vcc)
Name Function Type
HOLD Hold request Input
HLDA Hold acknowledge Output
WR Write control Output, 3-state
IO/M IO/memory control Output, 3-state
DT/R Data transmit/receive Output, 3-state
DEN Data enable Output, 3-state
SSO Status line Output, 3-state
ALE Address latch enable Output
INTA Interrupt acknowledge Output
Maximum mode signals(MN/MX= GND)
Name Function Type
RQ/GT1,0 Request/grant bus
access control
Bi-directional
LOCK Bus priority lock
control
Output, 3-state
S2-S0 Bus cycle status Output, 3-state
QS1, QS0 Instruction queue
status
Output

Address/Data Bus
Let us first look at the address/data bus.
In an 8086-based microcomputer
system, these lines serve two functions.
As an address bus, they are used to
carry address information to the
memory and I/O ports. The address bus
is 20 bits long and consists of signal
lines A0 through A19. A 20-bit address
gives the 8086 a 1 M byte memory
address space. However, only address
lines A0 through A15 are used when
accessing I/O. This gives the 8086 an
independent I/O address space that is
64Kbytes in length.
The sixteen data bus lines D0 through D15 are actually multiplexed with address lines A0 through
A15, respectively. For this reason, they are denoted as AD0 through AD15. When acting as a data
bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt-type
codes from an interrupt controller.
Status Signals
The four most significant address lines, A19 through A16 of 8086 are also multiplexed, but in this
case with status signals S6 through S3. These status bits are output on the bus at the same time
that data are transferred over the other bus lines.
Bits S4 and S3 together form a 2-bit binary code that identifies which of the internal segment
registers was used to generate the physical address that was output on the address bus during the
current bus cycle. These four codes and the registers they represent are shown in Fig.
Status line S5 reflects the status of another internal characteristic of the MPU. It is the logic level of
the internal interrupt enable flag. The status bit S6 is always at the 0 logic level.
Control Signals
The control signals are provided to support the memory and I/O interfaces of the 8086. They
control functions such as when the bus carries a valid address, which direction data are transferred
over the bus, when valid write data are on the bus, and when to put read data on the system bus.
Address latch enable (ALE) is a pulse to logic 1 that signals external circuitry when a valid address is
on the bus. This address can be latched in external circuitry on the l-to-0 edge of the pulse at ALE.
Using the IO/M (IO/memory) line, DT/R (data transmit/receive) line, and BHE(Bank High Enable)
line, the 8086 signals which type of bus cycle is in progress and in which direction data are to be
transferred over the bus. The logic level of IO/M tells external circuitry whether a memory or I/O
transfer is taking place over the bus. Logic 0 at this output signals a memory operation and logic 1
an I/O operation. The direction of data transfer over the bus is signaled by the logic level output at
DT/R. When this line is logic 1 the bus is in transmit mode and if forced to logic 0 the bus is in
receiving mode. That corresponds to write and read bus cycles respectively.

Logic 0 on BHE line is used as a memory enable signal for the most significant byte half of the data
bus, D8 through D15. This line also carries status bit S7.
The signals read (RD) and write (WR) indicate that a read bus cycle or a write bus cycle,
respectively, is in progress. The MPU switches WR to logic 0 to signal external devices that valid
write or output data are on the bus. On the other hand, RD indicates that the MPU is performing a
read of data off the bus. During read operations, one other control signal, DEN {data enable), is also
supplied. It enables external devices to supply data to the microprocessor.
One other control signal involved with the memory and I/O interface, the READY signal, can be used
to insert wait states into the bus cycle so that it is extended by a number of clock periods. This
signal is provided by way of an external clock generator device and can be supplied by the memory
or I/O subsystem to signal the MPU when it is ready to permit the data transfer to be completed.
Interrupt Signals
The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge (INTA).
INTR is an input to the 8086 that can be used by an external device to signal that it needs to be
serviced. This input is sampled during the final clock period of each instruction acquisition cycle.
Logic 1 at INTR represents an active interrupt request. When 8086 recognizes an interrupt request,
it indicates this fact to external circuit with pulses to logic 0 at INTA output.
TEST input is also related to the external interrupt interface. For example, execution of a WAIT
instruction causes the 8086 to check the logic level at the TEST input. If logic 1 is found at this input,
the MPU suspends operation and goes into what is known as the idle state. The MPU no longer
executes instructions; instead, it repeatedly checks the logic level of the TEST input waiting for its
transition back to logic 0. As TEST switches to 0, execution resumes with the next instruction in the
program. This feature can be used to synchronize the operation of the MPU to an event in external
hardware.
On the 0-to-1 transition of NMI, control is passed to a non-maskable interrupt service routine at
completion of execution of the current instruction. NMI is the interrupt request with highest
priority and cannot be masked by software.
The RESET input is used to provide a hardware reset for the MPU. Switching RESET to logic 0
initializes the internal registers of the MPU and initiates a reset service routine.
DMA Interface Signals
The direct memory access (DMA) interface of the 8086 minimum-mode microcomputer system
consists of the HOLD and HLDA signals. When an external device wants to take control of the
system bus, it signals this fact to the MPU by switching HOLD to the logic-1 level. When in the hold
state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, IO/M, DT/R, RD, WR, DEN, and
INTR are pulled to high impedance state. The 8086 signals external devices that it is in this state by
switching its HLDA output to logic 1.
MAXIMUM-MODE INTERFACE SIGNALS
When the 8086 microprocessor is set for the maximum-mode configuration, it produces signals for
implementing a multiprocessor/coprocessor system environment. Usually in this type of system
environment, some system resources are common to all processors. They are called global
resources. There are also other resources that are assigned to specific processors. These dedicated
resources are known as local or private resources.

In the maximum-mode system, facilities are provided
for implementing allocation of global resources and
passing bus control to other microprocessors sharing
the system bus.
8288 Bus Controller: Bus Commands and Control
Signals
8086 does not directly provide all the signals that are
required to control the memory, I/O, and interrupt
interfaces. Specifically, the WR, IO/M, DT/R, DEN,
ALE, and INTA signals are no longer produced by the
8086. Instead, it outputs a status code on three
signals lines, So, S1, and S2, prior to the initiation of
each bus cycle. This 3-bit bus status code identifies
which type of us cycle is to follow. S2S1S0 are input to
the external bus controller device, the 8288, which
decodes them to identify the type of MPU bus cycle.
In response, the bus controller generates the
appropriately timed command and control signals.
Figure shows the relationship between the bus status
codes and the types of bus cycles. Also shown are the
output signals generated to tell external circuitry
which type of bus cycle is taking place. These output signals are memory read command (MRDC),
memory write command (MWTC), advanced memory write command (AMWC), I/O read command
(IORC), I/O write command (I0WC), advanced I/O write command (AIOWC), and interrupt
acknowledge (INTA).
Status Inputs CPU Cycle 8288 Command
S0 S1 S2
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port lOWC /AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC,AMWC
1 1 1 Passive None
The other control outputs produced by the 8288 consist of DEN, DT/R and ALE. These three signals
provide the same functions as those described for the minimum mode.
Lock Signal
To implement a multiprocessor system, a signal called lock (LOCK) is provided on the 8086. This
signal is meant to be output (logic 0) whenever the processor wants to lock out the other
processors from using the bus. This would be the case when a shared resource is accessed.
Queue Status Signals
Two other signals produced by the 8086 in the maximum-mode are queue status outputs QS0 and
QS1 that form a 2-bit queue status code, QS1QS0. This code tells the external circuitry what type of

information was removed from the instruction queue during the previous clock cycle. Figure shows
the four different queue status codes.
QS1QS0 = 01 indicates that the first byte of an instruction was taken off the queue. As shown, the
fetch of the next byte of the instruction is identified by the code 11. Whenever the queue is reset
due to a transfer of control, the re-initialization code 10 is output.
Local Bus Control Signals
In a maximum-mode configuration, the minimum-mode HOLD and HLDA interface of the
8086/8086 is also changed. These two signals are replaced by request/grant lines RQ/GT0 and
RQ/GT1. They provide a prioritized bus access mechanism for accessing the local bus.
System Clock
The time base for synchronization of the internal and external operation of the microprocessor in a
microcomputer system is provided by the clock (CLK) input signal. 8284 IC is used to generate clock
for 8086. Fig below shows the block diagram of 8284 clock generator IC.
The standard way in which this clock
chip is used with the 8086 is to connect
a 15 or 24 MHz crystal between X1 and
X2. The crystal frequency is divided by 3
to generate 5 or 8 MHz clock signal. This
MOS level CLK output of 8284 is
connected to CLK input of 8086.
8284 also fetches two more clock
outputs peripheral clock (PCLK) and
oscillator clock (OSC). These signals are
provided to drive peripheral ICs. The
PCLK is half the frequency of CLK and is
TTL compatible. While OSC is crystal
frequency which is 3 times CLK
frequency.
8284 can also be driven by external clock source. The external clock is connected to EFI input. The
pin F/C selects between external frequency and crystal frequency.
The CSYNC input is used for external synchronization in multiple clock system.
BUS CYCLE AND TIME STATES
A bus cycle defines the basic operation that a microprocessor performs to communicate with
external devices. Examples of bus cycles are the memory read, memory write, input/output read,
and input/output write. A bus cycle corresponds to a sequence of events that start with an address
being output on the system bus followed by a read or write data transfer. During these operations,

the MPU produces a series of control signals to control the direction and timing of the bus. The bus
cycle of the 8086 microprocessors consists of at least four clock periods. These four time states are
called T1, T2, T3, and T4. During T1 the MPU puts an address on the bus. For a write memory cycle,
data are put on the bus during state T2 and maintained through T3 and T4. When a read cycle is to
be performed, the bus is first put in the high-Z state during T2 and then the data to be read must be
available on the bus during T3 and T4. These four clock states give a bus cycle duration of 125 ns X 4
= 500 ns in an 8-MHz 8086 system.
If no bus cycles are required, the microprocessor performs what are known as idle states. During
these states, no bus activity takes place. Each idle state is one clock period long, and any number of
them can be inserted between bus cycles. Figure shows two bus cycles separated by idle states. Idle
states are performed if the instruction queue inside the microprocessor is full and it does not need
to read or write operands from memory.
Wait states can also be inserted into a bus
cycle. This is done in response to a request
by an event in external hardware instead
of an internal event such as a full queue. In
fact, the READY input of the MPU is
provided specifically for this purpose.
Figure shows that logic 0 at this input
indicates that the current bus cycle should not be completed. As long as READY is held at the 0
level, wait states are inserted between states T3 and T4 of the current bus cycle, and the data that
were on the bus during T3 are maintained. The bus cycle is not completed until the external
hardware returns READY back to the 1 logic level. This extends the duration of the bus cycle,
thereby permitting the use of slower memory and I/O devices in the system.
HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE
The 8086's memory address space as shown in Fig is implemented as two independent 512K-byte
banks. They are called the low (even) bank and the high (odd) hank. Data bytes associated with an
even address (0000016, 0000216, etc.) reside in the low bank and those with odd addresses (0000116,
0000316, etc.) reside in the high bank.
Looking at the circuit diagram in Fig. we see that address bits A1 through A19 select the storage
location that is to be accessed. Therefore, they are applied to both banks in parallel. A0 and bank
high enable (BHE) are used as basic select signals. Logic 0 at A0 identifies an even-addressed byte of
data and causes the low bank of memory to be enabled. On the other hand, BHE equal to 0 enables
the high bank of access of an odd-addressed byte of data. Each of the memory banks provides half
of the 8086's 16-bit data bus. The lower bank transfers bytes of data over data lines D0 through D7,
while data transfers for a high bank use D8 through D15.
The 8086 microprocessor performs byte and word data transfers differently. Figure shows that
when a byte memory operation is performed in address X, which is an even address, a storage

location in the low bank is accessed. Therefore, A0 is set to logic 0 to enable the low bank of
memory and BHE to logic 1 to disable the high bank. As shown in the circuit diagram, data are
transferred to or from the lower bank over data bus lines D0 through D7.
On the other hand, to access a
byte of data at an odd address
such as X + 1 in Fig., A0 is set to
logic 1 and BHE to logic 0. This
enables the high bank of memory
and disables the low bank. Data
are transferred between the 8086
and the high bank over bus lines
D8 through D15.
Whenever an even-addressed
word of data is accessed, both the
high and low banks are accessed
at the same time. Figure
illustrates how a word at even
address X is accessed. Both A0
and BHE equal 0; therefore, both
banks are enabled. In this case,
two bytes of data are transferred
from or to one each low and high
banks at the same time. This 16-
bit word is transferred over the
complete data bus D0 through
D15. The bytes of an even-
addressed word are said to be
aligned and can be transferred
with a memory operation that
takes just one bus cycle.
A word at an odd addressed location is said to be unaligned. That is, the least significant byte is at
the lower address location in high memory bank. The odd byte of the word is located at address
X+1 and the even byte at address X+2.
Two bus cycles are required to access this Word. During the first bus cycle, the odd byte of the
word, which is located at address X + 1 in the high bank, is accessed. This is accompanied by select
signals A0 = 1 and BHE = 0 and a data transfer over D8 through D15. Next the 8086 automatically
increments the address so that A0 = 0. This represents the next address in memory which is even.
Then a second memory bus cycle is initiated. During this second cycle, the even byte located at X+2
in the low bank is accessed. The data transfer takes place over bus lines D0 through D7. This
transfer is accompanied by A0 = 0 and BHE = 1.
READ CYCLE.
The memory interface signals of a minimum-mode 8086 system are shown in Fig. The read bus
cycle begins with state T1. During this period, the 8086 outputs the 20-blt address of the memory
location to be accessed on its multiplexed address/data bus AD0 through AD15 and A16 through
A19. At the same time a pulse is also produced at ALE. The falling edge of this pulse is used to latch
the address in external circuitry.

Also at the start of T1, signals M/IO and DT/R are set to the 0 logic level. This indicates to circuitry in
the memory subsystem that a memory cycle is in progress and that the 8086 is going to receive
data from the bus. BHE signal is also output at this time.
Beginning with state T2, status bits S3
through S6 are output on the upper four
address bus lines A16 through A19.
Remember that bits S3 and S4 identify
external circuitry which segment register
was used to generate the address just
output. This status information is
maintained through periods T3 and T4.
Address/data bus lines AD0 through A15
are put in the high-Z state during T2. Late
in period T2, RD is switched to logic 0. This
indicates to the memory subsystem that a
read cycle is in progress. Then DEN is
switched to logic 0 to tell external circuitry
to put the data that are to be read from
memory onto the bus.
As shown in the waveforms, input data are read by the 8086 during T3, after which, as shown in T4,
the 8086 returns RD and DEN to the 1 logic level. The read cycle is now complete.
Figure shows a read cycle of 8-bit data in a maximum-mode 8086- based microcomputer system.
These waveforms are similar to those given for the minimum mode read cycle. The address and
data transfers that take place are identical. The only difference found in the maximum mode
waveforms is that a bus cycle status code S2, S1, S0, is output just prior to the beginning of the bus
cycle. This status information is decoded by the 8288 to produce control signals ALE, MRDC, DT/R,
and DEN.
WRITE CYCLE
The write bus cycle timing of the 8086 shown
in Fig. is similar to that given for a read cycle.
During T1 the address is output and latched
with the ALE pulse and M/IO is set to logic 1
to indicate that a memory cycle is in
progress. However, this time DT/R is
switched to logic 1. This signals external
circuits that the 8086 is going to transfer data
over the bus.
As T2 starts, the 8086 switches WR to logic 0.
This tells the memory subsystem that a write
operation is to follow over the bus. The 8086
puts the data on the bus late in T2 and
maintains the data valid through T4, The write of data into memory should be initiated as WR
returns from 0 to 1 early in T4. This completes the write cycle.

In maximum mode 8086-based system s0, s1 and s2 are output just prior to the beginning of the
bus cycle. This status information is utilized by 8288 to produce control signals ALE, MWTC,
AMWTC, DT/R and DEN
Wait States in the Memory Bus Cycle
Wait states can be inserted to lengthen the memory bus cycles of the 8086. This is done with the
ready input signal. Upon request from an event in hardware, for example, slow memory, the READY
input is switched to logic 0. This signals the MPU that the current bus cycle should not be
completed. Instead, it is extended by inserting wait states with duration Tw between periods T3
and T4. The data that were on the bus during T3 are maintained throughout the wait-state period.
In this way, the bus cycle is not completed until READY is returned back to logic 1.
In the maximum mode microcomputer system, the READY input of the MPU is supplied by the
READY output of the 8284 clock generator circuit.
MEMORY INTERFACE CIRCUITS
A memory interface diagram for a maximum-mode 8086-based microcomputer system is shown in
Fig. Here we find that the interface includes the 8288 bus controller, address bus latches and
address decoder, data bus transceiver/buffers, and bank write control logic.
The bus status code signals
S0, S1, and S2, which are
outputs of the 8086, are
supplied directly to the 8288
bus controller. Here they are
decoded to produce the
command and control signals
needed to control data
transfers over the bus.
The address bus is latched,
decoded, and buffered.
Address lines A0 through A19
are latched along with and
control signal BHE in the
address bus latch. The value
on latched address lines A17
through A19 is decoded to
produce chip enable outputs
CE0 through CE7. The 8288
bus controller produces the
address latch enable (ALE) control signal from S2, S1, and S0. ALE is applied to the CLK input of the
latches and strobes the bits of the address and bank high enable signal into the address bus latches.
These signals are buffered by the address latches. Latched address lines A0 through A16 and CE0
and CE7 are applied directly to the memory subsystem.
During read bus cycles, the MRDC output of the bus control logic enables the byte of data at the
outputs of the memory subsystem onto data bus lines D0 through D15.

During write operations to memory, the bank write control logic determines into which of the two
memory banks the data are written. This depends on whether a byte or word data transfer is taking
place over the bus. The latched bank high enable signal BHE and address line A0 are gated with the
memory write command signal MWTC to produce a separate write enable signal for each bank.
These signals are denoted as WRU through WRL. For example, if a word of data is to be written to
memory over data bus lines D0 through D15, both WRU and WRL are switched to the active 0 logic
level.
The bus transceivers control the direction of data transfer between the 8086 and memory
subsystem. The operation of the transceivers is controlled by the DT/R and DEN outputs of the bus
controller. DEN applied to the EN input of the transceivers and enables them for operation. DT/R
selects the direction of data transfer through the devices. It is connected to the DIR input of the
data bus transceivers. When a read cycle is in progress, DT/R is set to 0 and data are passed from
the memory subsystem to 8086 while during a write cycle, DT/R is switched to logic 1 and data are
carried from 8086 to the memory subsystem.
Address Latches and Buffers
The 74F373 and 8282/8283 are octal latches that can be used to implement the address latch
section of the 8086's memory interface circuit. It accepts eight inputs DI0 through DI7. During the
negative edge of ALE signal the address input is latched. The latched information in the flip-flops is
output at data outputs D0 through D7 when the output enable (OE) input is at logic 0.
In the 8086 microcomputer system, the 20 address lines (AD0-AD15, A16-A19) and the bank high
enable signal BHE are normally latched in the address bus latch. The circuit configuration shown in
Fig. below can be used to latch these signals. The latched outputs A0L through A19L and BHEL are
permanently enabled by fixing OE at the 0 logic level.
Data Bus Transceivers
The data bus transceiver of the bus interface circuit can be implemented with 74F245 or 8286/8287
octal bus transceivers ICs. Their bidirectional input/output lines are called A0 through A7 and B0
through B7. The G input is to enable the buffer, while DIR input is to select the direction of data
transfer. When interfaced the G input is connected to DEN output and DIR input is connected to
DT/R output of 8288.
Address Decoder
Address decoder is connected at the output side of address latch. Typically 2 to 4 or 3 to 8 decoder
is used as address decoder. Normally higher address lines are connected to the decoder inputs and
output lines CE0 to CE3/CE7 are connected to different devices to enable each of them on different
addresses.
PROGRAM STORAGE MEMORY ROM, PROM, AND EPROM
Read-only memory (ROM) is one type of semiconductor memory device. It is most widely used in
microcomputer systems for storage of the program that determines overall system operation. The
information stored within a ROM integrated circuit is permanent or nonvolatile. This means that
when the power supply of the device is turned off, the stored information is not lost.
ROM, PROM, and EPROM

For some ROM devices, information must be built in during manufacturing and for others the data
must be electrically entered. The process of entering data into a ROM is called programming. As the
name ROM implies, once entered into the device this information can be read only. Three types of
ROM devices exist. They are known as the mask-programmable read only memory (ROM), the one-
time programmable read-only memory (PROM), and the erasable programmable read-only memory
(EPROM).
Let us continue by looking more closely into the first type of device, the mask programmable read-
only memory. This device has its data pattern programmed as part of the manufacturing process.
This is known as mask programming. Once the device is programmed, its contents can never be
changed. Because of this and the cost for making the programming masks, ROMs are used mainly in
high-volume applications where the data will not change frequently.
The other two types of read-only memories, the PROM and EPROM, differ from the ROM in that the
data contents are electrically entered by the user. Programming is usually done with equipment
called a programmer. Both the PROM and EPROM are programmed in the same way. Once a PROM
is programmed, its contents cannot be changed. This is the reason they are sometimes called one-
time programmable PROMs. On the other hand, the contents of an EPROM can be erased by
exposing it to ultraviolet light. In this way, the device can be used over and over again simply by
erasing and reprogramming. PROMs and EPROMs are most often used during the design of a
product and for early production, when the code of the microcomputer may need to be changed
frequently.
Block Diagram of a ROM
A block diagram of a typical ROM is shown in Fig. Here
we see that the device has three sets of signal lines: the
address inputs, data outputs, and control inputs. This
block diagram is valid for a ROM, PROM, or EPROM. Let
us now look at the function of each of these sets of signal
lines.
The address bus is used to input the signals that select
between the data storage locations within the ROM
device. In Fig. below we find that this bus consists of 11
address lines, A0 through A10. With an 11-bit address,
the memory device has 211 = 2048 unique data storage
locations. The individual storage locations correspond to
addresses over the range 000000000002 = 00016 through
111111111112 = 7FF16.
Each bit of data is stored inside a ROM, PROM, or EPROM as either a binary 0 or binary 1. Actually,
8 bits of data are stored at every address. Therefore the total storage capacity of the device we are
describing is 2048 x 8 = 16,384 bits; that is, the device we are describing is really a 16K-bit ROM. By
applying the address of a storage location to the address inputs of the ROM, the byte of data held
at the addressed location is read out onto the data lines.
The control bus represents the control signals that are required to enable or disable the ROM,
PROM, or EPROM device. Two control leads output enable (OE) and chip enable (CE), are identified.
Logic 0 at OE enables the three state outputs, D0 through D7, of the device. If OE is switched to the
1 logic level, these outputs are disabled. Moreover, CE must be at logic 0 for the device to be active.

Read Operation
For a microprocessor to read a byte of data from the device, it must apply a binary address to
inputs A0 through A10. This address gets decoded inside the device to select the storage location of
the byte of data that is to be read. Then the micro processor must switch CE and OE to logic 0 to
enable the device and outputs.
After the inputs of the ROM are set up, the output appears immediately; however, in practice this is
not true. A short delay exists between address inputs and data outputs.
Access time tells us how long it takes to access data stored in a ROM. Here we assume that both CE
and OE are at their active 0 levels, and then an address is applied to the inputs of the ROM.
DATA STORAGE MEMORY SRAM AND DRAM
The memory section of a microcomputer system is normally formed from both read-only memories
(ROM) and random access read/write memories (RAM). The ROM is used to store permanent
information such as the microcomputer's program. RAM is different from ROM in two important
ways. First, we are able both to save data by writing it into RAM and to read it back for additional
processing. It is normally used to store data such as numerical and character data. The second
difference is that RAM is volatile; that is, if power is removed from RAM all data are lost.
Static and Dynamic RAMs
There are two types of RAMs in general use today, the static RAM (SRAM) and dynamic RAM
(DRAM). For static RAMs, data, once entered, remains valid as long as the power supply is not
turned off. While, to retain data in a DRAM, it is not sufficient just to maintain the power supply but
refreshing is also required. This is necessary because the storage elements in a DRAM are capacitive
nodes. If the storage nodes are not recharged at regular intervals of time, data would be lost. This
recharging process is known as refreshing the DRAM.
Block Diagram of a Static RAM
A block diagram of a typical static RAM IC is shown in
Fig. This diagram is much similar to the one for ROM.
Both have address lines, data lines, and control lines.
The data lines of the RAM, however, are bidirectional.
The structure of the data bus determines the
organization of the RAMs storage array. Here an 8-bit
data bus is shown. This type of organization is known
as a byte-wide RAM.
The address bus on the RAM in consists of the lines labeled A0 through A12. This 13-bit address is
what is needed to select between the 8K individual storage locations in an 8K x 8-bit RAM IC. The
16K x 4 and 64K x 1 devices have a 14-bit and 16-bit address bus, respectively.
To either read or write data from the RAM, the device must first be chip enabled. Just like for a
ROM, this is done by switching the CE input of the RAM to logic 0. The setting of the write enable
(WE) control input determines how the data lines operate. During all write operations to a storage
location within the RAM, the WE input must be switched to the active 0 logic level. This configures
the data lines as inputs. While, if data are to be read from a storage location, WE is left at the 1
logic level.

Standard Dynamic RAM ICs
Dynamic RAMs are available in higher densities than static RAMs. Some other benefits of using
DRAMs over SRAMs are that they cost less, consume less power, and their 16- and 18-pin packages
take up less space. For these reasons, DRAMs are normally used in applications that require a large
amount of memory.
A block diagram of the
device is shown in Fig.
Looking at the block
diagram we find that it
has eight address inputs,
A0 through A7, a data
input and data output
marked D and Q
respectively, and three
control inputs, row
address strobe (RAS),
column address strobe
(CAS), and read/write (W).
The storage array within
the 2164B is capable of storing 65,536 (64K) individual bits of data. To address this many storage
locations, we need a 16-bit address; however, this device's package has just 16 pins. For this
reason, the 16-bit address is divided into two separate parts: an 8-bit row address and an 8-bit
column address. These two parts are time-multiplexed into the device over a single set of address
lines, A0 through A7. First the row address is applied to A0 through A7. Then RAS is pulsed to logic 0
to latch it into the device. Next, the column address is applied and CAS strobed to logic 0. This 16-
bit address selects which one of the 64K storage locations is to be accessed.
Data are either written into or read from the addressed storage location in the DRAMs. Write data
are applied to the D input and read data are output at Q. The logic levels of control signals W, RAS,
and CAS tell the DRAM whether a read or write data transfer is taking place and control the three-
state outputs. As the output is put in the high-Z state during the write operation, the D input and Q
output of the DRAM can be tied together. The Q output is also in the high-Z state whenever CAS is
logic 1.
The key difference between the DRAM and SRAM is that the storage cells in the DRAM need to be
periodically refreshed; otherwise, they lose their data. To maintain the integrity of the data in a
DRAM, each of the rows of the storage array must typically be refreshed every 2 ms. All of the
storage cells in an array are refreshed by simply cycling through the row addresses. As long as CAS
is held at logic 1 during the refresh cycle, no data are output.
External circuitry is required to perform the address multiplexing, RAS/CAS generation, and refresh
operations for a DRAM subsystem. DRAM refresh controller ICs are available to permit easy
implementation of these functions.

TYPES OF INPUT/OUTPUT
The 8086 can employ two different types of I/O operations, namely isolated I/O and memory
mapped I/O. These I/O methods differ in the way they are mapped in the 8086’s address space. In
practice usually both type of I/O systems employed.
I/O devices are treated separate from memory. This is possible as software and hardware
architecture supports separate memory and I/O address spaces. 8086 supports memory map of
00000H to FFFFFH while I/O map of 0000H to FFFFH. And also it is possible to treat two consecutive
locations on either memory or I/O address space to be treated as word-wide data. i.e. locations
0011H and 0012H can be treated as two byte-wide ports or a single word-wide port.
The isolated method of I/O offers some advantages. One a complete 1MB address space is available
for use with memory. Another, special instructions are provided for isolated I/O operations. These
instructions are designed such that they maximize the I/O performance. While the disadvantage is
that the data transfer is possible between AL or AX and the I/O device.
In memory mapped mode the 8086 treats the I/O as a memory location. In 8086 based systems
addresses from E0000H to E0FFFH are dedicated to memory mapped I/O ports. These 4096 bytes
represent either 4096 byte-wide ports with addresses from E0000H to E0FFFH or can be
representing 2048 word-wide ports with interleaved addresses from E0000H to E0FFEH.
In this mode, instructions that affect memory locations are used instead of special I/O instructions.
This is advantageous as many instructions and addressing modes are available for performing I/O
operations. For example, direct logical or arithmetic operations (AND, OR, XOR, ADD, SUB etc.) can
be performed between the I/O port and internal registers (In isolated I/O mode the data transfer is
restricted to AL and AX only). This also has a disadvantage that the instructions are executed slower
than dedicated I/O instructions. Another disadvantage is that some part of memory address space
(E0000H to E0FFFH) is not available for memory.
ISOLATED I/O INTERFACE
The isolated I/O interface of 8086 permits them to communicate with the outside world. The I/O
data transfer takes place over the multiplexed address/data bus. This parallel bus permits easy
interface to peripherals such as parallel I/O expanders.
Unit 3

Minimum mode I/O Interface
Figure below shows the minimum mode isolated I/O interface for 8086 system. Here we find the
8086 interface circuitry and ports 0 to N. The circuits in the interface must be able to select I/O
port, latch input data and sample input data, synchronize the data transfer and translate between
TTL voltage levels and those required to operate the I/O devices.
In isolated I/O interface only AD0 to AD15 address/data lines are used instead of all AD0 to AD15
and A16 to A19. Also the interfacing requires ALE, BHE, RD, WR, M/IO, DT/R and DEN control signals
to accomplish the communication.
Maximum mode I/O Interface
In maximum mode, 8086 does not fetch all control signals directly, but instead S0, S1 and S2 are
decoded by 8288 bus controller to generate different control signals. For maximum mode I/O read
cycle I/O read Command (IORC) and for maximum mode write cycle I/O write command (IOWC and
AIOWC) are generated from 8288 bus controller. The 8288 also produces DT/R, DEN and ALE
signals.
I/O DATA TRANSFER
I/O ports in the 8086 microcomputers can be either byte-wide or word-wide. The port that is
accessed for input or output of data is selected by an I/O address. This address is specified as part
of the instruction that performs the I/O operation.
I/O addresses are 16 bit length and are output by 8086 to the isolated I/O interface over bus lines
AD0 to AD15. The bits A16 to A19 of the address lines are held at logic 0 during the T1 cycle of all
I/O bus cycles. Since 16 bits of address are used to address I/O ports, the 8086’s I/O address space
consists of 64K byte-wide I/O ports.
M/IO signal is forced to logic 0 to represent that I/O location is to be selected. During complete
cycle the signal remains logic 0 indicating I/O operation. An even or odd addressed port can be
addressed using A0 or BHE signals from 8086.
Also it is possible to access the ports as word-wide. With A0 and BHE both active (00) the even
addressed consecutive ports are accessed simultaneously. If the word-wide port is having odd

address, then two bus cycles are required to read or write a word-wide port. First bus cycle to
access odd addressed byte and next bus cycle to access even addressed byte.
I/O INSTRUCTIONS
Isolated I/O operations are executed using IN and OUT instructions. There are two types of these
instructions, direct I/O instructions and variable I/O instructions. These instructions are as follows:
Mnemonic Meaning Format Operation
IN Input direct IN Acc, Port (Acc)←(Port) Acc = AL or AX
Input indirect(variable) IN Acc, DX (Acc) ← ((DX))
OUT Output direct OUT Port, Acc (Port) ← (Acc)
Output indirect(variable) OUT DX, Acc ((DX)) ← (Acc)
These instructions can be used to transfer a byte or word of data. In the case of byte transfer, the
data are transferred over the lines D0 to D7. Word data are transferred over the lines D0 to D15.
All data transfers take place between I/O devices and 8086’s AL or AX register. For this reason the
method of performing I/O is known as accumulator I/O. Byte transfer involves AL, while word
transfer involves AX register. Specifying AL as source or destination defines a byte-wide port and AX
as source or destination defines word-wide port operations.
In direct I/O instructions, the address of I/O port is specified directly along with the instruction. An
eight bit address can be fed here, restricting address from 00 to FF, corresponding to page 0 in I/O
space. IN AL, 023H, transfers contents from port 23H to AL.
In variable I/O instructions the address of the port to be accessed lies in the register DX. Here a 16
bit address can be fed in register DX. The value of DX is representing absolute address as compared
to offset address in direct I/O instruction.
MOV DX, 01234H
IN AX, DX
This set of instruction loads address 1234H in DX
and then reads word-wide port 1234H
INPUT/OUTPUT BUS CYCLES
Waveforms for the 8086's I/O input (I/O read) bus cycle and I/O output (I/O write) bus cycle are
shown in Figs. below. Looking at the input and output bus cycle waveforms, the timing of M/IO
does not change. The 8086 switches it to logic 0 to indicate that an I/O bus cycle is in progress..It is
maintained at the 0 logic level for the duration of the I/O bus cycle.
As in memory cycles, the address is output together with ALE during clock period T1. Along with the
address BHE signal is also generated during this clock period T1. BHE is used along with A0 to select
between byte-wide and word-wide port. For the input bus cycle, DEN is switched to logic 0 to signal
the I/O interface circuitry when to put the data onto the bus and the 8086 reads the data off the
bus during period T3.
On the other hand, for the output bus cycle in the 8086 puts write data (DATA OUT) on the bus late
in T2 and maintains it during the rest of the bus cycle. This time WR switches to logic 0 to signal the
I/O section that valid data is on the bus.

INPUT BUS CYCLE OUTPUT BUS CYCLE
EIGHT-BYTE-WIDE OUTPUT PORTS USING ISOLATED I/O
Here is shown a circuit that can be used to implement parallel output ports in a microcomputer
system employing isolated I/O. This provides 8-byte-wide output ports that are implemented with
74F373 octal latches. In this circuit, the ports are labeled port 0 through port 7. These eight ports
give a total of 64 parallel output lines, which are labeled O0 through O63.
Here 8086's address/data bus is de-multiplexed just as was done for the memory interface. Notice
that two 74F373 octal latches are used to form a 16-bit address latch. These devices latch the
address A0 through A15 synchronously with the ALE pulse. The latched address outputs are labeled
A0L through A15L. Address lines A16 through A19 are not involved in the I/O interface.
Address/data bus lines AD0 through AD15 are also applied to one side of the 74F245 bus
transceiver. At the other side of the transceiver, data bus-lines D0 through D15 are shown
connecting to the output latches. It is over these lines that the 80866 writes data into the output
ports.
Address lines A0L and A15L provide two of the three enable inputs of the 74F138 input/output
address decoder. These signals are applied to enable inputs G2B and G1 respectively. The decoder
requires one more enable signal at its G2A input. It is supplied by the complement of M/IO. These
enable inputs must be G2BG1BG1 = 001 to enable the decoder for operation. The condition G2B = 0
corresponds to an even address and G = 0 represents the fact that an I/O bus cycle is in progress.
The third condition, G1 = 1, is an additional requirement that A15L be at logic 1 during all data
transfers for this section of parallel output ports.
The 3-bit code A3LA2LA1L is applied to select inputs CBA of the 74F138 l-of-8 decoder. When the
decoder is enabled, the P output corresponding to this select code switches to logic 0. Notice that
logic 0 at this output enables the WR signal to the clock (CLK) input of the corresponding output
latch. In this way, just one of the eight ports is selected for operation.
When valid output data are on D0 through D7, the 8086 switches WR to logic 0. This change in logic
level causes the selected 74F373 device to latch in the data from the bus. The outputs of the
latches are permanently enabled by the 0 logic level at the bus. The outputs of the latches are
permanently enabled by the 0 logic level at their OE inputs. Therefore, the data appear at the
appropriate port outputs.

The 74F245 in the circuit allows data to pass from the 8086 to the output ports. This is
accomplished by enabling the 74F245's DTR and G inputs with the DT/R and DEN signals, which are
at logic 1 and 0, respectively.
Not all address bits are used in the I/O address decoding. Here only latched address bits A0L, A1L,
A2L, A3L, and A15L are decoded. In this way, many addresses decode to select each of the I/O ports.
For instance, if all of the don't-care address bits are made 0, the address of PORT 0 is
1000000000000000002 = 8000H. However, if these bits are all made equal to 1 instead of 0, the
address is 111111111111100002 = FFF0H.
Both addresses enable PORT 0. In fact, every I/O address in the range from 8OOOH through FFF0H
that has its lower four bits equal to 00002 decodes to enable PORT 0.
EIGHT-BYTE-WIDE INPUT PORTS USING ISOLATED I/O
The circuit in Fig. below provides eight byte-wide input ports for an 8086 based microcomputer
system employing isolated I/O. The ports are labeled port 0 through port 7; however, this time the
64 parallel port lines are inputs, I0 through I63. Notice that eight 74F244 octal buffers are used to
implement the ports. These buffers are equipped with three-state outputs.
When an input bus cycle is in progress, the I/O address is first latched into the 74F373 address
latches. This address is accompanied by logic 0 on the M/IO control line. The M/IO is inverted and
applied to the G2A input of the I/O address decoder. If during the bus cycle address bit AOL = 0 and
A15L = 1, the address decoder is enabled for operation. Then the code A3LA2LA1L is decoded to
produce an active logic level at one of the decoder's outputs. For instance, an input of
A3LA2LA1L=001 switches the P1 output to logic 0. P1 is gated with RD to produce the G enable input
for the port 1 buffer. If both M/IO and P1 are logic 0, the G output of the control gate for port 1 is
switched to logic 0 and the outputs of the 74F244 are enabled. In this case, the logic levels at inputs
I8 through I15 are passed onto data bus lines D0 through D7, respectively. This byte of data is carried
through the enabled data bus transceiver to the data bus of the 8086. As part of the input
operation, the 8086 reads this byte of data into the AL register.

In practical applications, it is sometimes necessary within an I/O service routine to check the logic
level of certain input line. This is called polling, normally utilized to synchronize I/O routines with
external events.
INPUT/OUTPUT HANDSHAKING
In some applications, the microcomputer must synchronize the input or output of information to a
peripheral device. Synchronization is achieved by implementing what is known as handshaking as
part of the input/output interface.
A block diagram of a parallel printer interface is shown in Fig. Here we find 8 data output lines D0
through D7, and the two handshake control signals strobe (STB) and busy (BUSY). The MPU outputs
data representing the character to be printed through the parallel printer interface. Character data
are latched at the outputs of the parallel interface and are carried to the data inputs of the printer
over data lines D0 through D7. The STB output of the parallel printer interface is used to signal the
printer that new character data is available. Whenever the printer is already busy printing a
character, it signals this fact to the MPU with the BUSY input of the parallel printer interface. These
handshake signals are illustrated in Fig.
Let us now look at the sequence of events that take place at the parallel printer interface when
data are output to the printer. A flowchart of a subroutine that performs a parallel printer interface
character transfer operation is shown here. First the BUSY input of the parallel printer interface is
tested. This is done with a polling operation. That is, the MPU tests the logic level of BUSY
repeatedly until it is found to be at the not busy logic level. Busy means that the printer is currently
printing a character. While, not busy signals that the printer is ready to receive another character
for printing. After finding a not busy condition, a count of the number of characters in the printer
buffer (microprocessor memory) is read; a byte of character data is read from the printer buffer;
the character is output to the parallel interface; and then a pulse is produced at STB. This pulse tells
the printer to read the character off the data bus lines-. The printer is again printing a character and
signals this fact at BUSY. The handshake sequence is now complete. Now the count that represents

the number of characters in the buffer is decremented and checked to see if the buffer is empty. If
empty, the print operation is complete. Otherwise, the character transfer sequence is repeated.
Comparison of NMI and INTR interrupts
How many bytes are needed to store the starting addresses of ISR for 8086 ?
Ans. 8086 can implement 256 different interrupts. To store the starting adder ss of a single ISS
(Interrupt Service Subroutine), four bytes of memory space are required—two bytes to store the
value of CS and two bytes to store the IP value. Thus to store the starting address of 256 ISS, in all
256 × 4 = 1024 bytes = 1 KB will be required.
Indicate the number of memory spaces needed in stack when an interrupt occurs.
Ans. When an interrupt occurs, before moving over to starting address of the corresponding ISS,
the following are pushed into the stack: the contents of the flag register, CS and IP. Since each one
of the three are 2 bytes, hence a total of 6 bytes of memory space is needed in the stack to
accommodate the flag register, CS and IP contents.
What are meant by interrupt pointer and interrupt pointer table?
Ans. The starting address of an ISS in the 1 KB memory space is known as the interrupt pointer or
interrupt vector corresponding to that interrupt. The 1 KB memory space needed to store the
starting addresses of all the 256 ISS is called the interrupt pointer table.
NMI INTR
1. Non-maskable type. 1. Maskable type.
2. Higher priority. 2. Lower priority.
3. Edge triggered interrupt initiated on Low to
High transition.
3. Level triggered interrupt.
4. Must remain high for more than 2 CLK cycles. 4. Sampled during last CLK cycle of each
instruction.
5. The rising edge of NMI input is latched on-
chip and is serviced at the end of current
instruction.
5. No latching. Must stay high until
acknowledged by CPU.
6. No acknowledgement. 6. Acknowledged by INTA output signal.

Write down the steps, sequentially carried out
by the systems when an interrupt occurs.
Ans. When an interrupt occurs (hardware or
software), the following things happen:
The contents of flags register, CS and IP are
pushed on to the stack. TF and IF are cleared
which disable single step and INTR interrupts
respectively.
Program jumps to the starting address of ISS.
At the end of ISS, when IRET is executed in the
last line, the contents of flag register, CS and IP
are popped out of the stack and placed in the
respective registers. When the flags are
restored, IF and TF get back their previous
values.
Draw and discuss the interrupt pointer table
for 8086.
Ans. The interrupt pointer table for 8086 is
shown in Fig.
The 256 interrupt pointers are stored in
memory locations starting from 00000 H to
003FF H (1 KB memory space). The number
assigned to an interrupt pointer is called the
Type of the corresponding interrupt. As for example, Type 0 interrupt, Type 1 interrupt ... Type 255
interrupt. Type 0 interrupt has a memory address 00000 H, Type 1 has a memory address 00004 H,
while Type 255 has a memory address 003FF H. The first five pointers (Type 0 to Type 4) are
dedicated pointers used for divide by zero, single step, NMI, break point and overflow interrupts
respectively. The next 27 pointers (Type 5 to Type 31) are reserved pointers—reserved for some
special interrupts. The remaining 224 interrupts—from Type 32 to Type 255 are available to the
programmer for handling hardware and software interrupts.
Discuss the priority of interrupts of 8086.
Ans. 8086 tests for the occurence of interrupts in the following hierarchical sequence:
 Internal interrupts (divide-by-0, single step, break point and overflow)
 Non-maskable interrupt—via NMI
 Software interrupts—via INTn
 External hardware interrupt—via INTR
Hence, internal interrupts belong to the highest priority group and internal hardware interrupts are
the lowest priority group. Again, different interrupts are given different priorities by assigning a
type number corresponding to each priority—starting from Type 0 (highest priority interrupt) to
Type 255 (lowest priority interrupt). Thus, Type 40 interrupt is having more priority than Type 41
interrupt. If we presume that at any instant a Type 40 interrupt is in progress, then it can be
interrupted by any software interrupt, the non-maskable interrupt, all internal interrupts or any
external interrupt with a Type number less than 40.

Outline the events that take
place when 8086 processes an
interrupt.
Ans. Flowchart shows the manner
in which 8086 processes an
interrupt while the following are
the events that take place
sequentially when the processor
receives an interrupt (from an
external device via INT 32
through INT 255:
 Receiving an interrupt
request (from an external device)
 Generation of interrupt
acknowledge bus cycles.
 Servicing the Interrupt
Service Subroutine
(corresponding to the external
device which has interrupted the
CPU.)
Again the difference between
simultaneous interrupt and
interrupt within an ISS is to be
understood. Occurrence of more
than one interrupt within the
same instruction is called
simultaneous interrupt while if an
interrupt occurs while the ISS is in
progress, it is an interrupt occurring within an ISS.
Internal interrupts (except single step) have priority over simultaneous external requests. For
example, let the current instruction causes a divide-by-zero interrupt when an INTR (a hardware
interrupt) occurs, the former will be serviced. Again, if simultaneous interrupts occur on INTR and
NMI, then NMI will be serviced first.
For simultaneous interrupts occurring, the priority structure will be honored, with the highest
priority interrupt being serviced first. Although it has been commented that software interrupts get
priority over external hardware interrupts, even then if an interrupt on NMI occurs as soon as the
interrupt’s ISS begins, it (i.e., NMI) will be recognized and hence serviced.
List the different interrupt instructions associated with 8086.
Ans. Table lists the different interrupts of 8086 along with a brief description of their functions.
Mnemonic Meaning Format Operation Flags affected
CLI Clear interrupt flag CLI 0→(IF) IF
STI Set interrupt flag STI 1→(IF) IF
INT n Type n software interrupt INT n (Flags)→((SP) – 2)
0→TF, IF.
(CS)→((SP) – 4)
(2 + 4, n)→(CS)
(IP)→((SP)–6)
(4 . n)→(IP)
TF, IF

IRET Interrupt return IRET) ((SP))→(IP)
((SP)+2)→(CS)
((SP)+4)→(Flags)
(SP)+6→(SP)
All
INTO Interrupt on overflow INTO INT 4 steps TF, IF
HLT Halt HLT Wait for an external
interrupt or reset to
occur
None
WAIT Wait WAIT Wait for TEST input to
go active
None
Show the internal interrupts and their priorities.
Ans. The internal interrupts are: Divide-by-0, single step, break point and overflow corresponding
to Type 0, Type 1, Type 3 and Type 4 interrupts respectively. Since a type with lesser number has
higher priority than a type with more number, thus the mentioned internal interrupts can be
arranged in a decreasing priority mode, with highest priority mentioned first: Divide-by-0, single
step, break point, overflow.
What are the characteristics associated with internal interrupts?
Ans. The following are the characteristics associated with internal interrupts:
 The interrupt type code is either contained in the instruction itself or is predefined.
 No INTA bus cycles are generated, as in the case of INTR interrupt input.
 Apart from single step interrupt, no other internal interrupt can be disabled.
 Internal interrupts, except single step have higher priority than external interrupts.
Discuss the two interrupts HLT and WAIT.
Ans. On execution of HLT (halt) instruction by 8086, CPU suspends its instruction execution and
enters into an idle state. It waits for either an external hardware interrupt or a reset input
(interrupt). When any one of these occurs, CPU starts executing again.
When the WAIT instruction is executed by 8086, it internally checks the logic level existing at its
TEST input. If TEST is at logic 1 state, then CPU goes into an idle state. When TEST input assumes a
zero state, execution resumes from the next sequential instruction in the program. TEST input is
normally connected to the BUSY output signal of 8087 NDP.
Explain in detail the external hardware interrupt sequence.
Ans. The external device can request for service via INT 32 through INT 255 by pulling the
corresponding INT n (n = 32 to 255) high. The interrupt request gives rise to generation of interrupt
acknowledge bus cycles and then moving into ISS corresponding to the device which has
interrupted the system. The presently requested interrupt is recognized provided no higher priority
interrupt is pending and IF is already set via software.
Once the interrupt is recognized (since for any INTR to be recognized, the corresponding INT must
stay high till the last clock cycle of the presently executed instruction). 8086 initiates interrupt
acknowledge bus cycles, shown in Fig.
During T1 of the first interrupt bus cycle, ALE is put to low state and remains so till the end of the
cycle. During the whole of this cycle, address/data bus is driven into Z-state. During T2 and T3 of
this first interrupt bus cycle, INTA is put to low state indicating that the request for service has been
granted so that the requesting device can withdraw its high logic which is connected to INTR pin
8086.

LOCK signal is of importance only in maximum mode. This signal goes low during T2 of the first INTA
bus cycle and is maintained in zero state until T2 of the second INTA bus cycle.
8086 is prevented from accepting a HOLD request. The LOCK output, in conjunction with external
logic, is used to lock off other devices from the system bus. This ensures completion of the current
interrupt till its completion.
During the second interrupt bus
cycle, the external circuit puts in
the interrupt code (3210 = 20H
through 25510 = FFH) on the data
bus AD0– AD7 during T3 and T4
and is read by 8086.
Before moving to ISS, CPU saves
the contents of the flag register
along with the current CS and IP
values. Now by reading the
number from the data bus, the
corresponding CS and IP values are placed in them (for instance, if the external device has
interrupted via INT 60, then CS60 and IP60 would be loaded into CS and IP register respectively).
Thus the ISS would be run to its completion because before moving into ISS, IF and single-stepping
have been disabled.
In the last line of ISR, an IRET instruction is there, which on its execution pops the old CS and IP
values from the stack and put them in CS and IP registers. This thus ensures that the main program
starts at the very memory location that was left off because of ISS.
Discuss the following (a) Type 0 interrupt (b) Type 1 interrupt (c) Type 2 interrupt (d) Type 3
interrupt and (e) Type 4 interrupt.
Ans. (a) Type 0 interrupt (or Divide-by-zero interrupt)
If the quotient resulting from a DIV (divide) instruction or an IDIV (integer divide) instruction is too
large such that it cannot be accommodated in the destination register, a divide error occurs. Then
8086 perform a Type 0 interrupt. This then passes the control to a service subroutine at addresses
corresponding to IP0 and CS0 at 0000 H and 0002 H respectively in the pointer table.
(b) Type 1 interrupt (Single Step interrupt)
The single step interrupt will be enabled only if the trap flag (TF) bit is set (= 1). The TF bit can be
set/reset by software. Single step control is used for debugging in assembly language. In this mode
the processor executes one instruction and then stops. The contents of various registers and
memory locations can be examined. If the results are found to be ok, then a command can be
inserted for execution of the next instruction. Trap flag cannot be set directly. This is done by
pushing the flags on the stack, changes are made and then they are popped.
(c) Type 2 interrupt (non-maskable NMI interrupt)
Type 2 interrupt is the non-maskable NMI interrupt and is used for some emergency situations like
power failure. When power fails, an external circuit detects this and sends an interrupt signal via
NMI pin of 8086. The DC supply remains on for at least 50 ms via capacitor banks so that the
program and data remaining in RAM locations can be saved, which were being executed at the time
of power failure.
(d)Type 3 interrupt (break point interrupt)
Type 3 interrupt is a break point interrupt. The program runs up to the break point when the
interrupt occurs. This is achieved by inserting INT 3 at the point the break is desired. The ISS
corresponding to Type 3 interrupt saves the register contents in the stack and can also be displayed

on CRT and the control is returned to the user. This is used as a software debugging tool, like single
stepping method.
(e) Type 4 interrupt (overflow interrupt)
The software instruction INTO (interrupt on overflow) is inserted in a program immediately after an
arithmetic operation is performed. Insertion of INTO implements a Type 4 interrupt. When the
signed result of an arithmetic operation on two signed numbers is too large to be stored in the
destination register or else in a memory location, an overflow occurs and the OF (overflow flag) is
set. This initiates INT4 instruction and the program control moves over to the starting address of
the ISS, which corresponds to IP4 and CS4. These two are stored at address locations 0010 H and
0012 H respectively.
Draw the schemes of (a) Min and (b) Max mode 8086 system external hardware interrupt
interface and explain.
Ans. (a) The scheme of interconnections of Min-mode
8086 system external hardware interrupt interface is
shown below
The interconnecting signals to be considered for 8086
are ALE, INTR, INTA and the data bus AD0 – AD15. The
external device requests the service of 8086 via the
INTR line. INTR is level triggered and must stay at logic
1 until recognized by the processor. Two interrupt
acknowledge bus cycles are generated in response to
INTR. At the end of the first bus cycle, the INTR should
be removed so that it does not interrupt the
8086 a second time and the ISS can run
without interruption. In this second bus
cycle CPU puts the type number on the data
bus of the active interrupt.
(b) The scheme of interconnections of Max-
mode 8086 system external hardware
interrupt interface is shown below.
In this mode, the bus controller IC 8288
generates the INTA and ALE signals. INTA is
generated when at the input of 8288, a
status 000 H is applied via the status lines
S2, S1, S0. The LOCK signal in the figure is
the bus priority lock signal and is the input to bus arbiter circuit. This circuit ensures that no other
device can take control of the system buses until the presently run interrupt acknowledge cycle is
completed.
PROGRAMMABLE INTERRUPT CONTROLLER 82S9A
The processor 8086 has only two interrupt inputs namely NMI and INTR. One need an interfacing
device that accepts interrupts from many IRQs and conveys their values to the processor. The
microprocessor then gets this type and derives the interrupt vector address from that. Consider an
application, where a number of I/O devices connected with a CPU desire to transfer data using
interrupt driven data transfer mode. In these types of applications, more number of interrupt pins
are required than available in a typical microprocessor. Moreover, in these multiple interrupt

systems, the processor will have to take care of the priorities for the interrupts, simultaneously
occurring at the interrupt request pins.
To overcome all these difficulties, we require a programmable interrupt controller which is able to
handle a number of interrupts at a time. This controller takes care of a number of simultaneously
appearing interrupt requests along with their types and priorities. This relieves the processor from
all these tasks. The programmable interrupt controller 8259A from Intel is one such device.
Architecture and Signal Descriptions of 8259A
The architectural block diagram of 8259A is shown in Fig.
Interrupt Request Register
(IRR) The interrupts at IRQ
input lines are handled by
Interrupt Request Register
internally. IRR stores all the
interrupt requests in it in
order to serve them one by
one on the Priority basis.
In Service Register (ISR) This
stores all the interrupt
requests those are being
served, i.e. ISR keeps a track
of the requests being served.
Priority Resolver This unit
determines the priorities of
the interrupt requests
appearing simultaneously. The highest priority is selected and stored into the corresponding bit of
ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in
fixed priority mode. The priorities however may be altered by programming the 8259A in rotating
priority mode.
Interrupt Mask Register (IMR) This register stores the bits required to mask the interrupt inputs.
IMR operates on IRR at the direction of the Priority Resolver.
Interrupt Control Logic This block manages the interrupt and the interrupt acknowledge signals to
be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt
acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data
bus.
Data Bus Buffer This tri-state bidirectional buffer interfaces internal 8259A bus to the
microprocessor system data bus. Control words, status and vector information pass through data
buffer during read or write operations.
Read Write Control Logic This circuit accepts and decodes commands from the CPU. This block also
allows the status of the 8259A to be transferred on to the data bus.
Cascade Buffer/Comparator This block stores and compares the IDs of all the 8259As used in the
system. The three I/O pins CAS0-2 are outputs when the 8259 A is used as a master. The same-pins
act as inputs when the 8259A is in the slave mode. The 8259A in the master mode, sends the ID of

the interrupting slave device on these lines. The slave thus selected, will send its pre-programmed
vector address on the data bus during the next INTA pulse.
Figure shows the pin configuration of 8259A, followed by their functional description of each of the
signals in brief.
CS This is an active-low chip select signal for enabling RD and
WR operations of 8259A. INTA function is independent of CS.
WR This pin is an active-low write enable input to 8259A. This
enables it to accept commands from CPU.
RD This is an active-low read enable input to 8259A. A low on
this line enables 8259A to release status onto the data bus of
CPU.
D0-D7 These pins form a bidirectional data bus that carries 8-
bit data either to control word or from status word registers.
This also carries interrupt vector information.
CAS0-CAS2 A single 8259A provides eight vectored interrupts. If
more interrupts are required, the 8259A is used in the cascade
mode in which a master 8259A along with eight slaves 8259A
can provide up to 64 vectored interrupt lines. These three lines act as select lines for addressing the
slave 8259A.
PS/EN This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as a
buffer enable to control buffer transceivers. If this is not used in buffered mode then the pin is used
as input to designate whether the chip is used as a master or slave.
INT This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the
CPU and is connected to the INTR input of CPU.
IR0-IR7(interrupt requests) These pins act as inputs to accept interrupt requests to the CPU. In the I
edge triggered mode, an interrupt service is requested by raising an IR pin from a low to a high
state. It is held high until it is acknowledged, and just by latching it to high level, if used in the level
triggered mode.
INTA(Interrupt Acknowledge) This pin is an input used to strobe-in 8259A interrupt vector data on
to the data bus. In conjunction with CS, WR and RD pins, this selects the different operations like,
writing command words, reading status word, etc.
The device 8259A can be interfaced with any CPU using either polling or interrupt. In polling, the
CPU keeps on checking each peripheral device in sequence to ascertain if it requires any service
from the CPU. If any such service request is noticed, the CPU serves the request and then goes on
to the next device in sequence. After all the peripheral devices are scanned as above the CPU again
starts from the first device. This type of system operation results in the reduction of processing
speed because most of the CPU time is consumed in polling the peripheral devices.
In the interrupt driven method, the CPU performs the main processing task till it is interrupted by a
service requesting peripheral device. The net processing speed of these type of systems is high
because the CPU serves the peripheral only if it receives the interrupt request. If more than one
interrupt requests are received at a time, all the requesting peripherals are served one by one on

priority basis. This method of interfacing may require additional hardware if number of peripherals
to be interfaced is more than the interrupt pins available with the CPU.
Interrupt Sequence in an 8086 System
The interrupt sequence in an 8086-8259A system is described as follows:
1. One or more IR lines are raised high that set corresponding IRR bits.
2. 8259A resolves priority and sends an INT signal to CPU.
3. The CPU acknowledges with INTA pulse.
4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the.
corresponding IRR bit is reset. The 8259A does not drive data bus during this period.
5. The 8086 will initiate a second INTA pulse. During this period 8259A releases an 8-bit pointer on
to data bus from where it is read by the CPU.
6. This completes the interrupt cycle. The ISR bit
is reset at the end of the second INTA pulse if
automatic end of interrupt (AEOI) mode is
programmed. Otherwise ISR bit remains set until
an appropriate EOI command is issued at the end
of interrupt subroutine.
Command Words of 8259A
The command words of 8259A are classified in
two groups, viz. Initialization Command Words
(ICWs) and Operation Command Words (OCWs).
Initialization Command Words Before it starts
functioning, the 8259A must be initialized by
writing two to four command words into the
respective command word registers. These are
called as Initialization Command Words (ICWs). If
A0 = 0 and D4 = 1, the control word is recognized
as ICW1. It contains the control bits for
edge/level triggered mode, single/cascade mode,
call address interval and whether ICW4 is
required or not, etc. If A0 = 1, the control word is
recognized as ICW2. The ICW2 stores details
regarding interrupt vector addresses. The initialization sequence of 8259A is described in from of a
flow chart in Fig. The bit functions of the ICW1 and ICW2 are self explanatory as shown in Fig.

Once ICW1 is loaded, the following initialization procedure is carried out internally.
(a) The edge sense circuit is reset, i.e. by default 8259A interrupts are edge sensitive
(b) IMR is cleared
(c) IR7 input is assigned the lowest priority
(d) Slave mode address is set to 7
(e) Special mask mode is cleared and the status read is set to IRR
(f) If IC4 = 0, all the functions of ICW4 are set to zero. Master/slave bit in ICW4 is used in the
buffered mode only.
In 8086 based system, five most significant bits of the interrupt type byte are inserted in place of
T7 - T3 respectively and the remaining three bits (A8, A9 and A10) are inserted internally as 000 (as
if they are pointing to IR0). Other seven interrupt levels vector addresses are internally generated
automatically by 8259 using IR0 vector. Address interval is always four in an 8086 based system.
ICW1 and ICW2 are compulsory
command words in initialization
sequence of 8259A as is evident
from Fig. while ICW3 and ICW4
are optional. The ICW3 is read
only when there are more than
one 8259As in the system, i.e.
cascading is used (SNGL = 0). The
SNGL bit in ICW1 indicates
whether the 8259A is in the
cascade mode or not. The ICW3
loads an 8-bit slave register. Its
detailed functions are as follows:
In the master mode (i.e. SP = 1 or
in buffer mode M/S = 1 in ICW4), the 8-bit slave register will be set bit-wise to T for each slave in
the system, as shown in Fig. 6.16. The requesting slave will then release the second byte of a CALL
sequence.

In slave mode (i.e. SP = 0 or if BUF = 1 and M/S = 0 in ICW 4) bits D2 to Do identify the slave, i.e. 000
to 111 for slave1 to slave8. The slave compares the cascade inputs with these bits and if they are
equal, the second byte of the CALL sequence is released by it on the data bus.
ICW4 The use of this command word depends on the IC4 bit of ICW1 If IC4 = 1, ICW4 is used,
otherwise it is neglected. The bit functions of ICW4 are described as follows:
SFNM Special fully nested mode is selected, if SFNM = 1.
BUF If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts as enable output
and the master/slave is determined using the M/S bit of ICW4.
M/S If M/S = 1, 8259A is a master. If M/S = 0, 8259A is a slave. If BUF = 0, M/S is to be neglected
AEOI If AEOI = 1, the automatic end of interrupt mode is selected.
mPM If the mPM bit is 0, the Mcs-85 system operation is selected and if mPM =1, 8086 operation is
selected.
Operational Command Words Once 8259A is initialized using the previously discussed command
words for initialization, it is ready for its normal function, i.e. for accepting the interrupts but 8259
has its own ways of handling the received interrupts called as modes of operation. These modes of
operations can be selected by programming, i.e. writing three internal registers called as
operational command word registers. The data written into them (bit pattern) is called as operation
command words. In the three operation command words OCW1, OCW2, and OCW3 every bit
corresponds to some operational feature of the mode selected, except for a few bits those are
either ' 1' or '0'. The three operation command words are shown in Fig. with the bit selection
details.
OCW1 is used to mask the unwanted interrupt requests. If the mask bit is T, the corresponding
interrupt request is masked, and if it is '0', the request is enabled.
In OCW2 the three bits, viz. R,SL and EOI control the end of interrupt, the rotate mode and their
combinations as shown in Fig. The three bits L2, L1 and L0 in OCW2 determine the interrupt level to
be selected for operation , if the SL bit is active, i.e. 1. The details of OCW2 are shown in Fig.
In operation command word 3 (OCW3), if the ESMM bit, i.e. Enable special mask mode bit is set to
1, the SMM bit is enabled to select or mask the Special Mask Mode. When ESMM bit is '0', the SMM
bit is neglected. If the SMM bit, i.e. Special Mask Mode bit is '1', the 8259A will enter special mask
mode provided ESMM = 1.
If ESMM = 1 and SMM = 0, the 8259A will return to the normal mask mode. The details of bits of
0CW3 are given .in Fig. along with their bit definitions.
Operating Modes of 8259

The different modes of operation of 8259A can be programmed by setting or resting the
appropriate bits of the ICWs or OCWs as discussed previously. The different modes of operation of
8259A are as follows:
Fully Nested Mode: This is the default mode of operation of 8259A. IR0 has the highest priority and
IR7 has the lowest one. When interrupt requests are noticed, the highest priority request amongst
them is determined and the vector is placed on the data bus. The corresponding bit of ISR is set and
remains set till the microprocessor issues an EOI command just before returning from the service
routine or the AEOI bit is
set. If the ISR (In Service)
bit is set, all the same or
lower priority interrupts
are inhibited but higher
levels will generate an
interrupt that will be
acknowledged only if the
microprocessor's Interrupt
enable Flag (IF) is set. The
priorities can afterwards
be changed by
programming the rotating
priority modes.
End of Interrupt (EOI) The
ISR bit can be reset either
with AEOI bit of ICW1 or
by EOI command issued
before returning from the
interrupt service routine.
There are two types of EOI
commands specific and
non-specific. When 8259A
is operated in the modes
that preserve fully nested
structure, it can determine
which ISR bit is to be reset
on EOI. When non-specific
EOI command is issued to
8259A, it will automatically
reset the highest ISR bit
out of those already set.
When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to
determine the last level acknowledged. In this case a specific EOI command is issued to reset a
particular ISR bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a
non-specific EOI of 8259A, if it is in special mask mode.
Automatic Rotation This is used in the applications where all the interrupting devices are of equal
priority. In. this mode, an Interrupt Request (IR) level receives lowest priority after it is served while
the next device to be served gets the highest priority in sequence. Once all the devices are served
like this, the first device again receives highest priority.

Automatic EOI Mode Till AEOI = 1 in ICW4, the 8259A operates in AEOI mode. In this mode, the
8259A performs a non-specific EOI operation at the trailing edge of the last INTA pulse
automatically. This mode should be used only when a nested multilevel interrupt structure is not
required with a single 8259A.
Specific Rotation In this mode a bottom priority level can be selected, using L2, L1 and L0 in OCW2
and R = 1, SL = 1, EOI = 0. The selected bottom priority fixes other priorities. If IR5 is selected as a
bottom priority, then IR5 will have least priority and IR4 will have a next higher priority. Thus IR6
will have the highest priority. These priorities can be changed during an EOI command by
programming the rotate on specific EOI command in OCW2.
Special Mask Mode In the special mask mode, when a mask bit is set in 0CW1 it inhibits further
interrupts at that level and enables interrupt from other levels, which are not masked.
Edge and Level Triggered Mode This mode decides whether the interrupt should be edge triggered
or level triggered. If bit LTIM of ICW1 = 0, they are edge triggered, otherwise the interrupts are level
triggered.
Reading 8259 Status The status of the internal registers of 8259A can be read using this mode. The
OCW3 is used to read IRR and ISR while OCW1 is used to read IMR. Reading is possible only in no
polled mode.
Poll Command In the polled mode of operation, the INT output of 8259A is neglected, though it
functions normally, by not connecting INT output or by masking INT input of the microprocessor.
The mode is entered by setting P = 1 in OCW3. The 8259A is polled by using software execution by
microprocessor instead of the requests on INT input. The 8259A treats the next RD pulse, to the
8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there is a request. The priority
level is read and a data word is placed on to data bus, after RD is activated. The data word is shown
in fig.
A poll command may give you more than 64 priority levels. Note that this has nothing to do with
the 8086 interrupt structure and the interrupt priorities.
Special Fully Nested Mode: This mode is used in more complicated systems, where cascading is
used and the priority has to be programmed in the master using ICW4. This is somewhat similar to
the normal nested mode. This mode, when an interrupt request from a certain slave is in service,
this slave can further send requests to the master, if the requesting device connected to the slave
has higher priority than the one being currently served. In this mode, the master interrupts the CPU
only when the interrupting device has a higher or the same priority than the one currently being
served. In normal mode, other requests than the one being served are masked out.
When entering the interrupt service routine the software has to check whether this is the only
request from the slave. This is done by sending a non-specific EOI command to the slave and then
reading its ISR and checking for zero. If its zero, a non-specific EOI can be sent to the master,
otherwise no EOI should be sent. This mode is important, since in the absence of this mode, the
slave would interrupt the master only once and hence the priorities of the slave inputs would have
been disturbed.
Buffered Mode When the 8259A is used in the systems in which bus driving buffers are used on
data buses (e.g. cascade systems), the problem of enabling the buffers arises. The 8259A sends a
buffer enable signal on SP/EN pin, whenever data is placed on the bus.

Cascade Mode The 8259A can be connected in a system containing one master and eight slaves
(maximum) to handle upto 64 priority levels. The master controls the slaves using CAS0-CAS2 which
act as chip select inputs (encoded) for slaves. In this mode, the slave INT outputs are connected
with master IR inputs. When a slave request line is activated and acknowledged, the master will
enable the slave to release the vector address during the second pulse of INTA sequence. The
cascade lines are normally low and contain slave address codes from the trailing edge of the first
INTA pulse to the trailing edge of the second INTA pulse. Each 8259A in the system must be
separately initialized and programmed to work in different modes. The EOI command must be
issued twice, one for master and another for slave. A separate address decoder is used to activate
the chip select line of each 8259A. Fig. shows the details of the circuit connections of 8259As in
cascade scheme.

8086 Introduction

More Related Content

What's hot

Similar to 8086 Introduction

Recently uploaded

8086 Introduction