The document discusses the 8051 microcontroller. It was introduced by Intel in 1981 as an 8-bit microcontroller with features like 128 bytes of RAM, 4K bytes of ROM, timers, ports, and peripherals integrated onto a single chip. This led to variants like the 8052 with more RAM and an extra timer. The 8031 has no on-chip ROM. Microcontrollers are used in embedded systems for tasks like displaying microwave information or receiving remote signals. They have lower costs and power usage than microprocessors. The 8051 architecture includes registers like the accumulator, R registers, B register, data pointer, and program counter to interface with memory, ports and peripherals via a system bus.

1. UNIT-4
MICROCONTROLLER-8051

2. INTRODUCTION TO MICROCONTROLLER-8051:
In 1981, Intel introduced an 8-bit microcontroller called the 8051. It was referred as
system on a chip because it had 128 bytes of RAM, 4K byte of on-chip ROM, two
timers, one serial port, and 4 ports (8-bit wide), all on a single chip. ... This has led to
several versions with different speeds and amounts of on-chip RAM.
8051 Flavors / Members:
8052 microcontroller − 8052 has all the standard features of the 8051
microcontroller as well as an extra 128 bytes of RAM and an extra timer. It also
has 8K bytes of on-chip program ROM instead of 4K bytes.
8031 microcontroller − It is another member of the 8051 family. This chip is
often referred to as a ROM-less 8051, since it has 0K byte of on-chip ROM. You
must add external ROM to it in order to use it, which contains the program to be
fetched and executed. This program can be as large as 64K bytes. But in the
process of adding external ROM to the 8031, it lost 2 ports out of 4 ports. To
solve this problem, we can add an external I/O to the 8031

3. A microcontroller is a small and low-cost microcomputer, which is
designed to perform the specific tasks of embedded systems like
displaying microwave’s information, receiving remote signals, etc.
The general microcontroller consists of the processor, the memory (RAM,
ROM, EPROM), Serial ports, peripherals (timers, counters), etc.
Difference between Microprocessor and Microcontroller
The following table highlights the differences between a microprocessor
and a microcontroller −

4. Microcontroller Microprocessor
Microcontrollers are used to
execute a single task within an
application.
Microprocessors are used for big
applications.
Its designing and hardware cost is
low.
Its designing and hardware cost is high.
Easy to replace. Not so easy to replace.
It is built with CMOS technology,
which requires less power to
operate.
Its power consumption is high because
it has to control the entire system.
It consists of CPU, RAM, ROM, I/O
ports.
It doesn’t consist of RAM, ROM, I/O
ports. It uses its pins to interface to
peripheral devices.

5. Types of Microcontrollers
Microcontrollers are divided into various categories based on memory,
architecture, bits and instruction sets. Following is the list of their types −
Bit
Based on bit configuration, the microcontroller is further divided into
three categories.
•8-bit microcontroller − This type of microcontroller is used to execute
arithmetic and logical operations like addition, subtraction, multiplication
division, etc. For example, Intel 8031 and 8051 are 8 bits
microcontroller.
•16-bit microcontroller − This type of microcontroller is used to perform
arithmetic and logical operations where higher accuracy and
performance is required. For example, Intel 8096 is a 16-bit
microcontroller.

6. •32-bit microcontroller − This type of microcontroller is generally used
in automatically controlled appliances like automatic operational
machines, medical appliances, etc.
Memory
Based on the memory configuration, the microcontroller is further
divided into two categories.
•External memory microcontroller − This type of microcontroller is
designed in such a way that they do not have a program memory on the
chip. Hence, it is named as external memory microcontroller. For
example: Intel 8031 microcontroller.
•Embedded memory microcontroller − This type of microcontroller is
designed in such a way that the microcontroller has all programs and
data memory, counters and timers, interrupts, I/O ports are embedded
on the chip. For example: Intel 8051 microcontroller.

7. Instruction Set:
Based on the instruction set configuration, the microcontroller is further
divided into two categories.
•CISC − CISC stands for complex instruction set computer. It allows the
user to insert a single instruction as an alternative to many simple
instructions.
•RISC − RISC stands for Reduced Instruction Set Computers. It reduces
the operational time by shortening the clock cycle per instruction.
Applications of Microcontrollers
Microcontrollers are widely used in various different devices such as −
•Light sensing and controlling devices like LED.
•Temperature sensing and controlling devices like microwave oven,
chimneys.
•Fire detection and safety devices like Fire alarm.
•Measuring devices like Volt Meter.

8. Microcontrollers - 8051 Architecture:
8051 microcontroller is designed by Intel in 1981. It is an 8-bit
microcontroller. It is built with 40 pins DIP (dual inline package), 4kb of
ROM storage and 128 bytes of RAM storage, 2 16-bit timers. It consists
of four parallel 8-bit ports, which are programmable as well as
addressable as per the requirement. An on-chip crystal oscillator is
integrated in the microcontroller having crystal frequency of 12 MHz.
Let us now discuss the architecture of 8051 Microcontroller.
In the following diagram, the system bus connects all the support devices
to the CPU. The system bus consists of an 8-bit data bus, a 16-bit
address bus and bus control signals. All other devices like program
memory, ports, data memory, serial interface, interrupt control, timers,
and the CPU are all interfaced together through the system bus.

10. Registers of 8051:
The most widely used registers of the 8051 are A (accumulator), B,
R0-R7, DPTR (data pointer), and PC (program counter). All these
registers are of 8-bits, except DPTR and PC.
Storage Registers in 8051
We will discuss the following types of storage registers here −
Accumulator
R register
B register
Data Pointer (DPTR)
Program Counter (PC)
Stack Pointer (SP)

11. Accumulator
The accumulator, register A, is used for all arithmetic and logic operations. If the
accumulator is not present, then every result of each calculation (addition,
multiplication, shift, etc.) is to be stored into the main memory. Access to main
memory is slower than access to a register like the accumulator because the
technology used for the large main memory is slower (but cheaper) than that
used for a register.
The "R" Registers
The "R" registers are a set of eight registers, namely, R0, R1 to R7. These
registers function as auxiliary or temporary storage registers in many operations.
Consider an example of the sum of 10 and 20. Store a variable 10 in an
accumulator and another variable 20 in, say, register R4. To process the addition
operation, execute the following command −
ADD A,R4

12. After executing this instruction, the accumulator will contain the value 30. Thus
"R" registers are very important auxiliary or helper registers. The Accumulator
alone would not be very useful if it were not for these "R" registers. The "R"
registers are meant for temporarily storage of values.
Let us take another example. We will add the values in R1 and R2 together and
then subtract the values of R3 and R4 from the result.
MOV A,R3 ;Move the value of R3 into the accumulator
ADD A,R4 ;Add the value of R4
MOV R5,A ;Store the resulting value temporarily in R5
MOV A,R1 ;Move the value of R1 into the accumulator
ADD A,R2 ;Add the value of R2
SUBB A,R5 ;Subtract the value of R5 (which now contains R3 + R4)
As you can see, we used R5 to temporarily hold the sum of R3 and R4. Of
course, this is not the most efficient way to calculate (R1 + R2) – (R3 + R4), but it
does illustrate the use of the "R" registers as a way to store values temporarily.

13. The "B" Register
The "B" register is very similar to the Accumulator in the sense that it may hold
an 8-bit (1-byte) value. The "B" register is used only by two 8051 instructions:
MUL AB and DIV AB. To quickly and easily multiply or divide A by another
number, you may store the other number in "B" and make use of these two
instructions. Apart from using MUL and DIV instructions, the "B" register is
often used as yet another temporary storage register, much like a ninth R
register.

14. The Data Pointer
The Data Pointer (DPTR) is the 8051’s only user-accessible 16-bit (2-byte) register. The
Accumulator, R0–R7 registers and B register are 1-byte value registers. DPTR is meant for
pointing to data. It is used by the 8051 to access external memory using the address indicated
by DPTR. DPTR is the only 16-bit register available and is often used to store 2-byte values.
The Program Counter
The Program Counter (PC) is a 2-byte address which tells the 8051 where the next instruction
to execute can be found in the memory. PC starts at 0000h when the 8051 initializes and is
incremented every time after an instruction is executed. PC is not always incremented by 1.
Some instructions may require 2 or 3 bytes; in such cases, the PC will be incremented by 2 or
3.
Branch, jump, and interrupt operations load the Program Counter with an address other
than the next sequential location. Activating a power-on reset will cause all values in the
register to be lost. It means the value of the PC is 0 upon reset, forcing the CPU to fetch the
first opcode from the ROM location 0000. It means we must place the first byte of upcode in
ROM location 0000 because that is where the CPU expects to find the first instruction.

15. The Stack Pointer (SP)
The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The
Stack Pointer tells the location from where the next value is to be removed from the stack.
When a value is pushed onto the stack, the value of SP is incremented and then the value is
stored at the resulting memory location. When a value is popped off the stack, the value is
returned from the memory location indicated by SP, and then the value of SP is decremented.
This order of operation is important. SP will be initialized to 07h when the 8051 is initialized. If
a value is pushed onto the stack at the same time, the value will be stored in the internal RAM
address 08h because the 8051 will first increment the value of SP (from 07h to 08h) and then
will store the pushed value at that memory address (08h). SP is modified directly by the 8051
by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI.
ROM Space in 8051
Some family members of 8051 have only 4K bytes of on-chip ROM (e.g. 8751, AT8951); some
have 8K ROM like AT89C52, and there are some family members with 32K bytes and 64K bytes
of on-chip ROM such as Dallas Semiconductor. The point to remember is that no member of
the 8051 family can access more than 64K bytes of opcode since the program counter in 8051
is a 16-bit register (0000 to FFFF address).

16. The first location of the program ROM inside the 8051 has the address of 0000H, whereas the
last location can be different depending on the size of the ROM on the chip. Among the 8051
family members, AT8951 has $k bytes of on-chip ROM having a memory address of 0000 (first
location) to 0FFFH (last location).
8051 Flag Bits and PSW Register
The program status word (PSW) register is an 8-bit register, also known as flag register. It is of
8-bit wide but only 6-bit of it is used. The two unused bits are user-defined flags. Four of the
flags are called conditional flags, which means that they indicate a condition which results
after an instruction is executed. These four are CY (Carry), AC (auxiliary carry), P (parity), and
OV (overflow). The bits RS0 and RS1 are used to change the bank registers. The following figure
shows the program status word register.

17. The PSW Register contains that status bits that reflect the current status of the CPU.
CY CA F0 RS1 RS0 OV - P
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag
F0 PSW.5 Flag 0 available to user for general purpose.
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow Flag
- PSW.1 User definable FLAG
P PSW.0 Parity FLAG. Set/ cleared by hardware during instruction cycle to indicate
even/odd number of 1 bit in accumulator.
We can select the corresponding Register Bank bit using RS0 and RS1 bits.
RS1 RS2 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

18. CY, the carry flag − This carry flag is set (1) whenever there is a carry out from
the D7 bit. It is affected after an 8-bit addition or subtraction operation. It can
also be reset to 1 or 0 directly by an instruction such as "SETB C" and "CLR C"
where "SETB" stands for set bit carry and "CLR" stands for clear carry.
AC, auxiliary carry flag − If there is a carry from D3 and D4 during an ADD or
SUB operation, the AC bit is set; otherwise, it is cleared. It is used for the
instruction to perform binary coded decimal arithmetic.
P, the parity flag − The parity flag represents the number of 1's in the
accumulator register only. If the A register contains odd number of 1's, then P
= 1; and for even number of 1's, P = 0.
OV, the overflow flag − This flag is set whenever the result of a signed number
operation is too large causing the high-order bit to overflow into the sign bit. It
is used only to detect errors in signed arithmetic operations.

19. Registers Bank/Stack
RAM Memory Space Allocation in 8051
The 128 bytes of RAM inside the 8051 are assigned the address 00 to 7FH. They can be
accessed directly as memory locations and are divided into three different groups as follows −
32 bytes from 00H to 1FH locations are set aside for register banks and the stack.
16 bytes from 20H to 2FH locations are set aside for bit-addressable read/write memory.
80 bytes from 30H to 7FH locations are used for read and write storage; it is called as scratch
pad. These 80 locations RAM are widely used for the purpose of storing data and parameters
by 8051 programmers.

20. Register Banks in 8051
A total of 32 bytes of RAM are set aside for the register banks and the stack. These 32 bytes
are divided into four register banks in which each bank has 8 registers, R0–R7. RAM locations
from 0 to 7 are set aside for bank 0 of R0–R7 where R0 is RAM location 0, R1 is RAM location
1, R2 is location 2, and so on, until the memory location 7, which belongs to R7 of bank 0.
The second bank of registers R0–R7 starts at RAM location 08 and goes to locations OFH. The
third bank of R0–R7 starts at memory location 10H and goes to location to 17H. Finally, RAM
locations 18H to 1FH are set aside for the fourth bank of R0–R7.
Default Register Bank
If RAM locations 00–1F are set aside for the four registers banks, which register bank of R0–R7
do we have access to when the 8051 is powered up? The answer is register bank 0; that is,
RAM locations from 0 to 7 are accessed with the names R0 to R7 when programming the
8051. Because it is much easier to refer these RAM locations by names such as R0 to R7,
rather than by their memory locations.
RS1 RS2 Bank Selected
0 0 Bank0
0 1 Bank1
1 0 Bank2
1 1 Bank3

21. Stack in the 8051
As the stack is a section of a RAM, there are registers inside the CPU to point to it. The register
used to access the stack is known as the stack pointer register. The stack pointer in the 8051 is
8-bits wide, and it can take a value of 00 to FFH. When the 8051 is initialized, the SP register
contains the value 07H. This means that the RAM location 08 is the first location used for the
stack. The storing operation of a CPU register in the stack is known as a PUSH, and getting the
contents from the stack back into a CPU register is called a POP.
"PUSH 1" pushes register R1 onto the stack.
Popping the contents of the stack back into a given register
8051 DATA TYPES AND DIRECTIVES:
Microcontroller 8051 has only one 8-bits data type and the size of each register is also 8 bits.
The job of the programmer is to break down data larger than 8 bits [00 to FFH, or 0 to 255 in
decimal] to be processed by the CPU. The data type used by the 8051 can be positive or
negative.

22. DB [Define Byte]:
The DB directive is used to define the 8-bit data and the numbers can be in decimal,binary,
hex or ASCII formats. For decimal, the "D" after the decimal number is optional, but using "B"
[binary] and "H" [hexadecimal] is required. The assembler will convert the numbers in hex. To
indicate ASCII, simply put it in quotation marks 'like this'. The assembler will assign the ASCII
code for the numbers or characters automatically. The DB directive is the only directive that
can be used to define ASCII strings larger than two characters. It should be used for all ASCII
data definitions.
Either single or double quotes can be used around ASCII strings. Can be useful for strings,
which contain a single quote such as "O'Really". DB is also used to allocate memory in byte-
sized chunks.
Assembler Directives:
The following Assembler directives are widely used in 8051 Assembly language programming.
ORG [Origin]:
The ORG directive is used to indicate the beginning of the address. The number that comes
after ORG can be either in HEX or in decimal. If the number is not followed by 'H', it is decimal
and the assembler will convert it into hex. Some assemblers use ".ORG" [notice the dot]
instead of "ORG" for the origin directive. For tha you need to check your assembler.

23. EQU [Equate]:
EQU is used to define a constant without occupying a memory location. The EQU directive does
not set aside storage for a data item but associates a constant value with a data label so that
when the label appears in the program, its constant value will be substituted for the label. Here
uses EQU for the counter constant ans then the constant is used to load the R4 register.
After executing the instruction "MOV R4,#COUNT", the register R4 will be loaded with the
value 22 [# sign indicates it is a value, notice it].
What is the advantage of using EQU?
The answer is that, lets say in a program there is a constant value [a fixed value] used in many
different places in the program, and the programmer wants to change its value through out
the entire program. By the use of EQU, a programmer can change all valves at once and the
assembler will change all of it occurrences, rather than search the entire program and to
change the value one by one to fine every occurrence, just change the constant value
followed by EQU results changing the all occurrences at once.
END Directive:
END directive pseudocode is very important. END indicates to the assemblere the end of the source [asm ] file.
The END directive is the last line of an 8051 program. In assembly language programming anything after the
END directive is ignored by the assembler. Some assembler uses ".END" [notice the dot] instead of "END"

24. The pin diagram of 8051 microcontroller looks as follows −

25. •Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve
any other functions. It is internally pulled up, bi-directional I/O port.
•Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its
initial values.
•Pins 10 to 17 − These pins are known as Port 3. This port serves some
functions like interrupts, timer input, control signals, serial communication
signals RxD and TxD, etc.
•Pins 18 & 19 − These pins are used for interfacing an external crystal to
get the system clock.
•Pin 20 − This pin provides the power supply to the circuit.
•Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port.
Higher order address bus signals are also multiplexed using this port.
•Pin 29 − This is PSEN pin which stands for Program Store Enable. It is
used to read a signal from the external program memory.

26. •Pin 30 − This is EA pin which stands for External
Access input. It is used to enable/disable the external
memory interfacing.
•Pin 31 − This is ALE pin which stands for Address Latch
Enable. It is used to demultiplex the address-data signal
of port.
•Pins 32 to 39 − These pins are known as Port 0. It
serves as I/O port. Lower order address and data bus
signals are multiplexed using this port.
•Pin 40 − This pin is used to provide power supply to the
circuit.

27. 8051 microcontrollers have 4 I/O ports each of 8-bit, which can be
configured as input or output. Hence, total 32 input/output pins allow the
microcontroller to be connected with the peripheral devices.
•Pin configuration, i.e. the pin can be configured as 1 for input and 0 for
output as per the logic state.
• Input/Output (I/O) pin − All the circuits within the microcontroller
must be connected to one of its pins except P0 port because it does
not have pull-up resistors built-in.
• Input pin − Logic 1 is applied to a bit of the P register. The output
FE transistor is turned off and the other pin remains connected to
the power supply voltage over a pull-up resistor of high resistance.
•Port 0 − The P0 (zero) port is characterized by two functions −
• When the external memory is used then the lower address byte
(addresses A0A7) is applied on it, else all bits of this port are
configured as input/output.

28. • When P0 port is configured as an output then other ports consisting
of pins with built-in pull-up resistor connected by its end to 5V power
supply, the pins of this port have this resistor left out.
Input Configuration
If any pin of this port is configured as an input, then it acts as if it “floats”,
i.e. the input has unlimited input resistance and in-determined potential.
Output Configuration
When the pin is configured as an output, then it acts as an “open drain”.
By applying logic 0 to a port bit, the appropriate pin will be connected to
ground (0V), and applying logic 1, the external output will keep on
“floating”.
In order to apply logic 1 (5V) on this output pin, it is necessary to build an
external pullup resistor.
Port 1

29. P1 is a true I/O port as it doesn’t have any alternative functions as in P0,
but this port can be configured as general I/O only. It has a built-in pull-up
resistor and is completely compatible with TTL circuits.
Port 2
P2 is similar to P0 when the external memory is used. Pins of this port
occupy addresses intended for the external memory chip. This port can
be used for higher address byte with addresses A8-A15. When no
memory is added then this port can be used as a general input/output
port similar to Port 1.
Port 3
In this port, functions are similar to other ports except that the logic 1
must be applied to appropriate bit of the P3 register.
Pins Current Limitations
•When pins are configured as an output (i.e. logic 0), then the single port
pins can receive a current of 10mA.

30. •When these pins are configured as inputs (i.e. logic 1), then built-in pull-
up resistors provide very weak current, but can activate up to 4 TTL
inputs of LS series.
•If all 8 bits of a port are active, then the total current must be limited to
15mA (port P0: 26mA).
•If all ports (32 bits) are active, then the total maximum current must be
limited to 71mA.
Interrupts are the events that temporarily suspend the main program, pass the
control to the external sources and execute their task. It then passes the
control to the main program where it had left off.
8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can
be enabled or disabled by setting bits of the IE register and the whole interrupt
system can be disabled by clearing the EA bit of the same register.

31. IE (Interrupt Enable) Register
This register is responsible for enabling and disabling the interrupt. EA
register is set to one for enabling interrupts and set to 0 for disabling the
interrupts. Its bit sequence and their meanings are shown in the following
figure.
EA IE.7
It disables all interrupts. When EA = 0 no interrupt will be
acknowledged and EA = 1 enables the interrupt individually.
- IE.6 Reserved for future use.
- IE.5 Reserved for future use.

32. ES IE.4 Enables/disables serial
port interrupt.
ET1 IE.3 Enables/disables timer1
overflow interrupt.
EX1 IE.2 Enables/disables external
interrupt1.
ET0 IE.1 Enables/disables timer0
overflow interrupt.
EX0 IE.0 Enables/disables external
interrupt0.

33. IP (Interrupt Priority) Register
We can change the priority levels of the interrupts by changing the
corresponding bit in the Interrupt Priority (IP) register as shown in the
following figure.
•A low priority interrupt can only be interrupted by the high priority
interrupt, but not interrupted by another low priority interrupt.
•If two interrupts of different priority levels are received simultaneously,
the request of higher priority level is served.
•If the requests of the same priority levels are received simultaneously,
then the internal polling sequence determines which request is to be
serviced.

34. - IP.6 Reserved for future use.
- IP.5 Reserved for future use.
PS IP.4 It defines the serial port interrupt priority level.
PT1 IP.3 It defines the timer interrupt of 1 priority.
PX1 IP.2 It defines the external interrupt priority level.
PT0 IP.1 It defines the timer0 interrupt priority level.
PX0 IP.0 It defines the external interrupt of 0 priority level.

35. TCON Register
TCON register specifies the type of external interrupt to the
microcontroller.
Addressing modes of 8051:
In this section, we will see different addressing modes of the 8051 microcontrollers.
In 8051 there are 1-byte, 2-byte instructions and very few 3-byte instructions are
present. The opcodes are 8-bit long. As the opcodes are 8-bit data, there are 256
possibilities. Among 256, 255 opcodes are implemented.
The clock frequency is12MHz, so 64 instruction types are executed in just 1 µs, and
rest are just 2 µs. The Multiplication and Division operations take 4 µsto to execute.
In 8051 There are six types of addressing modes.
•Immediate AddressingMode
•Register AddressingMode
•Direct AddressingMode
•Register IndirectAddressing Mode
•Indexed AddressingMode
•Implied AddressingMode

36. Immediate addressing mode
In this Immediate Addressing Mode, the data is provided in the instruction
itself. The data is provided immediately after the opcode. These are some
examples of Immediate Addressing Mode.
MOVA , #0AFH;
MOVR3 , #45H;
MOVDPTR , #FE00H;
In these instructions, the # symbol is used for immediate data.
In the last instruction, there is DPTR. The DPTR stands for Data
Pointer. Using this, it points the external data memory
location. In the first instruction, the immediate data is AFH,
but one 0 is added at the beginning. So when the data is
starting with A to F, the data should be preceded by 0.

37. Register addressing mode : In the register addressing mode the
source or destination data should be present in a register (R0 to
R7). These are some examples of Register Addressing Mode.
MOVA , R5 ;
MOVR2 , #45H ;
MOVR0 , A ;
In 8051, there is no instruction like MOVR5, R7. But we can get the same result by
using this instruction MOV R5, 07H, or by using MOV 05H, R7. But this two instruction
will work when the selected register bank is RB0. To use another register bank and to
get the same effect, we have to add the starting address of that register bank with the
register number. For an example, if the RB2 is selected, and we want to access R5,
then the address will be (10H + 05H = 15H), so the instruction will look like this MOV
15H, R7. Here 10H is the starting address of Register Bank 2.

38. Direct Addressing Mode
In the Direct Addressing Mode, the source or destination address is
specified by using 8-bit data in the instruction. Only the internal data
memory can be used in this mode. Here some of the examples of direct
Addressing Mode.
MOV80H , R6 ;
MOVR2 , 45 H ;
MOVR0 , 05H ;
The first instruction will send the content of registerR6 to port
P0 (Address of Port 0 is 80H). The second one is forgetting
content from 45H to R2. The third one is used to get data from
Register R5 (When register bank RB0 is selected) to register R5.

39. Register indirect addressing Mode
In this mode, the source or destination address is given in the register. By
using register indirect addressing mode, the internal or external
addresses can be accessed. The R0 and R1 are used for 8-bit
addresses, and DPTR is used for 16-bit addresses, no other registers
can be used for addressing purposes. Let us see some examples of this
mode.
MOV0E5H , @R0 ;
MOV@R1 , 80H
In the instructions, the @ symbol is used for register indirect addressing.
In the first instruction, it is showing that theR0 register is used. If the
content of R0 is 40H, then that instruction will take the data which is
located at location 40H of the internal RAM. In the second one, if the
content of R1 is 30H, then it indicates that the content of port P0 will be
stored at location 30H in the internal RAM.

40. stored at location 30H in the internal RAM.
MOVXA , @R1 ;
MOV@DPTR , A ;
In these two instructions, the X in MOVX indicates the external data
memory. The external data memory can only be accessed in register
indirect mode. In the first instruction if the R0 is holding 40H, then A will get
the content of external RAM location40H. And in the second one, the
content of A is overwritten in the location pointed by DPTR.
Indexed addressing mode
In the indexed addressing mode, the source memory can only be
accessed from program memory only. The destination operand is always
the register A. These are some examples of Indexed addressing mode.
MOVCA , @A+PC ;
MOVCA , @A+DPTR ;

41. The C in MOVC instruction refers to code byte. For the
first instruction, let us consider A holds 30H. And the PC
value is1125H. The contents of program memory location
1155H (30H + 1125H) are moved to register A.
Implied Addressing Mode
In the implied addressing mode, there will be a single
operand. These types of instruction can work on specific
registers only. These types of instructions are also known
as register specific instruction. Here are some examples
of Implied Addressing Mode.
RLA ;
SWAPA ;

42. These are 1- byte instruction. The first one is used to
rotate the A register content to the Left. The second one
is used to swap the nibbles in A.
Interrupt structure of 8051:
Now in this section, we will see the interrupt structure of Intel 8051
microcontroller.
Interrupts are basically the events that temporarily suspend the main
program, pass the control to the external sources and execute their task.
It then passes the control to the main program where it had left off.
8051 has five interrupts. These interrupts are INT0, INT1,TO ,T1 , TI/RI.
All of the interrupts can be enabled or disabled by using the IE (interrupt
enable) register.
The interrupt addresses of these interrupts are like below −

43. The interrupt addresses of these interrupts are like
below:
Interrupt Address
INT0 0003H
INT1 000BH
T0 0013H
T1 001BH
TI/RI 0023H

44. Interrupt Enable (IE)Register
This register can be used to enable or disable interrupts
programmatically. This register is an SFR. The address is A8H. This byte
is bit addressable. So it can be programmed by the user. The bits in this
register has a different meaning. The register structure is looking like this:
BitAddress AF AE AD AC AB AA A9 A8
Bit Details EA X X ES ET1 EX1 ET0 EX0
Now, let us see the bit details and different operations
when the value is low (0) and high(1).

45. Bit Details High Value(1) Low Value(0)
EA Least significant 5 bits can decide enable
or disable of these five interrupts.
Disable all five interrupts. It just ignores
the rest five bits.
ES Enable Serial Port Interrupt Disable Serial Port Interrupt
ET1 Enable Timer1 interrupt Disable Timer1 interrupt
EX1 Enable external interrupt 1 (INT1) Disable external interrupt 1 (INT1)
ET0 Enable Timer0 interrupt Disable Timer0 interrupt
EX0 Enable external interrupt 0 (INT0) Disable external interrupt 0 (INT0)

46. Interrupt Priority (IP) Register
All of these five interrupts can be in one or two interrupt level. The priority
levels are level 1 and level 0. Priority level 1 indicates the higher priority,
and level 0 indicates lower priority. This IP register can be used to store
the priority levels for each interrupt. This is also a bit addressable SFR. Its
address is B8H.
BitAddress BF BE BD BC BB BA B9 B8
Bit Details X X X PS PT1 PX1 PT0 PX0
Now, let us see the bit details and different operations
when the value is low (0) and high(1).

47. Bit Details High Value(1) Low Value(0)
PS Set 1 level priority of Serial port interrupt Set 0 level priority of Serial port interrupt
PT1 Set 1 level priority of Timer1 interrupt Set 0 level priority of Timer1 interrupt
PX1 Set 1 level priority of external interrupt 1
(INT1)
Set 0 level priority of external interrupt 1
(INT1)
PT0 Set 1 level priority of Timer0 interrupt Set 0 level priority of Timer0 interrupt
PX0 Set 1 level priority of external interrupt 0
(INT0)
Set 0 level priority of external interrupt 0
(INT0)

48. When all of the five interrupts are in same priority level, and if all of the
interrupts are enabled, then the sequence of interrupts will be INT0,
T0, INT1, T1, TI/R I.
Some specific priority register value can be used to maintain the priorities
of the interrupts. Let the value of Priority register is xxx00101 indicates the
sequence INT0, INT1, TI/RI, T1, T0. But all of the sequences are not
feasible. Like INT0, INT1, TI/RI, T1, T0 is not valid.
External Interrupt
The external interrupts of 8051 are INT0and. INT1 These interrupts can
be programmed to either edge-triggered or level triggered. The TCON
register can be used top rogram external interrupts to edge or level
triggered. The TCON isTimer Control. TCON is another bit addressable
SFR. Here the address is 88H.

49. BitAddress 8F 8E 8D 8C 8B 8A 89 88
Bit Details TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Now, let us see the bit details and different operations
when the value is low (0) and high(1).

50. Bit Details High Value(1) Low Value(0)
PS Set 1 level priority of Serial port interrupt Set 0 level priority of Serial port interrupt
PT1 Set 1 level priority of Timer1 interrupt Set 0 level priority of Timer1 interrupt
PX1 Set 1 level priority of external interrupt 1
(INT1)
Set 0 level priority of external interrupt 1
(INT1)
PT0 Set 1 level priority of Timer0 interrupt Set 0 level priority of Timer0 interrupt
PX0 Set 1 level priority of external interrupt 0
(INT0)
Set 0 level priority of external interrupt 0
(INT0)

51. When all of the five interrupts are in same priority level, and if all of the
interrupts are enabled, then the sequence of interrupts will be INT0,
T0, INT1, T1, TI/R I.
Some specific priority register value can be used to maintain the priorities
of the interrupts. Let the value of Priority register is xxx00101 indicates the
sequence INT0, INT1, TI/RI, T1, T0. But all of the sequences are not
feasible. Like INT0, INT1, TI/RI, T1, T0 is not valid.
External Interrupt
The external interrupts of 8051 are INT0and. INT1 These interrupts can be
programmed to either edge-triggered or level triggered. The TCON register
can be used top rogram external interrupts to edge or level triggered. The
TCON isTimer Control. TCON is another bit addressable SFR. Here the
address is 88H.

52. BitAddress 8F 8E 8D 8C 8B 8A 89 88
Bit Details TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Now, let us see the bit details and different operations when the value is
low (0) and high(1).
Bit
Details
High Value(1) Low Value(0)
IT0 Set ( INT0) as negative edge
triggeredinput.
Set ( INT0) as active low level
triggered input.
IT1 Set ( INT1) as negative edge
triggeredinput.
Set ( INT1) as active low level
triggered input.

53. IE0 This will be 1, when INT0is activated as
level triggered.
This will be 0, when INT0is activated as
edge triggered.
IE1 This will be 1, when INT1 is activated as
level triggered.
This will be 0, when INT1 is activated as
edge triggered.
TR0 Set Timer0 as run mode Set Timer0 as stop mode.
TR1 Set Timer1 as run mode Set Timer1 as stop mode.
TF0 High when Timer T0 overflow occurs. After resetting the timer T0 thiswill also be
changed to 0 state
TF1 High when Timer T1 overflow occurs. After resetting the timer T1 this will also
be changed to 0 state.

54. The IT0 and IT1 are stands for Interrupt Type. These bits are used to
decide whether the INT0 and INT1 will be level trigged or edge triggered.
IE0 and IE1 bits are used to indicate the status of external interrupts.
These bit can be set or reset by the microcontroller itself.
The first four bits are the status information about timers. When TR0 and
TR1 are 1, it indicates the running mode of the timers. These bits provide
software control over the running of timers. Timers can also be controlled
by the hardware. The priority of hardware mode is higher than the
software mode.
The TF0 and TF1 are used to indicate the overflow of timer T0 and T1
respectively. When over flow occurs these flags are set to 1. When the
interrupt is handled by some interrupt service subroutine (ISS), these will
be 0.

55. Serial Port Interrupt
The serial ports can be used either Transmitting mode or reception mode.
The interrupt status for the Transmission is provided by TI, and status for
Reception is provided by RI. These are two bits of SCON(Serial Control).
This is also a bit addressable SFR. The address is98H
BitAddress 9F 9E 9D 9C 9B 9A 99 98
Bit Details SM0 SM1 SM2 REN TB8 RB8 TI RI
The significance of these bits are as follows

56. Bit Details Description
SM0 This is Serial Port Mode 0 shift register
SM1 This is Serial Port Mode 1 (8-bit UAR + variable)
SM2 Enable multiprocessor communication in the mode 2 or 3
REN Set or reset by the software to enable or disable the Reception
TB8 It indicates the 9
th
bit that will be transmitted in mode 2 or 3. It can be
set or reset by the software

57. RB8 In mode 2 or 3, the 9
th
bit was received in mode 1.
TI The transmission interrupt flag. It can be set by
hardware.
RI The receiver interrupt flag. It can be set by hardware
but must be reset by software.

58. The interrupt control system of 8051 is like below −

59. Data Memory Structure of Intel 8051:
The 8051 has 128 bytes of On-Chip RAM. So for accessing that RAM area,
the address space is 00H to 7FH. When we need more data memory, we
can use external RAM. The address space of external RAM is 0000H to
FFFFH.
The external and internal data memory can be added to increase the total amount of
data memory. When we are trying to access the external data memory, then the
read RD or write WR will be the output from 8051. The external data memory address
can be either 8-bit or 16-bit wide. Generally, the one 8-bit address is used but by using
the one-byte address, only 256 bytes of memory can be addressed. So when we need
a little bit of extra memory, we can use one-byte addresses by the Port 0 pins

60. When we need a little more space than 256 bytes, we can use a few lines
of Port 2 pins. Let us consider a case, where three lines of Port 2 are used
to select a page of 256 bytes. Remaining pins can be used for IO tasks. It
is assumed that there is no external program memory. There are some
instructions like MOVX A, @R1, here only one-byte data is sent out from
Port 0.

61. When we want to use large amounts of external data memory, we have to
use instructions like MOVXA, @DPTR. By connecting
the RD and PSEN of the 8051 to AND gate we can combine the data
memory and program memory. By this scheme the data and program may
overlap, so the programmer needs to be cautious about that

62. 8051 Instruction Set:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f
0x00 NOP AJMP LJMP RR INC INC INC INC INC INC INC INC INC INC INC INC
0x10 JBC ACALL LCALL RRC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC
0x20 JB AJMP RET RL ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD
0x30 JNB ACALL RETI RLC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC
0x40 JC AJMP ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL
0x50 JNC ACALL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL
0x60 JZ AJMP XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL
Instructions by opcode

63. 0x70 JNZ ACALL ORL JMP MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
0x80 SJMP AJMP ANL MOVC DIV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
0x90 MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB
0xa0 ORL AJMP MOV INC MUL ? MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
0xb0 ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE
0xc0 PUSH AJMP CLR CLR SWAP XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH XCH
0xd0 POP ACALL SETB SETB DA DJNZ XCHD XCHD DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ
0xe0 MOVX AJMP MOVX MOVX CLR MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
0xf0 MOVX ACALL MOVX MOVX CPL MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV

64. Alphabetical List of Instructions
•ACALL - Absolute Call
•ADD, ADDC - Add Accumulator (With Carry)
•AJMP - Absolute Jump
•ANL - Bitwise AND
•CJNE - Compare and Jump if Not Equal
•CLR - Clear Register
•CPL - Complement Register
•DA - Decimal Adjust
•DEC - Decrement Register
•DIV - Divide Accumulator by B
•DJNZ - Decrement Register and Jump if Not Zero
•INC - Increment Register
•JB - Jump if Bit Set
•JBC - Jump if Bit Set and Clear Bit
•JC - Jump if Carry Set
•JMP - Jump to Address
•JNB - Jump if Bit Not Set
•JNC - Jump if Carry Not Set
•JNZ - Jump if Accumulator Not Zero
•JZ - Jump if Accumulator Zero
•LCALL - Long Call
•LJMP - Long Jump
•MOV - Move Memory
•MOVC - Move Code Memory

65. •MOVX - Move Extended Memory
•MUL - Multiply Accumulator by B
•NOP - No Operation
•ORL - Bitwise OR
•POP - Pop Value From Stack
•PUSH - Push Value Onto Stack
•RET - Return From Subroutine
•RETI - Return From Interrupt
•RL - Rotate Accumulator Left
•RLC - Rotate Accumulator Left Through Carry
•RR - Rotate Accumulator Right
•RRC - Rotate Accumulator Right Through Carry
•SETB - Set Bit
•SJMP - Short Jump
•SUBB - Subtract From Accumulator With Borrow
•SWAP - Swap Accumulator Nibbles
•XCH - Exchange Bytes
•XCHD - Exchange Digits
•XRL - Bitwise Exclusive OR
•Undefined - Undefined Instruction

67. 8051 Instruction Set: ACALL:
Description: ACALL unconditionally calls a subroutine at the indicated code address. ACALL
pushes the address of the instruction that follows ACALL onto the stack, least-significant-byte
first, most-significant-byte second. The Program Counter is then updated so that program
execution continues at the indicated address.
8051 Instruction Set: ADD :
Description: Description: ADD and ADDC both add the value operand to the value of the
Accumulator, leaving the resulting value in the Accumulator. The value operand is not
affected. ADD and ADDC function identically except that ADDC adds the value of operand as
well as the value of the Carry flag whereas ADD does not add the Carry flag to the result.
8051 Instruction Set: AJMP
Description: AJMP unconditionally jumps to the indicated code address. The new value for
the Program Counter is calculated by replacing the least-significant-byte of the Program
Counter with the second byte of the AJMP instruction, and replacing bits 0-2 of the most-
significant-byte of the Program Counter with 3 bits that indicate the page of the byte
following the AJMP instruction. Bits 3-7 of the most-significant-byte of the Program Counter
remain unchaged.

68. 8051 Instruction Set: ANL:
Description: ANL does a bitwise "AND" operation between operand1 and operand2, leaving
the resulting value in operand1. The value of operand2 is not affected. A logical "AND"
compares the bits of each operand and sets the corresponding bit in the resulting byte only if
the bit was set in both of the original operands, otherwise the resulting bit is cleared.
8051 Instruction Set: CJNE:
Description: CJNE compares the value of operand1 and operand2 and branches to the
indicated relative address if operand1 and operand2 are not equal. If the two operands are
equal program flow continues with the instruction following the CJNE instruction.
8051 Instruction Set: CLR
Description: CLR clears (sets to 0) all the bit(s) of the indicated register. If the register is a bit
(including the carry bit), only the specified bit is affected. Clearing the Accumulator sets the
Accumulator's value to 0.
8051 Instruction Set: CPL :
Description: CPL complements operand, leaving the result in operand. If operand is a single bit then the state of the bit will
be reversed. If operand is the Accumulator then all the bits in the Accumulator will be reversed. This can be thought of as
"Accumulator Logical Exclusive OR 255" or as "255-Accumulator." If the operand refers to a bit of an output Port, the value
that will be complemented is based on the last value written to that bit, not the last value read from it.

69. 8051 Instruction Set: DA:
Description: DA adjusts the contents of the Accumulator to correspond to a BCD (Binary Coded Decimal) number after two
BCD numbers have been added by the ADD or ADDC instruction. If the carry bit is set or if the value of bits 0-3 exceed 9, 0x06
is added to the accumulator. If the carry bit was set when the instruction began, or if 0x06 was added to the accumulator in
the first step, 0x60 is added to the accumulator.
8051 Instruction Set: DEC:
8051 Instruction Set: DIV
Description: Divides the unsigned value of the Accumulator by the unsigned value of the "B" register. The
resulting quotient is placed in the Accumulator and the remainder is placed in the "B" register.
The Carry flag (C) is always cleared.
The Overflow flag (OV) is set if division by 0 was attempted, otherwise it is cleared.
Description: DJNZ decrements the value of register by 1. If the initial value of register is 0, decrementing the
value will cause it to reset to 255 (0xFF Hex). If the new value of register is not 0 the program will branch to
the address indicated by relative addr. If the new value of register is 0 program flow continues with the
instruction following the DJNZ instruction.
8051 Instruction Set: DJNZ
Operation: DJNZ
Function: Decrement and Jump if Not Zero
Syntax: DJNZ register,reladdr
Description: DEC decrements the value of register by 1. If the initial value of register is 0, decrementing the value will cause it
to reset to 255 (0xFF Hex). Note: The Carry Flag is NOT set when the value "rolls over" from 0 to 255.

70. 8051 Instruction Set: INC
Operation: INC
Function: Increment Register
Syntax: INC register
Description: INC increments the value of register by 1. If the initial value of register is 255 (0xFF Hex),
incrementing the value will cause it to reset to 0. Note: The Carry Flag is NOT set when the value "rolls over"
from 255 to 0.
In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented. If the initial value
of DPTR is 65535 (0xFFFF Hex), incrementing the value will cause it to reset to 0. Again, the Carry Flag is NOT set
when the value of DPTR "rolls over" from 65535 to 0.
8051 Instruction Set: JB
Operation: JB
Function: Jump if Bit Set
Syntax: JB bit addr, reladdr
Description: JB branches to the address indicated by reladdr if the bit indicated by bit addr is set. If the bit is not
set program execution continues with the instruction following the JB instruction.
8051 Instruction Set: JBC
Operation: JBC
Function: Jump if Bit Set and Clear Bit
Syntax: JB bit addr, reladdr

71. Description: JBC will branch to the address indicated by reladdr if the bit indicated by bit addr is set. Before
branching to reladdr the instruction will clear the indicated bit. If the bit is not set program execution continues
with the instruction following the JBC instruction.
8051 Instruction Set: JC
Operation: JC
Function: Jump if Carry Set
Syntax: JC reladdr
Description: JC will branch to the address indicated by reladdr if the Carry Bit is set. If the Carry Bit is not set
program execution continues with the instruction following the JC instruction.
8051 Instruction Set: JMP
Operation: JMP
Function: Jump to Data Pointer + Accumulator
Syntax: JMP @A+DPTR
Description: JMP jumps unconditionally to the address represented by the sum of the value of DPTR and the
value of the Accumulator.
8051 Instruction Set: JNB
Operation: JNB
Function: Jump if Bit Not Set
Syntax: JNB bit addr,reladdr

72. Description: JNB will branch to the address indicated by reladdress if the indicated bit is not set. If the bit is set
program execution continues with the instruction following the JNB instruction.
8051 Instruction Set: JNC
Operation: JNC
Function: Jump if Carry Not Set
Syntax: JNC reladdr
Description: JNC branches to the address indicated by reladdr if the carry bit is not set. If the carry bit is set
program execution continues with the instruction following the JNB instruction.
8051 Instruction Set: JNZ
Operation: JNZ
Function: Jump if Accumulator Not Zero
Syntax: JNZ reladdr
Description: JNZ will branch to the address indicated by reladdr if the Accumulator contains any value except 0. If
the value of the Accumulator is zero program execution continues with the instruction following the JNZ
instruction.
8051 Instruction Set: JZ
Operation: JZ
Function: Jump if Accumulator Zero
Syntax: JNZ reladdr

73. 8051 Instruction Set: LCALL
Operation: LCALL
Function: Long Call
Syntax: LCALL code addr
Description: LCALL calls a program subroutine. LCALL increments the program counter by 3 (to point to the
instruction following LCALL) and pushes that value onto the stack (low byte first, high byte second). The Program
Counter is then set to the 16-bit value which follows the LCALL opcode, causing program execution to continue at
that address.
8051 Instruction Set: LJMP
Operation: LJMP
Function: Long Jump
Syntax: LJMP code addr
Description: LJMP jumps unconditionally to the specified code addr.
8051 Instruction Set: MOV
Operation: MOV
Function: Move Memory
Syntax: MOV operand1,operand2
Description: MOV copies the value of operand2 into operand1. The value of operand2 is not affected. Both
operand1 and operand2 must be in Internal RAM.

74. . No flags are affected unless the instruction is moving the value of a bit into the carry bit in which case the carry
bit is affected or unless the instruction is moving a value into the PSW register (which contains all the program
flags).
** Note: In the case of "MOV iram addr,iram addr", the operand bytes of the instruction are stored in reverse
order. That is, the instruction consisting of the bytes 0x85, 0x20, 0x50 means "Move the contents of Internal
RAM location 0x20 to Internal RAM location 0x50" whereas the opposite would be generally presumed.
8051 Instruction Set: MOVC
Operation: MOVC
Function: Move Code Byte to Accumulator
Syntax: MOVC A,@A+register
Description: MOVC moves a byte from Code Memory into the Accumulator. The Code Memory address from
which the byte will be moved is calculated by summing the value of the Accumulator with either DPTR or the
Program Counter (PC). In the case of the Program Counter, PC is first incremented by 1 before being summed with
the Accumulator.
8051 Instruction Set: MOVX
Operation: MOVX
Function: Move Data To/From External Memory
(XRAM)
Syntax: MOVX operand1,operand2

75. Description: MOVX moves a byte to or from External Memory into or from the Accumulator.
If operand1 is @DPTR, the Accumulator is moved to the 16-bit External Memory address indicated by DPTR. This
instruction uses both P0 (port 0) and P2 (port 2) to output the 16-bit address and data. If operand2 is DPTR then
the byte is moved from External Memory into the Accumulator.
If operand1 is @R0 or @R1, the Accumulator is moved to the 8-bit External Memory address indicated by the
specified Register. This instruction uses only P0 (port 0) to output the 8-bit address and data. P2 (port 2) is not
affected. If operand2 is @R0 or @R1 then the byte is moved from External Memory into the Accumulator.
8051 Instruction Set: MUL
Operation: MUL
Function: Multiply Accumulator by B
Syntax: MUL AB
Description: Multiples the unsigned value of the Accumulator by the unsigned value of the "B" register. The least
significant byte of the result is placed in the Accumulator and the most-significant-byte is placed in the "B"
register.
The Carry Flag (C) is always cleared.
The Overflow Flag (OV) is set if the result is greater than 255 (if the most-significant byte is not zero), otherwise
it is cleared.
8051 Instruction Set: NOP
Operation: NOP
Function: None, waste time
Syntax: No Operation

76. Description: NOP, as it's name suggests, causes No Operation to take place for one machine cycle. NOP is
generally used only for timing purposes. Absolutely no flags or registers are affected.
8051 Instruction Set: ORL
Operation: ORL
Function: Bitwise OR
Syntax: ORL operand1,operand2
Description: ORL does a bitwise "OR" operation between operand1 and operand2, leaving the resulting value in
operand1. The value of operand2 is not affected. A logical "OR" compares the bits of each operand and sets the
corresponding bit in the resulting byte if the bit was set in either of the original operands, otherwise the
resulting bit is cleared.
8051 Instruction Set: POP
Operation: POP
Function: Pop Value From Stack
Syntax: POP
Description: POP "pops" the last value placed on the stack into the iram addr specified. In other words, POP will
load iram addr with the value of the Internal RAM address pointed to by the current Stack Pointer. The stack
pointer is then decremented by 1.
8051 Instruction Set: PUSH
Operation: PUSH
Function: Push Value Onto Stack
Syntax: PUSH

77. Description: PUSH "pushes" the value of the specified iram addr onto the stack. PUSH first increments the value
of the Stack Pointer by 1, then takes the value stored in iram addr and stores it in Internal RAM at the location
pointed to by the incremented Stack Pointer.
8051 Instruction Set: RET
Operation: RET
Function: Return From Subroutine
Syntax: RET
Description: RET is used to return from a subroutine previously called by LCALL or ACALL. Program execution
continues at the address that is calculated by popping the topmost 2 bytes off the stack. The most-significant-byte
is popped off the stack first, followed by the least-significant-byte.
8051 Instruction Set: RETI
Operation: RETI
Function: Return From Interrupt
Syntax: RETI
Description: RETI is used to return from an interrupt service routine. RETI first enables interrupts of equal and
lower priorities to the interrupt that is terminating. Program execution continues at the address that is calculated
by popping the topmost 2 bytes off the stack. The most-significant-byte is popped off the stack first, followed by
the least-significant-byte.
RETI functions identically to RET if it is executed outside of an interrupt service routine.

78. 8051 Instruction Set: RL
Operation: RL
Function: Rotate Accumulator Left
Syntax: RL A
Description: Shifts the bits of the Accumulator to the left. The left-most bit (bit 7) of the Accumulator is loaded
into bit 0.
8051 Instruction Set: RLC
Operation: RLC
Function: Rotate Accumulator Left Through Carry
Syntax: RLC A
Description: Shifts the bits of the Accumulator to the left. The left-most bit (bit 7) of the Accumulator is loaded
into the Carry Flag, and the original Carry Flag is loaded into bit 0 of the Accumulator. This function can be used
to quickly multiply a byte by 2.
8051 Instruction Set: RR
Operation: RR
Function: Rotate Accumulator Right
Syntax: RR A
Description: Shifts the bits of the Accumulator to the right. The right-most bit (bit 0) of the Accumulator is
loaded into bit 7.

79. 8051 Instruction Set: RRC
Operation: RRC
Function: Rotate Accumulator Right Through Carry
Syntax: RRC A
Description: Shifts the bits of the Accumulator to the right. The right-most bit (bit 0) of the Accumulator is loaded
into the Carry Flag, and the original Carry Flag is loaded into bit 7. This function can be used to quickly divide a
byte by 2.
8051 Instruction Set: SETB
Operation: SETB
Function: Set Bit
Syntax: SETB bit addr
Description: Sets the specified bit.
8051 Instruction Set: SJMP
Operation: SJMP
Function: Short Jump
Syntax: SJMP reladdr
Description: SJMP jumps unconditionally to the address specified reladdr. Reladdr must be within -128 or +127
bytes of the instruction that follows the SJMP instruction.

80. 8051 Instruction Set: SUBB
Operation: SUBB
Function: Subtract from Accumulator With Borrow
Syntax: SUBB A,operand
Description: SUBB subtract the value of operand and the Carry Flag from the value of the Accumulator, leaving
the resulting value in the Accumulator. The value operand is not affected.
The Carry Bit (C) is set if a borrow was required for bit 7, otherwise it is cleared. In other words, if the unsigned
value being subtracted is greater than the Accumulator the Carry Flag is set.
The Auxillary Carry (AC) bit is set if a borrow was required for bit 3, otherwise it is cleared. In other words, the bit
is set if the low nibble of the value being subtracted was greater than the low nibble of the Accumulator.
The Overflow (OV) bit is set if a borrow was required for bit 6 or for bit 7, but not both. In other words, the
subtraction of two signed bytes resulted in a value outside the range of a signed byte (-128 to 127). Otherwise it
is cleared.
8051 Instruction Set: SWAP
Operation: SWAP
Function: Swap Accumulator Nibbles
Syntax: SWAP A
Description: SWAP swaps bits 0-3 of the Accumulator with bits 4-7 of the Accumulator. This instruction is identical
to executing "RR A" or "RL A" four times.

81. 8051 Instruction Set: Undefined Instruction
Operation: Undefined Instruction
Function: Undefined
Syntax: ???
Description: The "Undefined" instruction is, as the name suggests, not a documented instruction. The 8051
supports 255 instructions and OpCode 0xA5 is the single OpCode that is not used by any documented function.
Since it is not documented nor defined it is not recommended that it be executed. However, based on my
research, executing this undefined instruction takes 1 machine cycle and appears to have no effect on the system
except that the Carry Bit always seems to be set.
Note: We received input from an 8052.com user that the undefined instruction really has a format of Undefined
bit1,bit2 and effectively copies the value of bit2 to bit1. In this case, it would be a three-byte instruction. We
haven't had an opportunity to verify or disprove this report, so we present it to the world as "additional
information."
Note: It has been reported that Philips 8051 model P89C669 uses instruction prefix 0xA5 to let the user access a
different (extended) SFR area.
8051 Instruction Set: XCH
Operation: XCH
Function: Exchange Bytes
Syntax: XCH A,register
Description: Exchanges the value of the Accumulator with the value contained in register.

82. 8051 Instruction Set: XCHD
Operation: XCHD
Function: Exchange Digit
Syntax: XCHD A,[@R0/@R1]
Description: Exchanges bits 0-3 of the Accumulator with bits 0-3 of the Internal RAM address pointed to indirectly
by R0 or R1. Bits 4-7 of each register are unaffected.
8051 Instruction Set: XRL
Operation: XRL
Function: Bitwise Exclusive OR
Syntax: XRL operand1,operand2
Description: XRL does a bitwise "EXCLUSIVE OR" operation between operand1 and operand2, leaving the
resulting value in operand1. The value of operand2 is not affected. A logical "EXCLUSIVE OR" compares the bits of
each operand and sets the corresponding bit in the resulting byte if the bit was set in either (but not both) of the
original operands, otherwise the bit is cleared.

83. Data transfer group in 8051
In 8051 Microcontroller there is 28 different instructions under the Data Transfer
Group. In total there are 79 opcodes. The flags are not affected by using the data
transfer instructions, but the P (Parity) flag may change if the value of A register
is changed using Data Transfer Instruction. Similarly, when a data is transferred
to the PSW register, the flags will change.
In the following table, we will see the Mnemonics, Lengths, Execution Time in
terms of the machine cycle, Number of Opcodes etc.
MOV A, Rn MOV A, a8 MOV A, @Ri MOV A, #d8 MOV Rn, A MOV Rn, a8 MOV Rn, #d8
MOV a8, A MOV a8, Rn MOV a8, a8 MOV a8, @Ri MOV a8, #d8 MOV @Ri, A MOV @Ri, a8
MOV @Ri, #d8 MOV DPTR, #d16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX
A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH a8 POP a8 XCH A, Rn XCH A, a8 XCH A,
@Ri XCHD A, @Ri

84. Logical Group in 8051 (Ingluding Rotate and SWAP) Instructions:
In 8051 Microcontroller there is 25 different instructions under the Logical Group.
In total there are 49 opcodes. The Carry Flag (CY) affects only by instruction RRC
and RLC.
In the following table, we will see the Mnemonics, Lengths, Execution Time in
terms of the machine cycle, Number of Opcodes etc.
ANL A, Rn ANL A, a8 ANL A, @Ri ANL A, #d8 ANL a8, A ANL a8, #d8 ORL A, Rn
ORL A, a8 ORL A, @Ri ORL A, #d8
ORL a8, A ORL a8, #d8 XRL A, Rn XRL A, a8 XRL A, @Ri XRL A, #d8 XRL a8, A
XRL a8, #d8 CLR A CPL ARL A RLC A
RR A RRC A SWAP A
Arithmetic group in 8051
In 8051 Microcontroller there are 24 different instructions under the Arithmetic
Group. In total there are 64 opcodes. The Carry Flag (CY), Auxiliary Carry (AC)and
Overflow flag (OV) are affected based on the result of ADD, ADDC, SUBB etc.

85. The multiple and divide instructions clear the Carry flag, and also does not affect
the AC flag. After execution of multiplication, the OV flag will be 1 when the
result is greater than FFH. Otherwise, it is 0. Similarly, after division OV flag is 1
when the content of B is 00H before division, otherwise it is 0. The DA A (Decimal
Adjust Accumulator) affects the Carry Flag only.
In the following table, we will see the Mnemonics, Lengths, Execution Time in
terms of the machine cycle, Number of Opcodes etc.
ADD A, Rn ADD A, a8 ADD A, @Ri ADD A, #d8 ADDC A, Rn ADDC A, a8 ADDC
A, @Ri ADDC A, #d8 SUBB A, Rn SUBB A, a8 SUBB A, @Ri SUBB A, #d8 INC A
INC Rn INC a8 INC @Ri DEC A DEC Rn DEC a8 DEC @Ri INC DPTR MUL AB
DIV AB DA A
Bit-processing group in 8051
In 8051 Microcontroller there is 17 different instructions under the Logical
Group. In total there are 17 opcodes. The Carry Flag (CY) acts like the single-bit
accumulator in different bit processing instructions.

86. In the following table, we will see the Mnemonics, Lengths, Execution Time in
terms of the machine cycle, Number of Opcodes etc.
CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit
ORL C, /bit MOV C, bit MOV bit, C JC rel
JNC rel JB bit, rel JNB bit, rel JBC bit, rel
Loop and Jump Instructions
Looping in the 8051
Repeating a sequence of instructions a certain number of times is called a loop.
An instruction DJNZ reg, label is used to perform a Loop operation. In this
instruction, a register is decremented by 1; if it is not zero, then 8051 jumps to
the target address referred to by the label.
The register is loaded with the counter for the number of repetitions prior to the
start of the loop. In this instruction, both the registers decrement and the
decision to jump are combined into a single instruction. The registers can be any
of R0–R7. The counter can also be a RAM location.

87. Conditional Jumps
The following table lists the conditional jumps used in 8051 −
JZ Jump if A = 0
JNZ Jump if A ≠ 0
DJNZ Decrement and Jump if register ≠ 0
CJNE A, dataJump if A ≠ data
CJNE reg, #data Jump if byte ≠ data
JC Jump if CY = 1
JNC Jump if CY ≠ 1
JB Jump if bit = 1
JNB Jump if bit = 0
JBC

88. Unconditional Jump Instructions
LJMP (long jump) − LJMP is 3-byte instruction in which the first byte represents
opcode, and the second and third bytes represent the 16-bit address of the
target location.
The 2-byte target address is to allow a jump to any memory location from 0000
to FFFFH.
SJMP (short jump) − It is a 2-byte instruction where the first byte is the opcode
and the second byte is the relative address of the target location. The relative
address ranges from 00H to FFH which is divided into forward and backward
jumps; that is, within –128 to +127 bytes of memory relative to the address of
the current PC (program counter). In case of forward jump, the target address
can be within a space of 127 bytes from the current PC. In case of backward
jump, the target address can be within –128 bytes from the current PC.

89. CALL Instructions
There are two instructions − LCALL and ACALL.
LCALL (Long Call): LCALL is a 3-byte instruction where the first byte represents the opcode
and the second and third bytes are used to provide the address of the target subroutine.
LCALL can be used to call subroutines which are available within the 64K-byte address space
of the 8051.
To make a successful return to the point after execution of the called subroutine, the CPU
saves the address of the instruction immediately below the LCALL on the stack. Thus, when a
subroutine is called, the control is transferred to that subroutine, and the processor saves the
PC (program counter) on the stack and begins to fetch instructions from the new location. The
instruction RET (return) transfers the control back to the caller after finishing execution of the
subroutine. Every subroutine uses RET as the last instruction.
ACALL (Absolute Call): ACALL is a 2-byte instruction, in contrast to LCALL which is 3 bytes. The
target address of the subroutine must be within 2K bytes because only 11 bits of the 2 bytes
are used for address. The difference between the ACALL and LCALL is that the target address
for LCALL can be anywhere within the 64K-bytes address space of the 8051, while the target
address of CALL is within a 2K-byte range.

90. Statement 1: – exchange the content of FFh and FF00h
Solution: – here one is internal memory location and other is memory external
location. so first the content of ext memory location FF00h is loaded in acc. then
the content of int memory location FFh is saved first and then content of acc is
transferred to FFh. now saved content of FFh is loaded in acc and then it is
transferred to FF00h.
Mov dptr, #0FF00h ; take the address in dptr
Movx a, @dptr ; get the content of 0050h in a
Mov r0, 0FFh ; save the content of 50h in r0
Mov 0FFh, a ; move a to 50h
Mov a, r0 ; get content of 50h in a
Movx @dptr, a ; move it to 0050h
Duplication and Subtraction

91. Statement 2: – store the higher nibble of r7 in to both nibbles
of r6
Solution: –first we shall get the upper nibble of r7 in r6. Then
we swap nibbles of r7 and make OR operation with r6 so the
upper and lower nibbles are duplicated
Mov a, r7 ; get the content in acc
Anl a, #0F0h ; mask lower bit
Mov r6, a ; send it to r6
Swap a ; xchange upper and lower nibbles
of acc
Orl a, r6 ; OR operation
Mov r6, a ; finally load content in r6

92. Statement 3: – treat r6-r7 and r4-r5 as two 16 bit registers.
Perform subtraction between them. Store the result in 20h
(lower byte) and 21h (higher byte).
Solution: – first we shall clear the carry. Then subtract the
lower bytes afterward then subtract higher bytes.
Clr c ; clear carry
Mov a, r4 ; get first lower byte
Subb a, r6 ; subtract it with other
Mov 20h, a ; store the result
Mov a, r5 ; get the first higher byte
Subb a, r7 ; subtract from other
Mov 21h, a ; store the higher byte

93. Division & Data Transfer
Statement 4: – divide the content of r0 by r1. Store the result in r2 (answer) and
r3 (reminder). Then restore the original content of r0.
Solution:-after getting answer to restore original content we have to multiply
answer with divider and then add reminder in that.
Mov a, r0 ; get the content of r0 and r1
Mov b, r1 ; in register A and B
Div ab ; divide A by B
Mov r2, a ; store result in r2
Mov r3, b ; and reminder in r3
Mov b, r1 ; again get content of r1 in B
Mul ab ; multiply it by answer
Add a, r3 ; add reminder in new answer
Mov r0, a ; finally restore the content of r0

94. Statement 5: – transfer the block of data from 20h to 30h to external location
1020h to 1030h.
Solution: – here we have to transfer 10 data bytes from internal to external
RAM. So first, we need one counter. Then we need two pointers one for source
second for destination.
Mov r7, #0Ah ; initialize counter by 10d
Mov r0, #20h ; get initial source location
Mov dptr, #1020h ; get initial destination location
Nxt: Mov a, @r0 ; get first content in acc
Movx @dptr, a ; move it to external location
Inc r0 ; increment source location
Inc dptr ; increase destination location
Djnz r7, nxt ; decrease r7. if zero then over otherwise move next
Various Comparison Programs

95. 2) 8 BIT ADDITION
MOV A, #04
MOV B,#02
ADD A,B
DA A
RET
INPUT OUTPUT
REGISTER DATA REGISTER DATA
A 05 A 11
B 06

96. 3) 8 BIT SUBSTRACTION
MOV A, #0F
MOV B,#04
SUBB A,B
DA A
RET
INPUT OUTPUT
REGISTER DATA REGISTER DATA
A 0F A 11
B 04

97. 4) Multiplication of two 8 bit numbers
MOV A, #02
MOV B,#06
MUL AB
RET
INPUT OUTPUT
REGISTER DATA REGISTER DATA
A 02 A 0C
B 06

98. 5) Division of two 8 bit numbers
MOV A, #04
MOV B,#02
DIV AB
RET
INPUT OUTPUT
REGISTER DATA REGISTER DATA
A 04 A 02
B 02

99. 6) . Write an assembly language program to find
the square of a given numberN.
Let N=05
mov a,#05 // a=N=05
mov b,a
mul ab
mov 30h,a // result is stored in 30hand 31h
mov 31h,b
end
Result:
Input: Output:

100. 7).Write an assembly language program to find whether given
eight bit number is odd or even. If odd store 00h in
accumulator. If even store FFh in accumulator.**
mov a,20h // 20h=given number, to find is it even or odd
Jb acc.0, odd
mov a,#0FFh
sjmp ext
odd: mov a,#00h
ext: end
Result:
Input: Output:
20h: a:

101. THANK YOU