The document provides an overview of the NXP i.MX6 processor Mars Board, detailing its key hardware specifications such as a dual-core ARM Cortex-A9 processor, memory capacity, and various interfaces including HDMI, USB, and Ethernet. It describes the architecture and communication protocols like SPI, I2C, and UART implemented on the board. Additionally, it covers display interfaces and debug capabilities of the board, emphasizing its versatility as a development platform.

1. NXP IMX6 Processor
Mars Board
Overview

2. Introduction
• Development platform based on NXP IMX6 Dual
Core processor
– ARM Cortex-A9 Dual core upto 1GHz
• 4 Gbyte EMMC Memory
• 1 Gbyte DDR3 SDRAM
• 2 Mbyte SPI Flash for boot loader
• HDMI Video / Audio Output
• 1 Giga Bit Ethernet
• USB OTG
• USB Host x 2

3. MarsBoard

4. Hardware Block Diagram

5. NXP IMX6 Processor
• 2 x ARM Cortex-A9 upto 1GHz
• 32 Kbyte L1 instruction cache
• 32 Kbyte L1 Data Cache
• Cortex-A9 NEON Media Processing Engine
• 2D & 3D Graphics Processor
• Video Decoder / Encoder
– 1080p60 Decode
– 1080p60 Encode, Dual 720p60 Encode
• DDR & NAND Memory Interface

6. NXP IMX6 Architecture

7. DDR3 SDRAM
• Double Data Rate 3 Synchronous Dynamic RAM
• 4 x 256 MB DDR3 SDRAM
• Address Lines multiplexed with ROW & Column
• 16-Bit Data Bus
• Differential Clock
• DDR3 Control Signals
– Chip Select
– Row / Column Address Strobes
• Data Mask

8. DDR3 Interface

9. eMMC Flash
• Flash Memory & MMC Controller into a single
Chip
• Used as embedded non-volatile memory
• Permanent attached to board
• Does not support SPI protocol
• All mobile phone & tablets uses this as
internal memory as well as for images.

10. eMMC Interface
NXP
i.MX6
eMMC
Flash
SD3 Data [ 3 – 0 ]
SD3 Reset
SD3 Clock
SD3 CMD

11. General Purpose I/O
• Generic Pin on an IC / Board
• Configured as Input or Output
• Can be enabled / disabled
• Logic Level
– High
– Low
• Input values are readable
• Output values are writable / readable
• Input configured pins also can be used as Interrupt
• No predefined purpose

12. Serial Peripheral Interface
• Synchronous Serial Communication Interface
• Used for Short distance. Basically with in the
board
• Full duplex mode with master slave architecture
• Also called as four-wire bus
• Pins
– MISO : Master Input Slave Output
– MOSI : Master Output Slave Input
– SCK : Serial Clock
– SS : Slave Select

13. SPI Model
SPI
Master
SPI
Slave 1
MOSI
MISO
SCK
SS1
SPI
Slave 2
SS2

14. Inter Integrated Circuit Inteface
• Multi master, multi slave serial interface bus
• Uses only two bi-directional open drain lines
– SDA : Serial Data Line
– SCL : Serial Clock Line
• Since lines are open drain, these pins needs to
be pulled high.
– Normally pull up resistor will be 4.7 K / 10K

15. I2C Model
I2C
Master
uC
I2C
Slave
I2C
Slave
I2C
Slave
VCC
SCL
SDA
R R

16. UART
• Univeral Asynchronuos Receiver / Transmitter
• Supports NRZ encoding format
• 7 or 8 bit data
• 1 or 2 Stop bits
• Hardware Flow Control
– RTS – Request to Send
– CTS – Clear to Send
• Programmable Parity ( even, odd and none )
• RS485, RS232 compatible

17. UART Interface
NXP
IMX6
UART
Serial
Device
TXD
RXD
RTS
CTS

18. Secure Digital Interface
• Provides interface with SD/SDIO/MMC Cards
• Handles bus transaction with SD / SDIO /
MMC Cards
• Evolution of old MMC Technology
• Provides Security, Capacity, Performance
• Interface categorization as follows,
– Memory Card
– IO Card
– Combo Card ( Both memory & IO )

19. Micro SD Card Interface
NXP
i.MX6
Micro SD
Card
SD Data [ 3 – 0 ]
SD Reset
SD Clock
SD CMD
SD CD

20. HDMI
• High Definition Multi Media Interface
• Transfers uncompressed Video, Audio and
Data using a Single Cable
• High bandwidth Data Content Protection
• HDMI System has one to one connectivity with
– HDMI Source which is the transmitter
– HDMI Sinks which is the receiver
• Data Display Channel
– Configuration & Data Exchange in HDMI

21. HDMI Interface

22. Parallel RGB LCD Interface
• Parallel Video Interface
• Supports upto 24 Bit Data
• Supports BT.656 Data format ( 8 Bit )
• Supports BT.1120 Data format ( 16 Bit )
• Supports HDTV standards SMPTE274
• Supports HDTV Standards SMPTE296
• RGB Color Depth fully configurable upto 8 Bit /
color value

23. Parallel RGB LCD Interface

24. LVDS Display Bridge
• Linear Voltage Differential Signaling
• Used to connect with Display with LVDS receiver
• Featured with Synchronization & Control
• Data arrangement will be based on external
Display
• LVDS Display Port
– 1 Clock Channel
– 4 Data Channel
• Each pair contains LVDS Special differential pads

25. LVDS Interface

26. RGMII
• Reduced Giga bit Media Independent Interface
• Used to interface between Ethernet MAC & PHY
• Half the number of data pins used in GMII
• Data clocking will be done at both rising and
falling edges of the clock
• Carrier Sense / Collision Detection
• Management Interface
– Management Interface Clock ( MDC )
– Management Interface I/O ( MDIO )

27. RGMII Interface

28. USB Host
• USB 2.0 Host controller
• 2 x USB 2.0 Host Ports
• Host Mode Event Handler
• USB Enhanced Host Controller Interface
• USB Host uses Master / Slave Architecture
• USB Host – Master
• USB Device – Slave

29. USB Host Interface

30. USB OTG
• USB On – The – GO
• Allows devices to switch back & forth between
USB Host & Device
• Will acts as Host when device connected
• Will acts as USB Device when it is connected
with Host

31. USB OTG Interface

32. Secure JTAG
• Provides debug & test control with maximum
security
• Joint Test Access Group
• IEEE Standard 1149.1 v2001 ( JTAG )
• Debug related control & status
• Putting the selected cores into reset / monitor
• JTAG Boundary Scan
– Provides access to all logic signals of complex IC
– Provides access to device pins

33. JTAG Interface

34. Thank You