FPGA Based RGB LED Display

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FPGA Based RGB LED Display

  1. 1. FPGA Based RGB LED Tiling System
  2. 2. Contents• System Overview• Digital Design• Software Design• Board Design
  3. 3. Software for decoding and SYSTEM GUI transmission OVERVIEW UARTControl Block Block Ram LED Matrix FPGA
  4. 4. FPGA MODULEPC CONNECTIVITY STORAGE FPGACOMMUNICATION LOGIC & CONTROL
  5. 5. PC CONNECTIVITY• Serial Transfer :UART MODULE – RS 232 Protocol – Asynchronous Transfer – Full Duplex – Tested at baud rate of 9600bps to 115200bps
  6. 6. UART MODULE IMPLEMENTATION Marc STOP BIT START DATA BIT SIN=0 SIN=0 START DATA DATA DATA DATA MARC BIT 0 1 2 3SIN=1 SIN=1 STOP DATA DATA DATA DATA BIT 7 6 5 4
  7. 7. STORAGE• Block RAM – Dual Port – Default : 256 X 32bit RAM – Combined three to get 192 X 72bit RAM
  8. 8. STORAGE: ORGANISATION OF DATALED 1.1 LED 1.1 LED 1.1 LED 1.2 LED 1.2 LED 1.2RED BLUE GREEN RED BLUE GREENLSB(0) LSB(0) LSB(0) LSB(0) LSB(0) LSB(0)LED 1.1 LED 1.1 LED 1.1 LED 1.2 LED 1.2 LED 1.2RED BLUE GREEN RED BLUE GREENMSB(7) MSB(7) MSB(7) MSB(7) MSB(7) MSB(7) LED LED 1.1 1.2LED 2.1 LED 2.1 LED 2.1 LED 2.2 LED 2.2 LED 2.2RED BLUE GREEN RED BLUE GREEN LED LEDLSB(0) LSB(0) LSB(0) LSB(0) LSB(0) LSB(0) 2.1 2.2LED 2.1 LED 2.1 LED 2.1 LED 2.2 LED 2.2 LED 2.2RED BLUE GREEN RED BLUE GREENMSB(7) MSB(7) MSB(7) MSB(7) MSB(7) MSB(7)
  9. 9. COMMUNICATION• Inter-FPGA-Communication Module – Modified I2C Bus Interface • Two Wire Interface: Clock Signal and Data Signal • Duplex with Single Master • Connects 255 FPGAs – Required to relay images to FPGAs PC UART FPGA1 I2C FPGA2 FPGA 4 FPGA 3
  10. 10. Modified I2C : Timing• Data transfer is initiated when data line is pulled low while Clock stays high.• The master puts new data on the falling edge• The slave receives data on the rising edge• Data Transfer is stopped by pulling the data line high while clock is constantly high
  11. 11. Modified I2C : Message Protocol Device Command Start Signal DATA Stop Signal Address Word• Clock=‘1’ • 1-255 • Bulk Transfer • 576 Byte • Clock=‘1’• Data 0-1 • Single • 1 Byte • Data 1-0 Transfer • Address
  12. 12. LOGIC & CONTROLRAM Read • PWM ControlRAM Write • UART Control • I2C
  13. 13. PWM Generation• Example – Generate 8 bit PWM • 0 means 0% duty cycle • 255 means 100% duty Cycle – Let us try and find PWM level of 128 • 128=010000000 • Hold the value of output= – bit 0 for 1 clock cycle – bit 1 for 2 clock cycle – bit 2 for 4 clock cycle – bit 3 for 8 clock cycle – bit 4 for 16 clock cycle – bit 5 for 32 clock cycle – bit 6 for 64 clock cycle – bit 7 for 128 clock cycle – Total clock cycles=255 • 128 would mean that we have 128 clock cycles for which the output is one and 127 cycles for which the output is 0 hence 50% duty cycle as required
  14. 14. PWM Generation + Read ControlLED 1.1 LED 1.1 LED 1.1 LED 1.2 LED 1.2 LED 1.2RED BLUE GREEN RED BLUE GREENLSB(0) LSB(0) LSB(0) LSB(0) LSB(0) LSB(0)LED 1.1 LED 1.1 LED 1.1 LED 1.2 LED 1.2 LED 1.2RED BLUE GREEN RED BLUE GREENMSB(7) MSB(7) MSB(7) MSB(7) MSB(7) MSB(7) LED LED 1.1 1.2LED 2.1 LED 2.1 LED 2.1 LED 2.2 LED 2.2 LED 2.2RED BLUE GREEN RED BLUE GREEN LED LEDLSB(0) LSB(0) LSB(0) LSB(0) LSB(0) LSB(0) 2.1 2.2LED 2.1 LED 2.1 LED 2.1 LED 2.2 LED 2.2 LED 2.2RED BLUE GREEN RED BLUE GREENMSB(7) MSB(7) MSB(7) MSB(7) MSB(7) MSB(7)
  15. 15. Write Control 9 Byte RAMUART Buffer 192X72
  16. 16. SOFTWARE DESIGN• Matlab • TERMINAL v1.9b • Serial Data Transfer • 115200bps Video Data Decoding Transfer Utilities GUI• Pymedia • Python
  17. 17. Video Decoding• Any Image is a 3D array – Image(; ;1) represents RED – Image(; ;2) represents GREEN – Image(; ;3) represents BLUE• Any Video is a 4D array with time as the 4th dimension – Video(; ; ; N) where N represents the Nth frame
  18. 18. Our Mechanism1 •Convert JPEG image to RGB Array2 •Covert Array values to Binary Value3 •Convert to RAM compatible format4 •Generate a text file5 •Transfer via Terminal at 115200bps
  19. 19. Our Mechanism 255 255 0 0 170 170 255 255 0 0 170 17011111111 11111111 00000000 00000000 10101010 1010101011111111 11111111 00000000 00000000 10101010 10101010 1 0 0 1 0 0 1 0 1 1 0 ASCII VALUE for 10010010
  20. 20. Python in Progress• Why Python? – Open Source and Free ware – Work: • Image Decoding • Data Transfer : PyUSB, PySerial • GUI Development: PyCard
  21. 21. LED Board• consists of matrix of RGB LEDs size – 24 X 24 RGB LEDs.FPGA Board• consists of power supply regulators, RS-232 Port, JTAG, 7-segment displays, buttons, and FPGA ( Spartan3AN-50K).
  22. 22. LED Board• Separation between RGB LEDs – 20mm.• Separate LEDs for each color because of cost factors• Board subdivided into 16 parts with 6 X 6 RGB LEDs• Board Specifications – Clearance – 10 mil – Width – 12mil – Drill size – 24 mil
  23. 23. LED Board• Multiplexing of LED Columns using High Power PMOS (FDC604P).• Power Supply - 5 V (Blue LEDs require 3.3 V)• NPN with every PMOS Since FPGA only Provides 3.3 V.
  24. 24. LED Board Layout
  25. 25. FPGA Board• Spartan3AN - XC3S50AN. – Package - Thin QFP with 144 pins (TQ144).• Power Supplies – VCCINT - 1.2V – VCCAUX – 3.3V• CLKIN – 20 MHz• Four Multiplexed - 7 Segment displays• RS- 232 Port along with MAX232 IC for signal interface with FPGA.• Four Buttons and three DIL switches as configuration selector.
  26. 26. FPGA Board Layout
  27. 27. Specifications of FPGA used• Device Name - XC3S50AN• System Gates -50K• Equivalent Logic Cells - 1,584• CLBs - 176• Slices - 704• Distributed RAM Bits – 11k• Block RAM Bits - 54K• Maximum User I/O -108

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