This document summarizes a technique called Dynamic Voltage and Threshold Scaling (DVTS) that can reduce power consumption in digital CMOS circuits. DVTS dynamically controls both the supply voltage (Vdd) and threshold voltage (Vth) to minimize total power based on workload conditions. It works by lowering Vdd to reduce dynamic power during low activity, and increasing Vth via body bias to reduce leakage power. Compared to dynamic voltage scaling (DVS) alone, DVTS provides additional leakage power savings. Simulation results show that DVTS controllers can effectively optimize Vdd and Vbs to minimize average power in basic logic gates and that the approach may be extended to larger circuits.
AVTS Approach To Digital CMOS Circuits For Diminishing Complete Power Expendi...IJRES Journal
Power utilization of present Digital integrated circuits escalating with each generation which becomes a serious design issue. This paper wished-for a generalized power tracking algorithm that reduces power directly by forceful control of supply voltage and body bias. The AVTS algorithm-(Active Voltage and Threshold Scaling algorithm) save the outflow power for the period of Active mode of the circuit. Total Active power can be diminishing by adjusting Vdd and Vth based on circuit operating environment such as hotness, operation load, and circuit structural design. The power saving method of AVTS is similar to that of the Active Voltage Scaling (AVS) scheme, which adaptively changes the supply voltage depending on the current function of the system. For the circuits, and it is possible to trade off active and sub threshold outflow power by balancing between Vdd and Vth to maintain performance
An adaptive protection scheme to prevent recloser-fuse miscoordination in dis...iosrjce
IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Photo Voltaic Cell Integrated DVR for Power Quality ImprovementIJMTST Journal
Grid integration of distributed energy resources (DERs) is increasing rapidly. Integration of various types of energy storage technologies like batteries, ultra capacitors (UCAPs), superconducting magnets and flywheels to support intermittent DERs, such as solar and wind, in order to improve their reliability is becoming necessary. Of all the energy storage technologies UCAPs have low energy density, high power density and fast charge/discharge characteristics. They also have more charge/discharge cycles and higher terminal voltage per module when compared to batteries. All these characteristics make UCAPs ideal choice for providing support to events on the distribution grid which require high power for short spans of time. UCAPs have traditionally been limited to regenerative braking and wind power smoothing applications. The major contribution of this dissertation is in integrating UCAPs for a broader range of applications like active/reactive power support, renewable intermittency smoothing, voltage sag/swell compensation and power quality conditioning to the distribution grid. Renewable intermittency smoothing is an application which requires bi-directional transfer of power from the grid to the UCAPs and vice-versa by charging and discharging the UCAPs. This application requires high active power support in the 10s-3min time scale which can be achieved by integrating UCAPs through a shunt active power filter (APF) which can also be used to provide active/reactive power support. Temporary voltage sag/swell compensation is another application which requires high active power support in the 3s-1min time scale which can be provided integrating UCAPs into the grid through series dynamic voltage restorer (DVR). All the above functionalities can also be provided by integrating the UCAPs into a power conditioner topology.
As a consequence of sensitive, diverse and complex loads in today's distribution networks, improving power quality in distribution systems has attracted great attention. Power quality issues involve voltage sags, transient interrupts and other distortions in sinusoidal waveforms. Enormous methods have been proposed for power quality modification. One of the methods by which power quality problems might be addressed is to apply power electronic devices in the form of custom power devices. One of such devices is Dynamic Voltage Restorer (DVR) which is connected in series to distribution networks. At the same time, through injection of voltage to the network it is able to control voltage amplitude and phase. It is adopted lend to compensate for voltage sags through injecting series and synchronous three phase voltage. Consisted of three single phase inverters and a DC bus, it can protect susceptible loads against various types of voltage sags as well as other disturbances in the power supply. Moreover, it is capable of generating and absorbing active and reactive power. Therefore, in this paper, different structures of DVR have been investigated and eventually proposed a new structure for DVR based on Γ-Source asymmetric inverter. With the proposed structure, severe voltage sags can be retrieved 80- 90 percent. The simulation results that obtained by using MATLAB/Simulink indicate the properly functioning of proposed structure.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
Events that may test transmission grid resilience are varied. Some involve minimal
permanent damage and can be recovered from relatively quickly. Other events may require
much longer periods of time to recover where extensive damage has occurred. Some events
are fast to develop, while other may provide an opportunity to prepare (weather) or not
(willful attack).
AVTS Approach To Digital CMOS Circuits For Diminishing Complete Power Expendi...IJRES Journal
Power utilization of present Digital integrated circuits escalating with each generation which becomes a serious design issue. This paper wished-for a generalized power tracking algorithm that reduces power directly by forceful control of supply voltage and body bias. The AVTS algorithm-(Active Voltage and Threshold Scaling algorithm) save the outflow power for the period of Active mode of the circuit. Total Active power can be diminishing by adjusting Vdd and Vth based on circuit operating environment such as hotness, operation load, and circuit structural design. The power saving method of AVTS is similar to that of the Active Voltage Scaling (AVS) scheme, which adaptively changes the supply voltage depending on the current function of the system. For the circuits, and it is possible to trade off active and sub threshold outflow power by balancing between Vdd and Vth to maintain performance
An adaptive protection scheme to prevent recloser-fuse miscoordination in dis...iosrjce
IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Photo Voltaic Cell Integrated DVR for Power Quality ImprovementIJMTST Journal
Grid integration of distributed energy resources (DERs) is increasing rapidly. Integration of various types of energy storage technologies like batteries, ultra capacitors (UCAPs), superconducting magnets and flywheels to support intermittent DERs, such as solar and wind, in order to improve their reliability is becoming necessary. Of all the energy storage technologies UCAPs have low energy density, high power density and fast charge/discharge characteristics. They also have more charge/discharge cycles and higher terminal voltage per module when compared to batteries. All these characteristics make UCAPs ideal choice for providing support to events on the distribution grid which require high power for short spans of time. UCAPs have traditionally been limited to regenerative braking and wind power smoothing applications. The major contribution of this dissertation is in integrating UCAPs for a broader range of applications like active/reactive power support, renewable intermittency smoothing, voltage sag/swell compensation and power quality conditioning to the distribution grid. Renewable intermittency smoothing is an application which requires bi-directional transfer of power from the grid to the UCAPs and vice-versa by charging and discharging the UCAPs. This application requires high active power support in the 10s-3min time scale which can be achieved by integrating UCAPs through a shunt active power filter (APF) which can also be used to provide active/reactive power support. Temporary voltage sag/swell compensation is another application which requires high active power support in the 3s-1min time scale which can be provided integrating UCAPs into the grid through series dynamic voltage restorer (DVR). All the above functionalities can also be provided by integrating the UCAPs into a power conditioner topology.
As a consequence of sensitive, diverse and complex loads in today's distribution networks, improving power quality in distribution systems has attracted great attention. Power quality issues involve voltage sags, transient interrupts and other distortions in sinusoidal waveforms. Enormous methods have been proposed for power quality modification. One of the methods by which power quality problems might be addressed is to apply power electronic devices in the form of custom power devices. One of such devices is Dynamic Voltage Restorer (DVR) which is connected in series to distribution networks. At the same time, through injection of voltage to the network it is able to control voltage amplitude and phase. It is adopted lend to compensate for voltage sags through injecting series and synchronous three phase voltage. Consisted of three single phase inverters and a DC bus, it can protect susceptible loads against various types of voltage sags as well as other disturbances in the power supply. Moreover, it is capable of generating and absorbing active and reactive power. Therefore, in this paper, different structures of DVR have been investigated and eventually proposed a new structure for DVR based on Γ-Source asymmetric inverter. With the proposed structure, severe voltage sags can be retrieved 80- 90 percent. The simulation results that obtained by using MATLAB/Simulink indicate the properly functioning of proposed structure.
Research Inventy : International Journal of Engineering and Scienceresearchinventy
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
Events that may test transmission grid resilience are varied. Some involve minimal
permanent damage and can be recovered from relatively quickly. Other events may require
much longer periods of time to recover where extensive damage has occurred. Some events
are fast to develop, while other may provide an opportunity to prepare (weather) or not
(willful attack).
Sag mitigation in distribution system by using Dynamic voltage Restorer (DVR)IJERA Editor
Power quality is most important concern in the current age. It’s now a day’s necessary with the refined devices, where performance is very perceptive to the quality of power supply. Power quality crisis is an incidence manifest as a typical voltage, current or frequency that results in a failure of end use equipments. One of the major crises dealt here is the power sag. Perceptive industrial loads and distribution networks suffer from different types of service interruptions and outages which results in a major financial loss. To improve the power quality, custom power-devices are used. The device considered in this work is Dynamic Voltage Restorer. This paper shows modelling, analysis and simulation of a DVR test systems using MATLAB.
I have considered single line to ground fault for linear load. The role of DVR is to “compensate load voltage” is examined during the different fault conditions like voltage sag, single phase to ground faults.
Design and Mitigation Techniques of MV Capacitor Bank Switching Transients on...ijtsrd
This paper presents the techniques to mitigate transients caused by capacitor switching in the distribution system. It includes the theory of capacitive switching transients with different methods of mitigation. The paper uses MATLAB SIMULINK software package to simulate the specific mitigation devices. The mathematical calculations of different parameters such as transient voltages, current, and frequencies for each device are compared with obtained value from the simulations of each case study. Poonam Bhati | Mukesh Kumar Lodha ""Design and Mitigation Techniques of MV- Capacitor Bank Switching Transients on 132 KV Substation"" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-4 , June 2019, URL: https://www.ijtsrd.com/papers/ijtsrd25093.pdf
Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/25093/design-and-mitigation-techniques-of-mv--capacitor-bank-switching-transients-on-132-kv-substation/poonam-bhati
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STATE OF THE ART: DYNAMIC VOLTAGE RESTORER FOR POWER QUALITY IMPROVEMENTecij
Improved and controlled power quality is one of the essential and fundamental need in any power driven industry for optimum utilization of resources. However critical problems in power quality have been recognized such as sags, swells, harmonic distortions and other interruptions. Out of these sags and swells
are predominantly found and have severe impact on the electrical devices or electrical machines and therefore needs to be compensated at an earliest to ensure any mal-operation or failure. To crack these problems custom power devices are used like unified power-quality conditioner (UPQC), distributionSTATCOM (DSTATCOM) and dynamic voltage restorer (DVR). The DVR is a one of the custom power device used for the compensation of voltage sag and swell with an advantage of active/reactive power control. A major volume of literature reported in past several years on different configurations of DVR and different control technique used in it. In context of this a detailed review on DVR has been presented with different possible power circuit topologies and control techniques available to reconcile these power quality issues. This review article will contribute in better selection of control strategy and power circuit for optimum performance of DVR for a particular requirement. Also it presents a very helpful investigation for the researcher in this field.
Modeling Analysis& Solution of Power Quality Problems Using DVR & DSTATCOMijsrd.com
A Power quality problem is an occurrence manifested as a nonstandard voltage, current or frequency that results in a failure or a disoperation of end use equipment. Utility distribution networks, sensitive industrial loads, and critical commercial operations all suffer from various types of outages and service interruptions which can cost significant financial loss per incident based on process down-time, lost production, idle work forces, and other factors. With the restructuring of Power Systems and with shifting trend towards Distributed and Dispersed Generation, the issue of Power Quality is going to take newer dimensions. The aim therefore, in this work, is to identify the prominent concerns in the area and thereby to recommend measures that can enhance the quality of the power, keeping in mind their economic viability and technical repercussions. In this paper electromagnetic transient studies are presented for the following two custom power controllers: the distribution static compensator (DSTATCOM), and the dynamic voltage restorer (DVR). Comprehensive results are presented to assess the performance of each device as a potential custom power solution.
Contemporary Control of DG Integrated DVR for Sag, Swell and Harmonic Mitigat...IJECEIAES
This paper presents a novel control strategy to control DG integrated DVR (dynamic voltage restorer) for mitigation voltage quality problems. Power quality is the most concerning areas in power engineering and voltage quality is of prime focus. Voltage sag, voltage swell and harmonics in voltage causes deterioration in quality of voltage delivered to load. A minor disturbance in voltage profile can degrade the performance of load. Dynamic voltage restorer is a quick responsive custom power device for voltage quality improvement. Photovoltaic (PV) system is considered as DG and output voltage of PV system is boosted with a boost converter to support voltage source converter of DVR. DG integrated DVR with novel control strategy for mitigation of voltage sag, swell and voltage harmonic is presented in this paper. The power system model with DG integrated DVR is developed and results are obtained using MATLAB/SIMULINK. Results are discussed during pre and post sag/swell condition with compensation and THD in voltage is maintained within nominal values.
Sag mitigation in distribution system by using Dynamic voltage Restorer (DVR)IJERA Editor
Power quality is most important concern in the current age. It’s now a day’s necessary with the refined devices, where performance is very perceptive to the quality of power supply. Power quality crisis is an incidence manifest as a typical voltage, current or frequency that results in a failure of end use equipments. One of the major crises dealt here is the power sag. Perceptive industrial loads and distribution networks suffer from different types of service interruptions and outages which results in a major financial loss. To improve the power quality, custom power-devices are used. The device considered in this work is Dynamic Voltage Restorer. This paper shows modelling, analysis and simulation of a DVR test systems using MATLAB.
I have considered single line to ground fault for linear load. The role of DVR is to “compensate load voltage” is examined during the different fault conditions like voltage sag, single phase to ground faults.
Design and Mitigation Techniques of MV Capacitor Bank Switching Transients on...ijtsrd
This paper presents the techniques to mitigate transients caused by capacitor switching in the distribution system. It includes the theory of capacitive switching transients with different methods of mitigation. The paper uses MATLAB SIMULINK software package to simulate the specific mitigation devices. The mathematical calculations of different parameters such as transient voltages, current, and frequencies for each device are compared with obtained value from the simulations of each case study. Poonam Bhati | Mukesh Kumar Lodha ""Design and Mitigation Techniques of MV- Capacitor Bank Switching Transients on 132 KV Substation"" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-4 , June 2019, URL: https://www.ijtsrd.com/papers/ijtsrd25093.pdf
Paper URL: https://www.ijtsrd.com/engineering/electrical-engineering/25093/design-and-mitigation-techniques-of-mv--capacitor-bank-switching-transients-on-132-kv-substation/poonam-bhati
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STATE OF THE ART: DYNAMIC VOLTAGE RESTORER FOR POWER QUALITY IMPROVEMENTecij
Improved and controlled power quality is one of the essential and fundamental need in any power driven industry for optimum utilization of resources. However critical problems in power quality have been recognized such as sags, swells, harmonic distortions and other interruptions. Out of these sags and swells
are predominantly found and have severe impact on the electrical devices or electrical machines and therefore needs to be compensated at an earliest to ensure any mal-operation or failure. To crack these problems custom power devices are used like unified power-quality conditioner (UPQC), distributionSTATCOM (DSTATCOM) and dynamic voltage restorer (DVR). The DVR is a one of the custom power device used for the compensation of voltage sag and swell with an advantage of active/reactive power control. A major volume of literature reported in past several years on different configurations of DVR and different control technique used in it. In context of this a detailed review on DVR has been presented with different possible power circuit topologies and control techniques available to reconcile these power quality issues. This review article will contribute in better selection of control strategy and power circuit for optimum performance of DVR for a particular requirement. Also it presents a very helpful investigation for the researcher in this field.
Modeling Analysis& Solution of Power Quality Problems Using DVR & DSTATCOMijsrd.com
A Power quality problem is an occurrence manifested as a nonstandard voltage, current or frequency that results in a failure or a disoperation of end use equipment. Utility distribution networks, sensitive industrial loads, and critical commercial operations all suffer from various types of outages and service interruptions which can cost significant financial loss per incident based on process down-time, lost production, idle work forces, and other factors. With the restructuring of Power Systems and with shifting trend towards Distributed and Dispersed Generation, the issue of Power Quality is going to take newer dimensions. The aim therefore, in this work, is to identify the prominent concerns in the area and thereby to recommend measures that can enhance the quality of the power, keeping in mind their economic viability and technical repercussions. In this paper electromagnetic transient studies are presented for the following two custom power controllers: the distribution static compensator (DSTATCOM), and the dynamic voltage restorer (DVR). Comprehensive results are presented to assess the performance of each device as a potential custom power solution.
Contemporary Control of DG Integrated DVR for Sag, Swell and Harmonic Mitigat...IJECEIAES
This paper presents a novel control strategy to control DG integrated DVR (dynamic voltage restorer) for mitigation voltage quality problems. Power quality is the most concerning areas in power engineering and voltage quality is of prime focus. Voltage sag, voltage swell and harmonics in voltage causes deterioration in quality of voltage delivered to load. A minor disturbance in voltage profile can degrade the performance of load. Dynamic voltage restorer is a quick responsive custom power device for voltage quality improvement. Photovoltaic (PV) system is considered as DG and output voltage of PV system is boosted with a boost converter to support voltage source converter of DVR. DG integrated DVR with novel control strategy for mitigation of voltage sag, swell and voltage harmonic is presented in this paper. The power system model with DG integrated DVR is developed and results are obtained using MATLAB/SIMULINK. Results are discussed during pre and post sag/swell condition with compensation and THD in voltage is maintained within nominal values.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Analysis of Total Harmonic Distortion (THD) Level of Distribution Network Usi...IJERA Editor
The modern sensitive, Non-linear and sophisticated load affects the power quality. Dynamic Voltage Restorer (DVR) provides the fast, flexible and efficient solution to improve the power quality for such distribution network [8]. The active power, reactive power, variation of voltage, flicker, harmonics, and electrical behavior of switching operations are the major source of affecting power quality. The intent of this paper is to demonstrate the improvements obtained with DVR in power system network using MATLAB/SIMULINK. In this paper, an overview of the DVR, its functions, configurations, components, control strategies are reviewed. The Simulation results are presented to illustrate the performance of DVR in Total Harmonic Distortion (THD). The results showed clearly the performance of using DVR in improving THD level.
A Review on Optimization Techniques for Power Quality Improvement using DSTAT...ijtsrd
As demand for electricity has risen exponentially, power production and transmission are affected by scarce energy, environmental constraints and other losses. Soft computing methods to fix the sag, swell and disruption of the supply voltage in the distributed device. At present, a broad variety of highly versatile controls that leverage on newly available power electronics components are evolving for custom power applications. Control electronic equipment intended to improve the stability and efficiency of electricity flows in low voltage distribution networks. The control algorithm is used to derive the fundamental weighted value of the active and reactive power components. Using a digital signal processor, DSTATCOM is built and its output as a DSTATCOM is found to be satisfactory for different types of loads. Amit Radhakrishna Parhad | Pramod Kumar Rathore "A Review on Optimization Techniques for Power Quality Improvement using DSTATCOM (Neural Network Approach)" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd42403.pdf Paper URL: https://www.ijtsrd.comengineering/electrical-engineering/42403/a-review-on-optimization-techniques-for-power-quality-improvement-using-dstatcom-neural-network-approach/amit-radhakrishna-parhad
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
Massive Energy Saving Systems and Strategies at Equipment Level in the Highes...IJERA Editor
Reducing operational expenditures (OpEx) have become main concern for almost all communication service
providers in the world. Some practical ideas and techniques implemented in Grameenphone might be very
helpful for others who are fighting to survive or trying to be more profitable or going to provide new services-
3G /LTE/LTE-Aor want to contribute in climate change anywhere in the world. Some challenging techniques
and tactics are discussed here to reduce vast amount of energy consumptions from different equipment used in
the base station, access and transport network for cost reduction.
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
Dual technique of reconfiguration and capacitor placement for distribution sy...IJECEIAES
Radial Distribution System (RDS) suffer from high real power losses and lower bus voltages. Distribution System Reconfiguration (DSR) and Optimal Capacitor Placement (OCP) techniques are ones of the most economic and efficient approaches for loss reduction and voltage profile improvement while satisfy RDS constraints. The advantages of these two approaches can be concentrated using of both techniques together. In this study two techniques are used in different ways. First, the DSR technique is applied individually. Second, the dual technique has been adopted of DSR followed by OCP in order to identify the technique that provides the most effective performance. Three optimization algorithms have been used to obtain the optimal design in individual and dual technique. Two IEEE case studies (33bus, and 69 bus) used to check the effectiveness of proposed approaches. A Direct Backward Forward Sweep Method (DBFSM) has been used in order to calculate the total losses and voltage of each bus. Results show the capability of the proposed dual technique using Modified Biogeography Based Optimization (MBBO) algorithm to find the optimal solution for significant loss reduction and voltage profile enhancement. In addition, comparisons with literature works done to show the superiority of proposed algorithms in both techniques.
Analysis of Power Dissipation & Low Power VLSI Chip DesignEditor IJMTER
Low power requirement has become a principal motto in today’s world of electronics
industries. Power dissipation has becoming an important consideration as performance and area for
VLSI Chip design. With reducing the chip size, reduced power consumption and power management
on chip are the key challenges due to increased complexity. Low power chip requirement in the
VLSI industry is main considerable field due to the reduction of chip dimension day by day and
environmental factors. For many designs, optimization of power is important as timing due to the
need to reduce package cost and extended battery life. This paper present various techniques to
reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power
Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level
Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors,
Dynamic Threshold MOS, Short Circuit Power Suppression.
Multi-objective Pareto front and particle swarm optimization algorithms for p...IJECEIAES
The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (V thV DD ) which showing satisfactory findings.
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
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M01052109115
1. IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE)
e-ISSN: 2278-1676,p-ISSN: 2320-3331, Volume 10, Issue 5 Ver. II (Sep – Oct. 2015), PP 109-115
www.iosrjournals.org
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 109 | Page
Reduce Power Consumption for Digital Cmos Circuits Using Dvts
Algoritham
Dr C.Rajesh kumar
Professor Jeppiaar Institute of Technology,Chennai
Abstract: The Power consumption of large scale integrated circuits increasing with each generation which
becomes a serious design issue. This paper proposed a generalized power tracking algorithm that reduces
power directly by dynamic control of supply voltage and body bias. The DVTS algorithm-(Dynamic Voltage and
threshold scaling algorithm) save the leakage power during active mode of the circuit. Total active power can
be minimized by dynamically adjusting Vdd and Vth based on circuit operating conditions such as temperature,
workload, and circuit architecture. The power saving method of DVTS is similar to that of the Dynamic VDD
Scaling (DVS) scheme, which adaptively changes the supply voltage depending on the current workload of the
system. For a digital circuit, it is possible to trade off dynamic and sub threshold leakage power by balancing
between Vdd and Vth to maintain performance.
Key words: dynamic voltage and threshold scaling(DVTS), leakage current control, low power, power ptimum
point, sleep transistor, variable body bias, variable supply voltage.
I. Introduction
Low power has emerged as a principal theme in today’s electronics industry. The need for low power
has caused a major paradigm shift where power dissipation has become as important a consideration as
performance and area. In the past, the major concerns of the VLSI designer were area, performance, cost and
reliability; power consideration was mostly of only secondary importance. In recent years, however, this has
begun to change and, increasingly, power is being given comparable weight to area and speed considerations.
Several factors have contributed to this trend. Perhaps the primary driving factor has been the
remarkable success and growth of the class of personal computing devices (portable desktops, audio- and video-
based multimedia products) and wireless communications systems (personal digital assistants and personal
communicators) which demand high-speed computation and complex functionality with low power
consumption.
Power dissipation has become an important objective in the design of digital circuits. There has been
intense research over the past two decades on various aspects of compilation and synthesis for low power. Many
architectural optimizations like re-configurable architectures, custom ASIC approaches, programmable multi-
cores, etc. have been explored. Micro-architectural techniques like parallelism and pipelining, power and clock
gating have become common place now. Circuit techniques for low voltage operation, standby current
reduction, optimal gate sizing have also been explored and are available for use by a designer. Most of these
optimization techniques are static techniques which are applied during design time. In the recent past, dynamic
power management techniques have emerged, where the power consumption is continuously adjusted during
run time of the system.
Traditionally, Dynamic power management (DPM) is employed at operating system level to adjust the
supply voltage for each power state. The supply voltage is conservatively margined to account for process and
temperature variations. These voltage margin increases with technology scaling due to larger process variations,
rendering DPM less efficient. On the other hand, the hardware approach like dynamic voltage scaling (DVS)
allows voltage to be scaled such that the actual delay of the chip instead of worst case delay meets the target
performance. This enables more power savings as minimum possible voltage for target performance can be
attained. In DVS the supply voltage is adjusted to meet the target delay using an on-chip delay monitor in a
hardware feedback loop. Performance degradation is a direct consequence of supply voltage reduction. In order
to maintain the required throughout, dynamic voltage scaling (DVS) systems are used to adjust the supply
voltage according to throughput requirements. Though DVS very well manages the dynamic switching power,
with shrinking feature size the static (leakage) power has increased exponentially which it cannot control.
Particularly, at low activity levels, leakage power is dominant.
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of
the circuit. Dynamic voltage and threshold scaling (DVTS) manages both dynamic and leakage powers by
adjusting supply voltage and body bias voltage. The power saving strategy of DVTS is similar to that of the
Dynamic VDD Scaling (DVS) scheme, which adaptively changes the supply voltage depending on the current
workload of the system. Instead of adjusting the supply voltage, DVTS controls the threshold voltage by means
2. Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 110 | Page
of body bias control, in order to reduce the leakage power. The power saving potential of DVTS and its impact
on dynamic and leakage power is applied to future technologies.
II. Dynamic Voltage And Thershold Scaling (Dvts):
Dynamic voltage and threshold scaling (DVTS) manages both dynamic and leakage powers by
adjusting supply voltage and body bias voltage In digital circuits designed below 0.1 m, total power at any given
performance can be optimized by DVTS. DVTS has been successfully proven on silicon for low power high
speed applications. The optimum power point varies strongly with activity and temperature.DVTS offers
considerable power savings compared to DVS when leakage power is a large fraction of total power. The power
savings increase with increasing logic depth. The moderate performance application-specific integrated circuit
(ASIC) with long logic depth at low activity and/or high temperatures gain the most with DVTS.
2.1 Overview Of Dvts:
Dynamic VTH Scaling (DVTS) scheme for active leakage power reduction. Whenever there is a slack
during computation, the VTH is adaptively changed to a higher value via changing the body bias voltage (VBB).
This will deliver just enough amount of throughput required for the current workload. In order to
examine the effectiveness of DVTS, comparisons between DVS and DVTS for current (0.25μm) and future
(0.07μm) process generations are performed. A careful investigation on the advantages and disadvantages of
DVTS over DVS is also made.
A DVTS hardware that has a feedback loop consisting of a voltage controlled oscillator (VCO), charge
pumps a feedback controller is proposed. The clock frequency of the system for a certain workload is
determined by the operating system in run-time. The DVTS hardware tracks the optimal VTH for the given
clock frequency by dynamically adjusting the VBB.
Figure 2.1 Dynamic VTH scaling by adaptively changing the body bias
Fig.2.1 shows how the DVTS scheme adaptively controls the body bias to change the VTH. For a time
period when the workload is less than the maximum, the operating system will recommend a lower clock
frequency to the hardware. Then the DVTS hardware will increase the PMOS body bias and decrease the
NMOS body bias to raise the VTH and reduce power dissipation. In cases when there is no workload at all, the
VTH can be increased as much as the upper limit of VBB, to significantly save the standby leakage power.
Reducing the clock frequency will proportionally reduce the total power. However, simply reducing the
clock rate does not affect the energy consumed per operation. Whereas by scaling the supply voltage together
with the frequency, we can gain significant power savings. This is because the dynamic power dominates the
total power. Scaling the threshold voltage instead of scaling the supply voltage saves mostly the leakage power.
For 0.25μm technology where the leakage power is a minute portion of the total power, DVTS is less efficient
than DVS in saving total power.
2.2 Modules Of Dvts System:
Vdd Controller:
Vdd is the power supply to the digital circuit. Vdd will be scaled according to power consumption and time
delay Maximum time delay will be set and between in that limits Vdd will be scaled.
If Vdd goes below the minimum Vdd value Vdd value will be increased.
Vbs Controller:
Vbs is the voltage between source and substrate. Vbs will effect threshold voltage .Vbs of the digital circuit
will be varied to decrease the threshold voltage.
In DVS only Vdd will be scaled to decrease total power consumption . In dvts approach both Vdd and Vbs
3. Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 111 | Page
will be scaled to decrease total power consumption.
2.3 Dvts Scheme:
Dynamic VTH Scaling (DVTS) scheme for active leakage power reduction. Whenever there is a slack
during computation, the VTH is adaptively changed to a higher value via changing the body bias voltage (VBB).
This will deliver just enough amount of throughput required for the current workload. In order to examine the
effectiveness of DVTS, comparisons between DVS and DVTS for current (0.25μm) and future (0.07μm) process
generations are performed.
A careful investigation on the advantages and disadvantages of DVTS over DVS is also made. A DVTS
hardware that has a feedback loop consisting of a voltage controlled oscillator (VCO), charge pumps a feedback
controller is proposed. The clock frequency of the system for a certain workload is determined by the operating
system in run-time. The DVTS hardware tracks the optimal VTH for the given clock frequency by dynamically
adjusting the VBB.
III. Dvts Controller:
Fig.3.1 shows block diagram of close loop DVTS system. DVTS controller implements the proposed
DVTS algorithm and controls the supply voltage regulator and well bias charge pump. Control signal generator
(CSG) generates control signals for power monitor when START signal is asserted. The proposed DVTS system
is suited for load circuits where the rate of change in activity is gradual.
Fig.3.1 Design Implementation Block Diagram
DVTS controller implements the proposed. DVTS algorithm and controls the supply voltage regulator
and well bias charge pump. The drain of sleep transistor acts as a virtual ground node for the load circuit. The
power monitor processes virtual ground voltage to generate a 2 bit output that gives information on total power
consumed by the load. Control signal generator (CSG) generates control signals for power monitor when
START signal is asserted. The delay monitor measures whether performance of load circuit meets the target
performance within tolerance limit. Delay monitor is implemented with a critical path replica circuit. The
proposed DVTS system is suited for load circuits where the rate of change in activity is gradual. The maximum
rate of change of activity that can be supported is discussed.
3.2 Dvts Algorithm:
Fig.3.2 shows the flow chart of the proposed DVTS algorithm. The algorithm first sets the supply
voltage to meet target performance, then adjust well potential to achieve minimum power. NWell bias and P
Well bias are always tuned by same amount and hence DVTS control loop is essentially a 2-D control loop. To
avoid oscillations, loop and loop are decoupled by tuning them independently. Initially maximum supply
voltages and maximum forward bias are applied and the supply voltages are slowly lowered.
At each step, the body bias is reset to maximum forward bias and locks to the target frequency to
ensure that the chip stays functional. Once the minimum power point is detected, the bias values can be held in a
register and the controller turned off.
4. Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 112 | Page
Fig. 3.2 (a) flowchart for automatic Vdd /Vth optimization.
The loop can be reactivated whenever the workload changes, or periodically updated to reflect changes
in temperature or operating conditions. Because the ASB loop does not have to be constantly running, the
overhead power consumption, which is already amortized across the whole chip, can be reduced even further.
This ASB control loop is completely self-contained and should lock to the true minimum power configuration
taking into account all possible current paths. This minimum will result in the physically lowest power
consumption achievable by tweaking both and subject to the constraint that the chips satisfy a target frequency.
Even for technologies where the theoretical limit is not yet achievable using body biasing techniques or in cases
where excessive forward bias at low degrades performance, it is still possible to use this architecture to find the
minimum physical power condition. The threshold voltage can be controlled by changing the body bias of the
transistors and is called the adaptive body bias (ABB) technique. For fast silicon, reverse body bias is applied to
increase threshold and reduce leakage, while for slow silicon, forward body bias is applied to reduce threshold
and improve performance. Here the body bias adjustment is done sparingly as needed based on the chip’s
process condition, and is not a continuous variable
like the supply voltage.
However the point of minimum power depends on the ratio of dynamic to leakage power, with the
former modulated by the activity factor. For media applications, the activity factor can vary a lot across different
applications and hence, the optimal settings for threshold and supply also vary
Analogous to table based DVS, a table based DVTS scheme has been proposed where for different
activity factors, the corresponding supply and body bias values are stored in the look up table. The activity
factors are estimated for different applications off-line. During run-time, based on the application being run, the
appropriate activity factor is used to consult the look up table to obtain the settings for supply and body bias,
which will minimize power. Adaptive voltage and threshold scaling aims to arrive at the optimal voltage and
threshold values at run time, by not only adapting to the process and temperature like in AVS, but also to the
dynamically varying activity conditions.
IV. Advantages Of Dvts Over Dvs:
No voltage level converters:
DVS or multiple VDD systems require a voltage level shifter whenever a low VDD signal is driving a
high VDD receiver. Although the conventional level converters prevent the static power consumption, the
dynamic power consumption is large enough to cancel out the power savings gained from supply voltage
scaling. Since DVTS systems use the same supply voltage throughout the chip, no voltage level converters are
required.
5. Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 113 | Page
Simple hardware:
Charge pumps are a simple solution for boosting voltages. No external inductors are needed and power
consumption is very low compared to buck converters, which are used for DVS systems. Charge pumps are used
for our DVTS system to generate the body bias voltages
Less power loss charging/discharging internal nodes:
Transition energy wasted charging/discharging the VDD ground capacitance is the power overhead of
the DVS scheme. For low-to-high and high-to-low transition of supply voltage, current is extracted or placed
back to the power supply. Even though there is no computation during this cycle, transition energy is consumed.
Since the supply voltage is fixed for DVTS, it has less transition energy loss while charging and discharging the
internal nodes.
Improvement in noise immunity:
Signal integrity has become an important issue for deep sub micron devices as crosstalk noise becomes
considerable. Increasing VTH for low workload periods in DVTS will help improve noise immunity, especially
for noise-susceptible circuits such as domino logic and pulsed flip-flops.
4.2 Results And Discussion:
To mitigate the active leakage problem, a Dynamic VTH Scaling (DVTS) scheme is presented. DVTS
algorithm that can be studied and implemented for the design of VDD controller. VDD will be scaled and
controlled according to the limits for the circuit. Power reduction technique can be applied to basic cmos circuits
and the results for average power are analyzed. Ex.Inveter, NAND, NOR. This idea can be extended to larger
circuits in future.
4.2.1 Vdd &Vbs Controller:
Fig 4.1 VDD controller Graph results
6. Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 114 | Page
Fig 4.2 VBS controller Graph results
Fig 4.3 DVTS controller Graph results
7. Reduce Power Consumption for Digital Cmos Circuits Using Dvts Algoritham
DOI: 10.9790/1676-1052109115 www.iosrjournals.org 115 | Page
V. Conclusion
A DVTS algorithm that can locate with varying activity is studied under simulation framework and
validated with a test chip. Timing overhead of DVTS system and size of load circuit are analyzed as they limit
the application of DVTS. The tracking performance of the algorithm can be improved by reducing the timing
overhead. It can be inferred that for technology node with larger leakage currents, DVTS is more beneficial over
DVS.
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