This document discusses analog multipliers and phase locked loops (PLL). It describes various analog multiplier circuits including the emitter coupled transistor pair, Gilbert multiplier cell, and variable transconductance technique. It also covers the basic principles of PLLs, including applications of PLL ICs for frequency multiplication, division, translation, and FM demodulation. Key components of PLLs like the voltage controlled oscillator and phase detector are analyzed.
UNIT - III
FETs and Digital Circuits: FETs: JFET, V-I characteristics, MOSFET, low frequency CS and CD amplifiers, CS and CD amplifiers.
Digital Circuits: Digital (binary) operations of a system, OR gate, AND gate, NOT, EXCLUSIVE OR gate, De Morgan Laws, NAND and NOR DTL gates, modified DTL gates, HTL and TTL gates, output stages, RTL and DCTL, CMOS, Comparison of logic families.
This presentation contains the basic information you need to know about operational amplifier.
I have tried to cover all the basic info. If anything is left out or you have any suggestions i will appreciate it.
UNIT - III
FETs and Digital Circuits: FETs: JFET, V-I characteristics, MOSFET, low frequency CS and CD amplifiers, CS and CD amplifiers.
Digital Circuits: Digital (binary) operations of a system, OR gate, AND gate, NOT, EXCLUSIVE OR gate, De Morgan Laws, NAND and NOR DTL gates, modified DTL gates, HTL and TTL gates, output stages, RTL and DCTL, CMOS, Comparison of logic families.
This presentation contains the basic information you need to know about operational amplifier.
I have tried to cover all the basic info. If anything is left out or you have any suggestions i will appreciate it.
The dipole and the monopole are arguably the two most widely used antennas across the UHF, VHF and lower-microwave bands. Arrays of dipoles are commonly used as base-station antennas in land-mobile systems. The monopole and its variations are common in portable equipment, such as cellular telephones, cordless telephones, automobiles, trains, etc. It has attractive features such as simple construction, sufficiently broadband characteristics for voice communication, small dimensions at high frequencies. Alternatives to the monopole antenna for hand-held units is the inverted F and L antennas, the microstrip patch antenna, loop and spiral antennas, and others. The printed inverted F antenna (PIFA) is arguably the
most common antenna design used in modern handheld phones.
(c) Nikolova 2016
Classification of signals and systems as well as their properties are given in the PPT .Examples related to types of signals and systems are also given .
Concept (Block diagram), properties, positive and negative feedback, loop gain, open loop gain, feedback factors; topologies of feedback amplifier; effect of feedback on gain, output impedance, input impedance, sensitivities (qualitative), bandwidth stability; effect of positive feedback: instability and oscillation, condition of oscillation, Barkhausen criteria. Introduction to integrated circuits, operational amplified and its terminal properties; Application of operational amplifier; inverting and non-inverting mode of operation, Adders, Subtractors, Constant-gain multiplier, Voltage follower, Comparator, Integrator, Differentiator
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCOVLSICS Design
In order to keep electronic world properly PLL plays a very important role. Designing of low
phase noise and less jittery PLL in generation of clock signals is an important task. Clock signals
are required for providing reference timing to electrical system and also to ICs. So in this paper
PLL is designed with improved Phase noise and also jitter. Where such types of design is
important when sophisticated timing requirements are needed to provide synchronization and
distribution of clocks like in ADC, DAC, high speed networking, medical imaging systems. The
clock signal’s quality depends upon jitter and phase noise. An ideal clock source has zero phase
noise and jitter but in reality it has some modulated phase noise. This modulated phase noise
spreads the power to the adjacent frequencies, hence produces noise sidebands. The phase noise
is typically frequency domain analysis which is expressed in terms of dBc/Hz measured at offset
frequency with respect to ideal clock frequency. The low phase noise is important factor mainly
in RF and ADC applications. In RF wireless high speed applications, increased PN will leads to
channel to channel interference, attenuates quality of signal. In ADC, increased PN limits the
SNR and data converter’s equivalent no. of bits (ENOB). Jitter is time domain meas
The dipole and the monopole are arguably the two most widely used antennas across the UHF, VHF and lower-microwave bands. Arrays of dipoles are commonly used as base-station antennas in land-mobile systems. The monopole and its variations are common in portable equipment, such as cellular telephones, cordless telephones, automobiles, trains, etc. It has attractive features such as simple construction, sufficiently broadband characteristics for voice communication, small dimensions at high frequencies. Alternatives to the monopole antenna for hand-held units is the inverted F and L antennas, the microstrip patch antenna, loop and spiral antennas, and others. The printed inverted F antenna (PIFA) is arguably the
most common antenna design used in modern handheld phones.
(c) Nikolova 2016
Classification of signals and systems as well as their properties are given in the PPT .Examples related to types of signals and systems are also given .
Concept (Block diagram), properties, positive and negative feedback, loop gain, open loop gain, feedback factors; topologies of feedback amplifier; effect of feedback on gain, output impedance, input impedance, sensitivities (qualitative), bandwidth stability; effect of positive feedback: instability and oscillation, condition of oscillation, Barkhausen criteria. Introduction to integrated circuits, operational amplified and its terminal properties; Application of operational amplifier; inverting and non-inverting mode of operation, Adders, Subtractors, Constant-gain multiplier, Voltage follower, Comparator, Integrator, Differentiator
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCOVLSICS Design
In order to keep electronic world properly PLL plays a very important role. Designing of low
phase noise and less jittery PLL in generation of clock signals is an important task. Clock signals
are required for providing reference timing to electrical system and also to ICs. So in this paper
PLL is designed with improved Phase noise and also jitter. Where such types of design is
important when sophisticated timing requirements are needed to provide synchronization and
distribution of clocks like in ADC, DAC, high speed networking, medical imaging systems. The
clock signal’s quality depends upon jitter and phase noise. An ideal clock source has zero phase
noise and jitter but in reality it has some modulated phase noise. This modulated phase noise
spreads the power to the adjacent frequencies, hence produces noise sidebands. The phase noise
is typically frequency domain analysis which is expressed in terms of dBc/Hz measured at offset
frequency with respect to ideal clock frequency. The low phase noise is important factor mainly
in RF and ADC applications. In RF wireless high speed applications, increased PN will leads to
channel to channel interference, attenuates quality of signal. In ADC, increased PN limits the
SNR and data converter’s equivalent no. of bits (ENOB). Jitter is time domain meas
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGYVLSICS Design
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design
Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology VLSICS Design
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGYVLSICS Design
Power has become one of the most important paradigms of design convergence for multi
gigahertz communication systems such as optical data links, wireless products, microprocessor &
ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core
of a microprocessor, which includes the largest power density on the microprocessor. In an effort to
reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of
dynamic and static power consumption. Lowering the supply voltage, however, also reduces the
performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available
in some application domains, is to replicate the circuit block whose supply voltage is being reduced in
order to maintain the same throughput .This paper introduces a design aspects for low power phase
locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process
technology parameters, which in turn offers high speed performance at low power. The main novelty
related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect
dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit
parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,
translation onto silicon, CAD, practical experience in layout design
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. The use of a Phase Locked Loop enables the receiver to adaptively track and remove frequency/phase offsets. The pll consists of loop filter, VCO and amplifier. The paper describes the designing of this loop filter using CMOS. The use of this element reduces cost drastically and has a good response. An experiment was conducted through this component which provided better result. The main advantage of designing low pass filter by CMOS is that it offers improvements in design simplicity and programmability when compared to op-amp based structures as well as reduced component count. It has high noise immunity and low static power consumption. Hence the overall efficiency increases as well producing the desired effect.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
CMOS ring oscillator delay cell performance: a comparative studyIJECEIAES
A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.
What is PLL and elements of PLL??
What is Analog PLL??
What is Digital PLL??
What are the components of Digital PLL??
Applications of PLL
PLL as 565 IC pin diagram
PLL as Frequency Synthesizer (Frequency Translator)
PLL as Frequency Division
PLL as Frequency Multiplication
PLL as FM Demodulator
In this project an RF detector using tuned LC circuits is
formed for detecting signals in the GHz frequency band
used in mobile phones as the transmission frequency of
mobile phone ranges from 0.9 to 3 GHz.
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...VLSICS Design
A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to
higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
this circuit. The circuit is designed in 0.18 μm CMOS and the simulations for 27-1 pseudo random bit
sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
is 1.1 ps
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Honest Reviews of Tim Han LMA Course Program.pptxtimhan337
Personal development courses are widely available today, with each one promising life-changing outcomes. Tim Han’s Life Mastery Achievers (LMA) Course has drawn a lot of interest. In addition to offering my frank assessment of Success Insider’s LMA Course, this piece examines the course’s effects via a variety of Tim Han LMA course reviews and Success Insider comments.
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
• The Committee on Ways and Means has been investigating several universities since November 15, 2023, when the Committee held a hearing entitled From Ivory Towers to Dark Corners: Investigating the Nexus Between Antisemitism, Tax-Exempt Universities, and Terror Financing. The Committee followed the hearing with letters to those institutions on January 10, 202
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
The French Revolution, which began in 1789, was a period of radical social and political upheaval in France. It marked the decline of absolute monarchies, the rise of secular and democratic republics, and the eventual rise of Napoleon Bonaparte. This revolutionary period is crucial in understanding the transition from feudalism to modernity in Europe.
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Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
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This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
Macroeconomics- Movie Location
This will be used as part of your Personal Professional Portfolio once graded.
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Prepare a presentation or a paper using research, basic comparative analysis, data organization and application of economic information. You will make an informed assessment of an economic climate outside of the United States to accomplish an entertainment industry objective.
Thesis Statement for students diagnonsed withADHD.ppt
LIC UNIT III.pptx
1. UNIT – III
ANALOG MULTIPLIER AND PLL
LINEAR INTEGRATED CIRCUITS
1
KONGUNADU COLLEGE OF ENGINEERING
AND TECHNOLOGY (AUTONOMOUS)
2. ANALOG MULTIPLIER AND PLL
Syllabus
Analog Multiplier using Emitter Coupled Transistor
Pair - Gilbert Multiplier cell – Variable
transconductance technique - Analog multiplier ICs
and their applications – PLL: basic principles,
analysis – Voltage controlled oscillator - Monolithic
PLL IC 565 – Application of PLL: Frequency
Multiplication, Division, Frequency translation, FM
demodulation, FSK demodulator.
2
KONGUNADU COLLEGE OF ENGINEERING
AND TECHNOLOGY (AUTONOMOUS)
3. INTRODUCTION
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AND TECHNOLOGY (AUTONOMOUS)
3
The circuit which has two analog inputs and produces an output
proportional to their product is called as analog multipliers. An analog
multiplier is a device having two input ports and one output port. The
signal at the output is the product of the two input signals.
If both input and output signals are voltages, the transfer characteristic
is the product of the two input voltages divided by a scaling factor K.
Multiplier can be classified as single-quadrant, two quadrant or
four quadrant multipliers depending on the possible polarities of
the input signals.
Single quadrant multipliers allow only positive input signals. Two
quadrant multipliers allows one signal to swing both positive
and negative. In four quadrant multipliers, both input signals
can be negative or positive.
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Basic operations of analog multiplier
5. KONGUNADU COLLEGE OF ENGINEERING
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Various methods available for analog multiplication are
:
(i) Logarithmic summing technique
(ii) Pulse height/width modulation technique
(iii) Variable transconductance technique and
(iv) Gilbert multiplier cell.
6. ANALOG MULTIPLIER USING EMITTER COUPLED TRANSISTOR
PAIR
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6
7. TRANSFER CHARACTERISTICS OF EMITTER COUPLED
TRANSISTOR PAIR
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8. KONGUNADU COLLEGE OF ENGINEERING
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8
The emitter coupled pair, shown in the figure is used to produce
output currents that are related to the differential input voltage
V1. The output currents IC1 and IC2 are given by
where, VT is the thermal voltage and base currents has
been neglected.
The difference between the two output currents is given
by,
9. KONGUNADU COLLEGE OF ENGINEERING
AND TECHNOLOGY (AUTONOMOUS)
9
If the differential input voltage V1 is much less than VT,
then
The current IEE is actually the bias current for the emitter
coupled pair.
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10
Two quadrant analog multiplier
12. GILBERT MULTIPLIER CELL
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12
Due to the variable I-V relationship of BJT, the
variable transconductance Gilbert cell multiplier
architecture, allows for linear operation. It is the most
commonly used bipolar multiplier architecture.
The Gilbert multiplier cell, is a modification of the
emitter-coupled cell, which allows four-quadrant
multiplication.
The Gilbert multiplier cell is the basis for most
integrated-circuit balanced multiplier systems. The
series connection of an emitter coupled pair with two
cross-coupled, emitter coupled pairs produces a
useful transfer characteristic.
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AND TECHNOLOGY (AUTONOMOUS)
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The Gilbert cell consists of two differential amplifier stages
formed by emitter-coupled transistor pairs (Q3, Q4 & Q5,
Q6) whose outputs are connected (currents summed) with
opposite phases.
19. KONGUNADU COLLEGE OF ENGINEERING
AND TECHNOLOGY (AUTONOMOUS)
19
APPLICATIONS OF GILBERT MULTIPLIER CELL
1) Gilbert cell can be used as a small signal precise
four-quadrant multiplier (with the
condition that both inputs are small compared with
VT) (VT=Thermal voltage = 0.025V)
2) Large signal phase detector (with the condition that
both inputs are greater than VT)
3) Modulator in a communications application (with
the condition that, only one input is
small compared with VT while the other input is
greater)
4) Pre-processing circuit in a ADC to reduce the
number of comparators in this architecture.
This circuit is called as folding ADC.
20. VARIABLE TRANSCONDUCTANCE TECHNIQUE
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20
Principle of the variable transconductance multiplier is as
follows: one input variable controls the gain (transconductance)
of an active device. The other input, which is the input of this
device is amplified in proportion to the control input. Then, for a
small range of inputs, the output appears to be proportional to
the product of both inputs.
The most famous multiplier based on this principle is the Gilbert
multiplier. This multiplier can be obtained from a simple
transconductance amplifier, which consists of a differential pair
and a single current mirror.
It uses two linearized transconductance pairs (Q3, Q4 and Q5,
Q6) with bases driven in anti-phase.
The pre distortion for the input signal is achieved by transistors
Q7 and
Q8. The currents passing through the emitters of Q7 and Q8
generate a voltage between the two emitter terminals that is
proportional to the inverse hyperbolic tangent of V1. This
compensates the hyperbolic tangent and produces the
25. PHASE LOCKED LOOP (PLL)
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A phase locked loop (PLL) is one of the fundamental
building blocks of a linear system.
A phase locked loop (PLL) is a closed loop system
designed to lock the output frequency and phase to
the frequency and phase of an input signal.
PLL is available as a single package. ICs 560, 561,
562, 564,565 and 567 are some of the PLL ICs.
This technique of electronic frequency control is used
in satellite communication systems, air borne
navigational systems, FM communication systems
and computers etc.,
26. BASIC PLL OPERATION
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The basic function of the phase
detector is to compare the
phase and frequency of the
incoming signal with the output
of VCO.
If there two signals differ in
frequency and/or phase, an
error signal is generated.
The output signal (error signal)
of the phase detector is a d.c.
voltage and it is given as input
to the low pass filter.
The output of low pass filter
without high frequency noise is
known as error voltage or
control voltage. Then the error
amplifier amplifies the error
voltage and given as input
VCO.
27. Different modes of operation of PLL
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Free running mode
If control voltage is equal to zero, then VCO is in free running
mode and its output frequency is called as center frequency.
Capture mode
The error or control voltage forces the VCO to change its output
frequency in the direction that reduces the differences between
the input frequency and the output frequency of VCO. This
capturing action continues till the output frequency of VCO is
equal to the input signal frequency.
Phase lock mode
Once the two frequencies are same, the circuit is said to be
locked. Phase detector generates a constant d.c. level which is
required to shift to output frequency of VCO from centre
frequency to the input frequency. Once locked, PLL tracks the
frequency changes of the input signal.
28. IMPORTANT DEFINITIONS TO PLL
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Lock Range :
Lock range is defined as the range of frequencies over
which the PLL maintain lock with the incoming signal. It is
also called as tracking range. It is expressed as a
percentage of VCO frequency fo.
Capture Range :
Capture range is defined as the range of frequencies over
which the PLL can acquire lock with an input signal. This
parameter is expressed as a percentage of VCO
frequency fo.
Pull-in Time :
Pull-in time is defined as the total time taken by the PLL to
establish. This depends on the initial phase and frequency
difference between the signals as well as on the overall
loop gain and loop filter characteristics.
29. FUNCATIONAL BLOCK DIAGRAM OF MONOLITHIC PL
565
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The centre frequency of the PLL is determined by the
free running frequency of the VCO. This is given by
the equation
Fo = 1.2/(4R1C1)Hz, where R1 and C1 are the
external R and C connected to pins 8 and 9 of the IC.
R1 must have a value between 2KΩ and 20KΩ. C1
can have any standard value. The internal resistance
R2 = 3.6 KΩ and external capacitor C2 acts as Low
pass filter.
31. CLOSE LOOP ANALYSIS OF PLL
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35. VOLTAGE CONTROLLED OSCILLATOR
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Voltage control oscillator is a free running oscillator in
which the frequency of oscillation can be controlled by
an external timing capacitor, an external resistor and
an externally applied voltage (Control Voltage Vc).
VCO generates square and triangular waveforms
whose frequency is directly proportional to its control
voltage Vc.
36. PIN DIAGRAM OF IC 566 VCO
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37. BLOCK DIAGRAM OF NE/SE 566 VCO
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The constant current source is used to
charge and discharge the capacitor C.
The charging current can be controlled
by changing the voltage Vc at pin
number 5 or by changing the external
resistance R.
Pin 5 and Pin 6 have equi-potential.
Therefore, if we increase the control
voltage Vc at pin 5, the voltage at 6 will
also increase with the same amount.
The increment in above said voltage
Vc reduces the voltage drop across R
and reduce the charging current.
38. BLOCK DIAGRAM OF NE/SE 566 VCO
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The voltage across the capacitor C
(triangular wave) is applied to buffer
A1. This buffer is used to avoid loading
of capacitor. The output of buffer is
taken as triangular wave output at pin
4.
Schmitt trigger A2, converts the
incoming triangular wave into square
waveform. The output voltage of
Schmitt trigger is designed to swing
between +V and 0.5V.
Resistors Ra and Rb determine the
LTP and UTP of Schmitt trigger. The
square wave output of Schmitt trigger
A2 is inverted by inverter A3 and made
available at pin 3.
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Features of IC 566 VCO
The main features of IC 566 VCO are :
1. Wide supply voltage range of 10V to 24V
2. Very linear modulation stability
3. High temperature stability
4. Excellent power supply rejection
5. The frequency can be controlled by means of current,
voltage, resistor or capacitor
41. APPLICATIONS OF VCO
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The applications of VCO are :
1. FM modulation
2. Signal generation (Triangular or square wave).
3. Function generation
4. Frequency shift keying (FSK demodulator)
5. Frequency multipliers
6. Converting low frequency signals such as EEG and
ECG into Audio frequency range signals and
7. Tone generation
42. APPLICATIONS OF PLL - FREQUENCY MULTIPLIER
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Frequency multiplier can be
constructed by connecting the
divided by N (÷N) counter in
between the VCO (pin 4) and
phase detector (pin 5).
Since the output of the divider
is locked to the input
frequency, the VCO is actually
running at a multiple of the
input frequency. Therefore, in
the locked
43. FREQUENCY DIVIDER
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The frequency multiplier can also be used for
frequency division. Since the VCO output (a square
wave) is rich in harmonics, it is possible to lock the mth
harmonic of the VCO output with the input signal fs,
The output fo of VCO is now given by
44. FREQUENCY SYNTHESIZER
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The circuit of frequency synthesizer is same as frequency
multiplier circuit except that divided by M network is added
at the input of phase lock loop (PLL). In order to ensure
the stability of output frequency, a crystal oscillator is
employed.
The frequency of the crystal-controlled oscillator is divided
by an integer factor M. Divided by network is used to
produce a frequency of fosc/M, where fosc is the
frequency of the crystal controlled oscillator.
PLL compares this frequency with the frequency at the
output of divide by N network, and tries to adjust this
frequency equal to fosc/M.
45. PLL AS FREQUENCY SYNTHESIZER
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46. PLL AS A FM DETECTOR
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The FM signal which is to
be demodulated is applied
to the input of PLL.
When the PLL is locked in
on the FM signal, the VCO
frequency follows the
instantaneous frequency of
the FM signal. The error
voltage or VCO control
voltage is proportional to
the deviation of the input
frequency from the centre
frequency.
The ac component of the
error voltage represents the
modulating signal. Thus,
demodulated signal can be
obtained at the error
amplifier output. The
faithful reproduction of
modulating voltage
depends on the linearity
between the instantaneous
frequency deviation and the
control voltage of VCO.
47. FREQUENCY SHIFT KEYING (FSK)
DEMODULATOR
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It is similar to the PLL demodulator for analog FM
signals except the addition of a comparator to produce
a reconstructed digital output signal.
48. KONGUNADU COLLEGE OF ENGINEERING
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Binary data is transmitted by means of a carrier frequency. It uses two
different carrier frequencies for logic 1 and logic 0 states of binary data
signal. This type of data transmission is called frequency shift keying
(FSK).
In this data transmission, on the receiving end, two carrier frequencies
are converted into 1 and 0 to get the original binary data. This process
is called as FSK demodulation.
FSK is used in computer peripherals and radio (wireless)
communication. There are two frequencies. one frequency (f1) is
represented as “0” and other frequency (f2) is represented as “1”. If the
PLL remains locked into the FSK signal at both f1 and f2, the VCO
control voltage which is also supplied to the comparator will be given
as Vc1 = (f1 - fo) / Kv and Vc2 = (f2 - fo) / Kv respectively. Where Kv is
the voltage to frequency transfer coefficient of the VCO.
The difference between the two control voltage levels will be ∆Vc = (f2-
f1) / Kv. The reference voltage for the comparator is derived from the
additional low pass filter and it is adjusted midway between Vc1 and
Vc2· Therefore, for Vc1 and Vc2 comparator gives output ‘0’ and ‘1’
,respectively. Thus the FSK signal is demodulated, and at the output ‘o’
and ‘1’ are available.
49. FREQUENCY TRANSLATION
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Frequency translator circuit contains mixer, low pass
filter and the PLL. The frequency fs is one the input
given to the mixer, which is to be translated to the new
desired value.
Another input to the mixer is the output of VCO.
Therefore, the output of mixer contains the sum and
difference signal (fo ± fS).
50. PLL AS FREQUENCY TRANSLATOR
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