This document summarizes a lecture on random number generators and linear feedback shift registers (LFSRs) in Verilog. It introduces random number generators and their uses. It describes computational random number generation methods like linear congruential generators. It then focuses on LFSRs for generating pseudo-random numbers in digital hardware. It discusses Fibonacci and Galois LFSR structures and explains that Galois is better for hardware due to computing all taps in parallel. Finally, it provides examples of LFSR Verilog code, including a D flip-flop module with propagation delays specified.
Logic Level Techniques for Power Reduction GargiKhanna1
This document discusses various logic level techniques for low power VLSI design, including:
- Gate reorganization techniques like combining gates to reduce switching activity.
- Signal gating to block propagation of unwanted signals using AND/OR gates or latches.
- Logic encoding methods like gray code counting to reduce bit transitions.
- State machine encoding to lower expected bit transitions in the state register and outputs.
- Precomputation logic that disables inputs to combinational logic when output is invariant, reducing switching activity at the cost of increased area.
This document discusses digital filters and their implementation in Verilog. It covers:
- Types of digital filters including low-pass, high-pass, band-pass, and band-stop filters
- Finite impulse response (FIR) filters and their implementation using multiplication and addition
- An example 5-tap FIR filter implemented in Verilog
- Infinite impulse response (IIR) filters and their implementation using feedback registers
- An example single tap IIR filter implemented in Verilog with combinational and sequential logic blocks
A second important technique in error-control coding is that of convolutional coding . In this type of coding the encoder output is not in block form, but is in the form of an encoded
sequence generated from an input information sequence.
convolutional encoding is designed so that its decoding can be performed in some structured and simplified way. One of the design assumptions that simplifies decoding
is linearity of the code. For this reason, linear convolutional codes are preferred. The source alphabet is taken from a finite field or Galois field GF(q).
Convolution coding is a popular error-correcting coding method used in digital communications.
The convolution operation encodes some redundant information into the transmitted signal, thereby improving the data capacity of the channel.
Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.
This document discusses various designs for digital multipliers. It begins by reviewing the basic building blocks used in digital circuits and how binary multiplication works by adding partial products. It then describes approaches for implementing multiplication, including right shift and add serial multipliers and faster parallel array and tree multipliers. Booth encoding is introduced as a technique to reduce the number of stages in a multiplier. Implementation details are provided for array and Wallace tree multipliers, including the use of compression cells like the (4,2) counter. Optimization goals for multipliers differ from adders in emphasizing reducing the critical path.
This document discusses the conversion of flip flops, including converting an SR flip flop to a T flip flop and an SR flip flop to a JK flip flop. The generalized process for conversion involves using the excitation tables of the given and required flip flops to design a combinational logic circuit. This circuit, along with the given flip flop, produces the behavior of the required flip flop. Specifically, the document provides examples of converting an SR flip flop to a T flip flop using a truth table and K-maps and converting an SR flip flop to a JK flip flop using the same process.
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
VHDL is a hardware description language used to model digital circuits. It allows modeling at different levels of abstraction like behavioral, dataflow, and structural. VHDL supports design reuse through libraries and packages. Key benefits include being public standard, technology independent, and supporting design hierarchy, simulation, synthesis and documentation. The basic units in VHDL are entities which define the interface and architectures which describe the internal implementation. Architectures contain concurrent statements that execute in parallel and sequential statements in processes that execute sequentially.
Logic Level Techniques for Power Reduction GargiKhanna1
This document discusses various logic level techniques for low power VLSI design, including:
- Gate reorganization techniques like combining gates to reduce switching activity.
- Signal gating to block propagation of unwanted signals using AND/OR gates or latches.
- Logic encoding methods like gray code counting to reduce bit transitions.
- State machine encoding to lower expected bit transitions in the state register and outputs.
- Precomputation logic that disables inputs to combinational logic when output is invariant, reducing switching activity at the cost of increased area.
This document discusses digital filters and their implementation in Verilog. It covers:
- Types of digital filters including low-pass, high-pass, band-pass, and band-stop filters
- Finite impulse response (FIR) filters and their implementation using multiplication and addition
- An example 5-tap FIR filter implemented in Verilog
- Infinite impulse response (IIR) filters and their implementation using feedback registers
- An example single tap IIR filter implemented in Verilog with combinational and sequential logic blocks
A second important technique in error-control coding is that of convolutional coding . In this type of coding the encoder output is not in block form, but is in the form of an encoded
sequence generated from an input information sequence.
convolutional encoding is designed so that its decoding can be performed in some structured and simplified way. One of the design assumptions that simplifies decoding
is linearity of the code. For this reason, linear convolutional codes are preferred. The source alphabet is taken from a finite field or Galois field GF(q).
Convolution coding is a popular error-correcting coding method used in digital communications.
The convolution operation encodes some redundant information into the transmitted signal, thereby improving the data capacity of the channel.
Convolution Encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.
This document discusses various designs for digital multipliers. It begins by reviewing the basic building blocks used in digital circuits and how binary multiplication works by adding partial products. It then describes approaches for implementing multiplication, including right shift and add serial multipliers and faster parallel array and tree multipliers. Booth encoding is introduced as a technique to reduce the number of stages in a multiplier. Implementation details are provided for array and Wallace tree multipliers, including the use of compression cells like the (4,2) counter. Optimization goals for multipliers differ from adders in emphasizing reducing the critical path.
This document discusses the conversion of flip flops, including converting an SR flip flop to a T flip flop and an SR flip flop to a JK flip flop. The generalized process for conversion involves using the excitation tables of the given and required flip flops to design a combinational logic circuit. This circuit, along with the given flip flop, produces the behavior of the required flip flop. Specifically, the document provides examples of converting an SR flip flop to a T flip flop using a truth table and K-maps and converting an SR flip flop to a JK flip flop using the same process.
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
VHDL is a hardware description language used to model digital circuits. It allows modeling at different levels of abstraction like behavioral, dataflow, and structural. VHDL supports design reuse through libraries and packages. Key benefits include being public standard, technology independent, and supporting design hierarchy, simulation, synthesis and documentation. The basic units in VHDL are entities which define the interface and architectures which describe the internal implementation. Architectures contain concurrent statements that execute in parallel and sequential statements in processes that execute sequentially.
This document provides an overview of frequency analysis techniques for signals and systems, including the Fourier series, Fourier transform, discrete-time Fourier series (DTFS), discrete-time Fourier transform (DTFT), and discrete Fourier transform (DFT). It discusses properties and applications of these techniques, such as analyzing periodic and aperiodic signals. Examples are provided to illustrate calculating the Fourier series and transform of simple signals. The document also covers sampling theory and the Nyquist criterion for proper reconstruction of signals from samples.
Latch and flip flop circuits are used to store digital information. A latch can store a bit as long as power is applied, while a flip flop uses feedback to store a bit even after inputs change. There are different types of flip flops like SR, JK, D and T flip flops that store bits based on their input conditions and clock signal. Flip flops are edge triggered which means they change state only on rising or falling edge of the clock signal. This provides synchronization between logic and memory in digital circuits.
This document discusses counters in digital electronics. It begins by introducing counters as sequential circuits that increment their output value by one each clock cycle, wrapping back to 0 after their maximum count. There are two main types of counters: asynchronous and synchronous. Asynchronous counters have their flip-flops clocked one after another by the previous flip-flop's output, causing a ripple effect. Synchronous counters clock all flip-flops simultaneously with a common clock signal. Examples of 4-bit asynchronous and synchronous counters are also provided with their respective timing diagrams.
The document discusses built-in self-testing (BIST) for testing integrated circuits. BIST uses on-chip pattern generators and response compactors to test circuits without needing expensive external automatic test equipment. It reduces costs associated with test generation, storage, application and diagnosis. The document covers BIST architectures, linear feedback shift registers for pseudo-random pattern generation, response compaction, and fault coverage analysis of BIST.
This document describes a 4-bit synchronous binary counter. It contains the truth table for a JK flip-flop, diagrams of the counter circuit using 4 JK flip-flops connected in series with a common clock, and tables showing the output logic states and timing diagram as the counter counts from 0 to 15 over 16 clock pulses.
In communication system, intersymbol interference (ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. This is an unwanted phenomenon as the previous symbols have similar effect as noise, thus making the communication less reliable.
In communication system, the Nyquist ISI criterion describes the conditions which when satisfied by a communication channel (including responses of transmit and receive filters), result in no intersymbol interference(ISI). It provides a method for constructing band-limited functions to overcome the effects of intersymbol interference.
This document discusses Low Density Parity Check (LDPC) codes. It describes LDPC codes as having sparse parity check matrices, which allows for large minimum distances and improved error correction performance. It explains the differences between regular and irregular LDPC codes, and discusses factors like minimum distance, cycle length, linear independence, and encoding and decoding of LDPC codes. It provides examples of parity check matrices and generator matrices. It also provides an overview of an LDPC system and the encoding process.
DSP_2018_FOEHU - Lec 03 - Discrete-Time Signals and SystemsAmr E. Mohamed
The document discusses discrete-time signals and systems. It defines discrete-time signals as sequences represented by x[n] and discusses important sequences like the unit sample, unit step, and periodic sequences. It then defines discrete-time systems as devices that take a discrete-time signal x(n) as input and produce another discrete-time signal y(n) as output. The document classifies systems as static vs. dynamic, time-invariant vs. time-varying, linear vs. nonlinear, and causal vs. noncausal. It provides examples to illustrate each classification.
This document provides an overview of digital filter design. It introduces finite impulse response (FIR) and infinite impulse response (IIR) filters. FIR filters are designed using window techniques like rectangular, Hamming, and Kaiser windows. IIR filters are designed using approximation methods like Butterworth, Chebyshev I, and Chebyshev II. MATLAB code is provided to design low pass, high pass, and other filters using different window and approximation techniques. Pros and cons of FIR and IIR filters are discussed along with references.
This document discusses the design and characteristics of CMOS voltage comparators. It begins by defining the basic requirement of a comparator to compare an analog input voltage to a reference voltage and output a binary signal. It then covers comparator static characteristics like gain, offset voltage, resolution and noise. Dynamic characteristics of propagation delay and slew rate are also discussed. Different comparator circuit topologies like open-loop, regenerative and high-speed designs are presented. The document provides small-signal models of common comparator circuits and examines the effects of hysteresis. It concludes by presenting the typical architecture of high-speed comparators using preamplifier and latch stages to minimize propagation delay.
This document provides an introduction to Verilog, a hardware description language (HDL). It describes the main purposes of HDLs as allowing designers to describe circuits at both the algorithmic and gate levels, enabling simulation and synthesis. The document then discusses some Verilog basics, including modules as building blocks, ports, parameters, variables, instantiation, and structural vs procedural code. It provides examples of module declarations and typical module components.
What is PLL and elements of PLL??
What is Analog PLL??
What is Digital PLL??
What are the components of Digital PLL??
Applications of PLL
PLL as 565 IC pin diagram
PLL as Frequency Synthesizer (Frequency Translator)
PLL as Frequency Division
PLL as Frequency Multiplication
PLL as FM Demodulator
A ripple carry adder is constructed by cascading full adder blocks in series. It is called a ripple carry adder because the carry bit from each stage ripples into the next. For an n-bit ripple adder, n full adders are required. It has a propagation delay, as the carry bit must ripple from the least significant to the most significant bit. Ripple carry adders are commonly used for addition in digital signal processing and microprocessors due to their simplicity.
This document discusses metastability, mean time between failures (MTBF), synchronizers, and synchronizer failures. It begins with introductions to metastability and cases where it can occur. It then illustrates metastability with diagrams and graphs. It discusses how systems enter metastability and what occurs during metastability. The document derives the MTBF equation and provides an example calculation. It concludes by listing references for further information.
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...Madhumita Tamhane
In contrast to block codes, Convolution coding scheme has an information frame together with previous m information frames encoded into a single code word frame, hence coupling successive code word frames. Convolution codes are most important Tree codes that satisfy certain additional linearity and time invariance properties. Decoding procedure is mainly devoted to correcting errors in first frame. The effect of these information symbols on subsequent code word frames can be computed and subtracted from subsequent code word frames. Hence in spite of infinitely long code words, computations can be arranged so that the effect of earlier frames, properly decoded, on the current frame is zero.
IIR filter realization using direct form I & IISarang Joshi
The document discusses IIR filter realization using Direct Form I and Direct Form II structures. It presents the difference equation and transfer function for an IIR filter. It also provides examples of implementing IIR filters using Direct Form I and Direct Form II structures based on a given difference equation or transfer function.
This document discusses switch level modeling in Verilog. It describes different types of transistor switches that can be used as primitives in Verilog, including nmos, pmos, rnmos, rpmos, and cmos switches. It also covers bidirectional switches like tran, tranif1, and examples of how to use the switches to model basic logic gates and memory cells like a RAM cell. Time delays can be specified for switches. Switch level modeling allows designing circuits using transistors directly in Verilog.
This document discusses multirate digital signal processing and basic sampling rate alteration devices. It describes up-samplers and down-samplers in the time and frequency domains. Up-samplers increase the sampling rate by inserting zeros, which in the frequency domain causes images of the input spectrum. Down-samplers decrease the sampling rate by selecting samples, which can cause aliasing due to spectrum overlap if the Nyquist criterion is not met. The time-varying and frequency translation properties of up-samplers and down-samplers are illustrated through examples.
The document describes the implementation of 16-bit and 64-bit shift registers using VHDL in data flow modeling. It includes the VHDL code, test bench, and simulation results for shift registers that shift the values in the input register right by 1 bit position on the positive edge of the clock. The 16-bit shift register outputs the shifted value on q1 and the 64-bit shift register outputs the shifted value on q2. The design and functionality of both shift registers are verified through simulation.
This document provides an overview of Verilog concepts including data types, operators, modeling combinational and sequential logic, and designing modules with a hierarchical structure. It discusses four-value logic, number formats, constants, nets, registers, integers, bitwise, relational, logical, and arithmetic operators. It provides examples of combinational logic models using always blocks and case statements, and sequential logic using if and case statements. It also covers topics like indexing/slicing, internal wires, and designing modules that instantiate other modules.
This document provides an overview of frequency analysis techniques for signals and systems, including the Fourier series, Fourier transform, discrete-time Fourier series (DTFS), discrete-time Fourier transform (DTFT), and discrete Fourier transform (DFT). It discusses properties and applications of these techniques, such as analyzing periodic and aperiodic signals. Examples are provided to illustrate calculating the Fourier series and transform of simple signals. The document also covers sampling theory and the Nyquist criterion for proper reconstruction of signals from samples.
Latch and flip flop circuits are used to store digital information. A latch can store a bit as long as power is applied, while a flip flop uses feedback to store a bit even after inputs change. There are different types of flip flops like SR, JK, D and T flip flops that store bits based on their input conditions and clock signal. Flip flops are edge triggered which means they change state only on rising or falling edge of the clock signal. This provides synchronization between logic and memory in digital circuits.
This document discusses counters in digital electronics. It begins by introducing counters as sequential circuits that increment their output value by one each clock cycle, wrapping back to 0 after their maximum count. There are two main types of counters: asynchronous and synchronous. Asynchronous counters have their flip-flops clocked one after another by the previous flip-flop's output, causing a ripple effect. Synchronous counters clock all flip-flops simultaneously with a common clock signal. Examples of 4-bit asynchronous and synchronous counters are also provided with their respective timing diagrams.
The document discusses built-in self-testing (BIST) for testing integrated circuits. BIST uses on-chip pattern generators and response compactors to test circuits without needing expensive external automatic test equipment. It reduces costs associated with test generation, storage, application and diagnosis. The document covers BIST architectures, linear feedback shift registers for pseudo-random pattern generation, response compaction, and fault coverage analysis of BIST.
This document describes a 4-bit synchronous binary counter. It contains the truth table for a JK flip-flop, diagrams of the counter circuit using 4 JK flip-flops connected in series with a common clock, and tables showing the output logic states and timing diagram as the counter counts from 0 to 15 over 16 clock pulses.
In communication system, intersymbol interference (ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. This is an unwanted phenomenon as the previous symbols have similar effect as noise, thus making the communication less reliable.
In communication system, the Nyquist ISI criterion describes the conditions which when satisfied by a communication channel (including responses of transmit and receive filters), result in no intersymbol interference(ISI). It provides a method for constructing band-limited functions to overcome the effects of intersymbol interference.
This document discusses Low Density Parity Check (LDPC) codes. It describes LDPC codes as having sparse parity check matrices, which allows for large minimum distances and improved error correction performance. It explains the differences between regular and irregular LDPC codes, and discusses factors like minimum distance, cycle length, linear independence, and encoding and decoding of LDPC codes. It provides examples of parity check matrices and generator matrices. It also provides an overview of an LDPC system and the encoding process.
DSP_2018_FOEHU - Lec 03 - Discrete-Time Signals and SystemsAmr E. Mohamed
The document discusses discrete-time signals and systems. It defines discrete-time signals as sequences represented by x[n] and discusses important sequences like the unit sample, unit step, and periodic sequences. It then defines discrete-time systems as devices that take a discrete-time signal x(n) as input and produce another discrete-time signal y(n) as output. The document classifies systems as static vs. dynamic, time-invariant vs. time-varying, linear vs. nonlinear, and causal vs. noncausal. It provides examples to illustrate each classification.
This document provides an overview of digital filter design. It introduces finite impulse response (FIR) and infinite impulse response (IIR) filters. FIR filters are designed using window techniques like rectangular, Hamming, and Kaiser windows. IIR filters are designed using approximation methods like Butterworth, Chebyshev I, and Chebyshev II. MATLAB code is provided to design low pass, high pass, and other filters using different window and approximation techniques. Pros and cons of FIR and IIR filters are discussed along with references.
This document discusses the design and characteristics of CMOS voltage comparators. It begins by defining the basic requirement of a comparator to compare an analog input voltage to a reference voltage and output a binary signal. It then covers comparator static characteristics like gain, offset voltage, resolution and noise. Dynamic characteristics of propagation delay and slew rate are also discussed. Different comparator circuit topologies like open-loop, regenerative and high-speed designs are presented. The document provides small-signal models of common comparator circuits and examines the effects of hysteresis. It concludes by presenting the typical architecture of high-speed comparators using preamplifier and latch stages to minimize propagation delay.
This document provides an introduction to Verilog, a hardware description language (HDL). It describes the main purposes of HDLs as allowing designers to describe circuits at both the algorithmic and gate levels, enabling simulation and synthesis. The document then discusses some Verilog basics, including modules as building blocks, ports, parameters, variables, instantiation, and structural vs procedural code. It provides examples of module declarations and typical module components.
What is PLL and elements of PLL??
What is Analog PLL??
What is Digital PLL??
What are the components of Digital PLL??
Applications of PLL
PLL as 565 IC pin diagram
PLL as Frequency Synthesizer (Frequency Translator)
PLL as Frequency Division
PLL as Frequency Multiplication
PLL as FM Demodulator
A ripple carry adder is constructed by cascading full adder blocks in series. It is called a ripple carry adder because the carry bit from each stage ripples into the next. For an n-bit ripple adder, n full adders are required. It has a propagation delay, as the carry bit must ripple from the least significant to the most significant bit. Ripple carry adders are commonly used for addition in digital signal processing and microprocessors due to their simplicity.
This document discusses metastability, mean time between failures (MTBF), synchronizers, and synchronizer failures. It begins with introductions to metastability and cases where it can occur. It then illustrates metastability with diagrams and graphs. It discusses how systems enter metastability and what occurs during metastability. The document derives the MTBF equation and provides an example calculation. It concludes by listing references for further information.
Convolution codes - Coding/Decoding Tree codes and Trellis codes for multiple...Madhumita Tamhane
In contrast to block codes, Convolution coding scheme has an information frame together with previous m information frames encoded into a single code word frame, hence coupling successive code word frames. Convolution codes are most important Tree codes that satisfy certain additional linearity and time invariance properties. Decoding procedure is mainly devoted to correcting errors in first frame. The effect of these information symbols on subsequent code word frames can be computed and subtracted from subsequent code word frames. Hence in spite of infinitely long code words, computations can be arranged so that the effect of earlier frames, properly decoded, on the current frame is zero.
IIR filter realization using direct form I & IISarang Joshi
The document discusses IIR filter realization using Direct Form I and Direct Form II structures. It presents the difference equation and transfer function for an IIR filter. It also provides examples of implementing IIR filters using Direct Form I and Direct Form II structures based on a given difference equation or transfer function.
This document discusses switch level modeling in Verilog. It describes different types of transistor switches that can be used as primitives in Verilog, including nmos, pmos, rnmos, rpmos, and cmos switches. It also covers bidirectional switches like tran, tranif1, and examples of how to use the switches to model basic logic gates and memory cells like a RAM cell. Time delays can be specified for switches. Switch level modeling allows designing circuits using transistors directly in Verilog.
This document discusses multirate digital signal processing and basic sampling rate alteration devices. It describes up-samplers and down-samplers in the time and frequency domains. Up-samplers increase the sampling rate by inserting zeros, which in the frequency domain causes images of the input spectrum. Down-samplers decrease the sampling rate by selecting samples, which can cause aliasing due to spectrum overlap if the Nyquist criterion is not met. The time-varying and frequency translation properties of up-samplers and down-samplers are illustrated through examples.
The document describes the implementation of 16-bit and 64-bit shift registers using VHDL in data flow modeling. It includes the VHDL code, test bench, and simulation results for shift registers that shift the values in the input register right by 1 bit position on the positive edge of the clock. The 16-bit shift register outputs the shifted value on q1 and the 64-bit shift register outputs the shifted value on q2. The design and functionality of both shift registers are verified through simulation.
This document provides an overview of Verilog concepts including data types, operators, modeling combinational and sequential logic, and designing modules with a hierarchical structure. It discusses four-value logic, number formats, constants, nets, registers, integers, bitwise, relational, logical, and arithmetic operators. It provides examples of combinational logic models using always blocks and case statements, and sequential logic using if and case statements. It also covers topics like indexing/slicing, internal wires, and designing modules that instantiate other modules.
This document summarizes a class lecture on cryptocurrency mining. It discusses the mining process, which involves finding a nonce value that satisfies the mining difficulty target for a block. Miners include transactions and solve cryptographic puzzles to validate blocks and earn rewards. The document explains Merkle trees, which improve transaction verification scalability. It also discusses the high computational costs and energy requirements of mining, noting specialized mining hardware can solve puzzles thousands of times faster than CPUs. The goal of mining is to process and validate transactions in a decentralized manner to maintain blockchain integrity.
The document is a lab manual for the VLSI Design Laboratory course. It contains information about the college and course code. The manual includes 10 experiments related to Xilinx and FPGA based design and Cadence based design. It provides Verilog code and simulation outputs for designing basic logic gates, counters, state machines, an 8-bit adder and 4-bit multiplier using Xilinx. The experiments cover synthesis, placement and routing of designed components on FPGA boards.
This work presents the evaluation of the two classic workstealing algorithms (FIFO and LIFO) together with a new proposed implementation based on the priority of tasks calculated using the longest path as a metric
Quantum programming in a nutshell Radu Vunvulea ITCamp 2018Radu Vunvulea
I'm pretty sure that you already heard about quantum computers and how they will change the way how we do IT. In this session, we plan to take a look at the programming models that we need to use when we write applications for quantum processors.
Sounds interesting? Then join this session for a journey in the world of quantum programming to find out how we should write code for this supercomputers
Exactly-Once Made Easy: Transactional Messaging Improvement for Usability and...Guozhang Wang
1) The document discusses Kafka transactions and exactly-once processing in Kafka.
2) It describes the current approach Kafka uses to achieve exactly-once semantics, including idempotent writes within a partition and transactional writes across partitions.
3) It also discusses challenges with the current approach, such as lack of scalability due to the need to create a producer for each input partition, and proposes solutions in KIP-447 to address these challenges.
The document discusses blockchain and cryptocurrency technologies. It provides information on the following key points:
- Cryptographic hash functions are the backbone of blockchain and map variable-length inputs to fixed-length outputs, making it difficult to determine the input from the output or find colliding inputs.
- Blockchain uses these hash functions to create tamper-evident linked data structures like blocks in a blockchain or nodes in a Merkle tree. This allows transactions in a blockchain to be publicly verifiable and tamper-resistant.
- Bitcoin implements blockchain technology to create a decentralized transaction ledger. Transactions are grouped into blocks and miners compete to add new blocks through a computational puzzle. This consensus mechanism allows all nodes to agree
Static analysis should be used regularlyPVS-Studio
We have a practice of occasionally re-analyzing projects we have already checked with PVS-Studio. There are several reasons why we do so. For example, we want to know if we have managed to eliminate false positives for certain diagnostics. But the most interesting thing is to see how new diagnostic rules work and what errors they can find. It is very interesting to watch the tool catch more and more new defects in a project that seems to be cleaned out already. The next project we have re-checked is Clang.
Exactly-Once Made Easy: Transactional Messaging Improvement for Usability and...HostedbyConfluent
This talk is aimed to give developers who are interested to scale their streaming application with Exactly-Once (EOS) guarantees. Since the original release, EOS processing has received wide adoption as a much needed feature inside the community, and has also exposed various scalability and usability issues when applied in production systems.
To address those issues, we improved on the existing EOS model by integrating static Producer transaction semantics with dynamic Consumer group semantics. We will have a deep-dive into the newly added features (KIP-447), from which the audience will have more insight into the scalability v.s. semantics guarantees tradeoffs and how Kafka Streams specifically leveraged them to help scale EOS streaming applications written in this library. We would also present how the EOS code can be simplified with plain Producer and Consumer. Come to learn more if you wish to adopt this improved EOS feature and get started on building your own EOS application today!
"HHVM is a high-performance, open source PHP execution engine developed at Facebook. It’s the fastest PHP runtime in the world, with support for PHP5, PHP7, and Hack—the programming language used for Facebook’s web server application logic. In addition to powering Facebook’s web tier, HHVM has also been adopted by other major services such as Wikipedia, Baidu, and Box.
HHVM uses just-in-time compilation to transform PHP and Hack source code into optimized machine code. Thanks to contributions from developers across the ARM community, HHVM can now target AArch64 in addition to x86-64 and successfully runs open source PHP frameworks like WordPress. Join us for an overview of HHVM, a quick demo, and some thoughts on where optimization efforts can go from here."
This document discusses sequential circuits and sequential basics in Verilog, including:
- Sequential circuits have outputs that depend on current and previous inputs and store state to represent the history of inputs, usually governed by a clock.
- D-flipflops are basic 1-bit storage elements that store a new value on each clock cycle. Registers are made of multiple D-flipflops to store multi-bit values.
- Pipelines can be built using registers to break a process into stages, allowing a new input to pass through each stage on every clock cycle while keeping the clock period low. An example pipeline computes the average of three input streams by storing intermediate values in registers between calculation stages.
The document discusses MQ problem determination techniques using tracing on Linux. It covers MQ API tracing to see application calls to MQ, including input and return data. It provides an example API trace of the amqsput program and explains how to read the trace, including the meaning of input and output fields. It also discusses the mqtrcfrmt tool to help format traces by expanding MQ data structures and constants.
This document summarizes elements of the Bitcoin protocol for developers. It describes the blockchain network protocol, how transactions are structured with inputs and outputs, and how Bitcoin scripting works to lock and unlock transactions based on signatures and public keys. Bitcoin scripting uses a stack-based approach to evaluate transactions in a non-Turing complete manner. Examples are provided of common script patterns and a more complex script for an odd/even betting contract.
The document discusses using Simulink for model-based development of an electric vehicle control system. It lists several Simulink blocks used including subsystems, bit shifting, switch case, unit delays, and displaying scope. It also mentions using Simulink Support Package for Arduino to target an Arduino Mega microcontroller. The document encourages having a good model-based development life and provides links to GitHub repositories for the EV control system models.
This document describes the implementation of a Snake game on an FPGA board using Verilog. The game logic and hardware description are written in Verilog. Key components include a Xilinx Zybo Zynq-7000 FPGA board connected to a VGA monitor. Verilog code is used to generate the VGA signals and implement the snake game logic including movement, boundaries, scoring, and reset. The design is tested through simulation and implemented on the FPGA board.
The document discusses recent improvements to numeric handling in Python, particularly the new float representation (repr) introduced in Python 2.7. The new repr aims to produce the shortest decimal string that rounds back to the original float value, satisfying constraints of accuracy and consistency. It uses adapted C code that performs correctly rounded conversions between decimal strings and floating point values. The new repr is friendlier for beginners and reduces discrepancies between platforms.
Kotlin Backend Development 6 Yrs Recap. The Good, the Bad and the UglyHaim Yadid
NEXT Insurance is a US based insurtech startup, revolutionizing the small business insurance industry. NEXT was founded 6 years ago and ever since we have been building our microservices in Kotlin. During this period we grew from a small startup with one backend developer(myself) to a $4B company with 150 backend developers. We have written over 1.2M lines of code in Kotlin and aquired long mileage with this programming language. In this talk I am going to share our experiences, insights and pains.
This talk was given in JFokus 2022
This document provides an overview of computer architecture and microprocessor concepts including:
1. It discusses different number systems such as binary, decimal, hexadecimal and their conversions. It also covers logic gates, Boolean algebra and other digital logic concepts.
2. It introduces microprocessors and their general architecture. It discusses microprocessor operations such as memory reads/writes and I/O reads/writes.
3. It covers computer languages from machine language to assembly and high-level languages. It also discusses compilers and interpreters.
El día 21 de Septiembre, tuvimos el placer de acoger en nuestras oficinas un Meetup impartido por nuestro compañero Paco Guerrero sobre la plataforma Apache Flink.
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Beyond Degrees - Empowering the Workforce in the Context of Skills-First.pptxEduSkills OECD
Iván Bornacelly, Policy Analyst at the OECD Centre for Skills, OECD, presents at the webinar 'Tackling job market gaps with a skills-first approach' on 12 June 2024
How to Make a Field Mandatory in Odoo 17Celine George
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This document provides an overview of wound healing, its functions, stages, mechanisms, factors affecting it, and complications.
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Leveraging Generative AI to Drive Nonprofit InnovationTechSoup
In this webinar, participants learned how to utilize Generative AI to streamline operations and elevate member engagement. Amazon Web Service experts provided a customer specific use cases and dived into low/no-code tools that are quick and easy to deploy through Amazon Web Service (AWS.)
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1. ECE 4514
Digital Design II
Spring 2008
Lecture 6:
A Random Number Generator
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Lecture 6:
A Random Number Generator
in Verilog
A Design Lecture
Patrick Schaumont
2. What is a random number generator?
Random
Number
Generator
11, 86, 82, 52, 60, 46, 64, 10, 98, 2, ...
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Generator
3. What do I do with randomness?
Play games!
Have the monsters appear in different rooms every time
Do statistical simulations
Simulate customers in a shopping center (find the best spot
for a new Chuck E Cheese)
Run security protocols
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Make protocol resistent against replay
Encrypt documents
Use random numbers as key stream
4. Encrypt Documents
Random
Number
Generator
XOR
stream of bytes
plaintext
encrypted stream of bytes
cryptext
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Generator
XOR
cryptext
decrypted stream of bytes
plaintext
'one-time pad'
5. Random numbers by physical methods
Use dice, coin flips, roulette
Use thermal noise (diodes and resistors)
Use clock jitter (use ring oscillators)
Use radioactive decay
Use Lava Lamps
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Use Lava Lamps
Patented!
6. Random numbers by computational methods
Not truly random, but pseudo random
meaning, after some time the same sequence returns
Linear Congruential Generator
x(n+1) = [ a.x(b) + b ] mod m
Eg. a = 15, b = 5, m = 7
a, b, m must be chosen carefully!
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Eg. a = 15, b = 5, m = 7
X(0) = 1
X(1) = (15 + 5) mod 7 = 6
x(2) = (15*6 + 5) mod 7 = 4
x(3) = 2
x(4) = 0
x(5) = 5
x(6) = 3
x(7) = 1
x(8) = ...
a, b, m must be chosen carefully!
for a maximum lenth sequence
7. A quick way to generate random numbers
Verilog has a buildin random number generator
module random(q);
output [0:31] q;
reg [0:31] q;
initial
r_seed = 2;
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
r_seed = 2;
always
#10 q = $random(r_seed);
endmodule
Nice, but only for testbenches …
Instead, we want an hardware implementation
8. Linear Feedback Shift Register
Pseudo Random Numbers in Digital Hardware
shift register
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
feedback network
9. Linear Feedback Shift Register
All zeroes
not very useful ...
0 0 0 0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0
10. Linear Feedback Shift Register
Non-zero state is more interesting
0 0 0 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1
1
11. Linear Feedback Shift Register
Non-zero state is more interesting
1 0 0 0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0
10
12. Linear Feedback Shift Register
Non-zero state is more interesting
0 1 0 0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0
100
13. Linear Feedback Shift Register
Non-zero state is more interesting
0 0 1 0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1
1001
14. Linear Feedback Shift Register
Non-zero state is more interesting
1 0 0 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1
10011
15. Linear Feedback Shift Register
Non-zero state is more interesting
0 1 0 0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0
100110
16. Linear Feedback Shift Register
Non-zero state is more interesting
0 0 1 0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1
1001101
etc ...
17. Linear Feedback Shift Register
This is actually a finite state machine
1 0 0 1
State Encoding
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1
18. Linear Feedback Shift Register
This is actually a finite state machine
0 0 0 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0001 1000 0100 0010 . . .
How many states will you see?
19. Linear Feedback Shift Register
15 states
0 0 0 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0001 1000 0100 0010 1001 1100 0110 1011
0101 1010 1101 1110 1111 0111 0011
20. Linear Feedback Shift Register
We can specify an LFSR by means of the
characteristic polynomial (also called feedback
polynomial)
X^1 X^2 X^3 X^4
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
P(x) = x^4 + x^3 + 1
There exists elaborate finite-field math to analyze the properties of
an LFSR - outside of the scope of this class
21. Linear Feedback Shift Register
So, knowing the polynomial you can also draw the
LFSR
P(x) = x^8 + x^6 + x^5 + x^4 + 1
How many taps ?
How many 2-input XOR?
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
How many 2-input XOR?
22. Linear Feedback Shift Register
So, knowing the polynomial you can also draw the
LFSR
P(x) = x^8 + x^6 + x^5 + x^4 + 1
How many taps ? 8
How many 2-input XOR?
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
How many 2-input XOR?
23. Linear Feedback Shift Register
So, knowing the polynomial you can also draw the
LFSR
P(x) = x^8 + x^6 + x^5 + x^4 + 1
How many taps ? 8
How many 2-input XOR? 3
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
How many 2-input XOR? 3
24. Linear Feedback Shift Register
Certain polynomials generate very long state
sequences. These are called maximal-length LFSR.
P(X) = x^153 + x^152 + 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
P(X) = x^153 + x^152 + 1
is a maximum-length feedback polynomial
State machine with 2 ^ 153 -1 states ..
25. Fibonacci and Galois LFSR
This format is called a Fibonacci LFSR
1 2 3 4
Fibonacci
~1175-1250
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Can be converted to an equivalent Galois LFSR
4 3 2 1
Evariste
Galois
1811-1832
26. Fibonacci and Galois LFSR
Each Fibonacci LFSR can transform into Galois LFSR:
Reverse numbering of taps
Make XOR inputs XOR outputs and vice versa
Example: starting with this Fibonacci LFSR
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1 2 3 4 5 6 7 8
27. Fibonacci and Galois LFSR
Disconnect XOR inputs
Reverse tap numbering (not the direction of shifting!)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
28. Fibonacci and Galois LFSR
Turn XOR inputs into XOR outputs and vice versa
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
29. Which one is better for digital hardware?
Fibonacci
1 2 3 4 5 6 7 8
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
Galois
30. Which one is better for digital hardware?
Fibonacci
1 2 3 4 5 6 7 8
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
Galois computes all taps in parallel
31. Which one is better for software?
Fibonacci
1 2 3 4 5 6 7 8
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
Galois
32. Which one is better for software?
Fibonacci
1 2 3 4 5 6 7 8
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
Galois
char_v = (char_v >> 1) ^ (-(signed char) (char_v & 1) & 0xe)
33. Let's write an LFSR in Verilog
xor(out, in1, in2)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
FF You need to build this one
(structural, behavioral)
34. A Flip flop
module flipflop(q, clk, rst, d);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
always @(posedge clk or posedge rst)
begin
if (rst)
q = 0;
else
q = d;
end
endmodule
35. A Flip flop
Setup Time:
Time D has to be stable before a clock edge
Hold Time:
Time D has to be stable after clock edge
Propagation Delay:
Delay from clock edge to Q
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Delay from clock edge to Q
Delay from reset to Q
How to specify propagation delay ?
36. A Flip flop
module flipflop(q, clk, rst, d);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
always @(posedge clk or posedge rst)
begin
if (rst)
q = 0;
else
q = d;
end
endmodule
How to specify propagation delay ?
37. A Flip flop
module flipflop(q, clk, rst, d);
input clk;
input rst;
input d;
output q;
reg q;
always @(posedge clk or posedge rst)
begin
if (rst)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
if (rst)
#2 q = 0;
else
q = #3 d;
end
specify
$setup(d, clk, 2);
$hold(clk, d, 0);
endspecify
endmodule
See Chapter 10
Palnitkar
Test setup, hold
38. Let's turn the LFSR into a module
1 2 3 4
How to program this?
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
output
(1 bit)
39. Let's turn the LFSR into a module
seed (4 bit)
load (1 bit)
1 1 1 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
1 2 3 4
output
(1 bit)
0
1
0 0 0
40. Multiplexer symbol
1
a
control
if (control)
out = a;
module mux(q, control, a, b);
output q;
reg q;
input control, a, b;
wire notcontrol;
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
0
b
out = a;
else
out = b;
bit multiplexer
wire notcontrol;
always @(control or
notcontrol or
a or b)
q = (control & a) |
(notcontrol & b);
not (notcontrol, control);
endmodule;
41. LFSR, structural
1 2 3 4
output (1 bit)
seed (4 bit)
load (1 bit)
1
0
1
0
1
0
1
0
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
module lfsr(q, clk, rst, seed, load);
...
wire [3:0] state_out;
wire [3:0] state_in;
flipflop F[3:0] (state_out, clk, rst, state_in);
endmodule
42. LFSR, structural
1 2 3 4
output (1 bit)
seed (4 bit)
load (1 bit)
1
0
1
0
1
0
1
0
module lfsr(q, clk, rst, seed, load);
...
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
...
wire [3:0] state_out;
wire [3:0] state_in;
wire nextbit;
xor G1(nextbit, state_out[2], state_out[3]);
assign q = nextbit;
endmodule
43. LFSR, structural
1 2 3 4
output (1 bit)
seed (4 bit)
load (1 bit)
1
0
1
0
1
0
1
0
module lfsr(q, clk, rst, seed, load);
...
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
...
wire [3:0] state_out;
wire [3:0] state_in;
wire nextbit;
mux M1[3:0] (state_in, load, seed, {state_out[2],
state_out[1],
state_out[0],
nextbit});
assign q = nextbit;
endmodule
44. LFSR module - complete
module lfsr(q, clk, rst, seed, load);
output q;
input [3:0] seed;
input load;
input rst;
wire [3:0] state_out;
wire [3:0] state_in;
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
flipflop F[3:0] (state_out, clk, rst, state_in);
mux M1[3:0] (state_in, load, seed, {state_out[2],
state_out[1],
state_out[0],
nextbit});
xor G1(nextbit, state_out[2], state_out[3]);
assign q = nextbit;
endmodule
45. LFSR testbench
module lfsrtst;
reg clk;
reg rst;
reg [3:0] seed;
reg load;
wire q;
lfsr L(q, clk, rst,
seed, load);
// initialization
// drive clock
always
#50 clk = !clk;
// program lfsr
initial begin
#100 seed = 4'b0001;
load = 1;
#100 load = 0;
end
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
// initialization
// apply reset pulse
initial
begin
clk = 0;
load = 0;
seed = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end
end
endmodule
48. Place and Route ..
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
49. Can a random number generator have flaws?
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
50. Can a random number generator have flaws?
Problem #1: it can have bias
Meaning: a certain number occurs more often then others
Expressed in the entropy rate of the generator
Entropy = true information rate (in bit/sec), can be lower then
the actual bitrate of the random number generator
Example: Assume an RNG that produces three events A,B,C
encoded with two bits
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
RNG
A
B
C
P(A) = 1/2
P(B) = 1/4
P(C) = 1/4
00
01
10
symbol probability bitpattern
So this bitstream has much more '0' then '1'. It has a bias.
E.g. ABACAABC... is encoded as 0001001000000110...
51. Can a random number generator have flaws?
Problem #1: it can have bias
Meaning: a certain number occurs more often then others
Expressed in the entropy rate of the generator
Entropy = true information rate (in bit/sec), can be lower then
the actual bitrate of the random number generator
Example: Assume an RNG that produces three events A,B,C
encoded with two bits
better
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
RNG
A
B
C
P(A) = 1/2
P(B) = 1/4
P(C) = 1/4
0
10
11
symbol probability
better
bitpattern
In this bitstream, the number of '1' and '0' are balanced.
E.g. ABACAABC... is encoded as 010011001011...
52. Can a random number generator have flaws?
Problem #1: it can have bias
Do LFSR have a bias ?
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
53. Can a random number generator have flaws?
Problem #1: it can have bias
Do LFSR have a bias ?
Yes, they have a small bias because the all-zero
state never appears.
However, for a very long LFSR, the bias becomes
negligible
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
negligible
54. Can a random number generator have flaws?
Problem #2: it can be predicted
Not when truly random phsysical phenomena
But, if it is a Pseudo RNG (like an LFSR), it is a
deterministic sequence.
Is this really a problem? Yes!
• Don't want to use a predictable RNG for dealing cards, driving a
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
• Don't want to use a predictable RNG for dealing cards, driving a
slot machine, ... (at least not if you own the place).
• Don't want to use predicatable RNG in security. Predicability =
weakness
55. Can a random number generator have flaws?
Problem #2: it can be predicted
The real issue for PRNG is: can the value of bit
N+1 be predicted when someone observes the first
N bits.
closed box
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
8 7 6 5 4 3 2 1
closed box
010111011..
The next one
will be .. 1 !
56. LFSR are very predictable ..
Predicting the next output bit is equivalent to knowing
the feedback pattern of the LFSR and the states of all
LFSR flip-flops.
Mathematicians (Berlekamp-Massey) found that:
Given an N-bit LFSR with unknown feedback pattern, then
only 2N bits are needed to predict bit 2N + 1
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
So let's say we have and 8-bit LFSR, then we need
only 16 bits of the RNG stream before it becomes
predicatble
LFSR are unsuited for everything that should be
unpredictable
57. To be unpredictable, the LFSR should be long
Solution 1
Use a maximal-length P(x) = x^N + ... + 1
with N >>> (E.g. 65,536)
Very expensive to make! 64K flip-flops ..
Solution 2: Non-linear Combination Generator
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Solution 2: Non-linear Combination Generator
short LFSR1
short LFSR2
short LFSR3
non
linear
func
A
B
C
out
Eg.
out = AB ^ BC ^ C
58. Example design by Tkacik, 2002
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Cellular Automata Shift Register
59. Example design by Tkacik, 2002
43-bit LFSR defined by
P(X) = X^43 + X^41 + X^20 + X + 1 => 3XOR, 43 taps
Maximal Length: 2^43-1
Bias ~ 2^-43 (because all-zero pattern cannot appear)
37-bit cellular automata shift register
Combines previous and next statereg into current state reg
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Similar to 37 intertwined state machines (automata)
Maximal Length: 2^37-1
Bias ~ 2^-37
1 2 3
from 37 from 1 from 2
to 37
...
...
60. Sample Implementation
On opencores you can find an implementation of
Tkacik's design - assigned reading of today
(this design has a few minor differences with the spec written
by Tkacik - but OK for our purpose)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
61. Module interface
module rng(clk,reset,loadseed_i,seed_i,number_o);
input clk;
input reset;
input loadseed_i;
input [31:0] seed_i;
output [31:0] number_o;
reg [31:0] number_o;
reg [42:0] LFSR_reg; // internal state
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
reg [42:0] LFSR_reg; // internal state
reg [36:0] CASR_reg; // internal state
always (.. CASR ..)
always (.. LFSR ..)
always (.. combine outputs ..)
endmodule
62. LFSR Part
reg[42:0] LFSR_varLFSR; // temporary working var
reg outbitLFSR; // temporary working var
always @(posedge clk or negedge reset)
begin
if (!reset )
begin
...
end
else
begin
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
begin
if (loadseed_i )
begin
...
end
else
begin
...
end
end
end
63. LFSR Part
reg[42:0] LFSR_varLFSR; // temporary working var
reg outbitLFSR; // temporary working var
always @(posedge clk or negedge reset)
begin
if (!reset )
begin
LFSR_reg = (1);
end
else
begin
assemble bits
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
begin
if (loadseed_i )
begin
LFSR_varLFSR [42:32]=0;
LFSR_varLFSR [31:0]=seed_i ;
LFSR_reg = (LFSR_varLFSR );
end
else
begin
...
end
end
end
LFSR_varLFSR
LFSR_reg
64. LFSR Part
reg[42:0] LFSR_varLFSR; // temporary working var
reg outbitLFSR; // temporary working var
always @(posedge clk or negedge reset)
begin
if (!reset )
else
begin
if (loadseed_i )
else
begin
LFSR_varLFSR
LFSR_reg
LFSR_varLFSR
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
begin
LFSR_varLFSR = LFSR_reg;
LFSR_varLFSR [42] = LFSR_varLFSR [41];
outbitLFSR = LFSR_varLFSR [42];
LFSR_varLFSR [42] = LFSR_varLFSR [41];
LFSR_varLFSR [41] = LFSR_varLFSR [40]^outbitLFSR ;
// some lines skipped ...
LFSR_varLFSR [0] = LFSR_varLFSR [42];
LFSR_reg = LFSR_varLFSR;
end
end
end
LFSR_reg
65. CASR Part (similar ...)
//CASR:
reg[36:0] CASR_varCASR,CASR_outCASR;
always @(posedge clk or negedge reset)
begin
if (!reset )
begin
...
end
else
begin
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
begin
if (loadseed_i )
begin
...
end
else
begin
...
end
end
end
66. CASR Part (similar ...)
//CASR:
reg[36:0] CASR_varCASR,CASR_outCASR; // temp
always @(posedge clk or negedge reset)
begin
if (!reset )
begin
CASR_reg = 1;
end
else
begin
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
begin
if (loadseed_i )
begin
CASR_varCASR [36:32]= 0;
CASR_varCASR [31:0] = seed_i ;
CASR_reg = (CASR_varCASR );
end
else
begin
...
end
end
end
67. CASR Part (similar ...)
//CASR:
reg[36:0] CASR_varCASR,CASR_outCASR; // temp
always @(posedge clk or negedge reset)
begin
if (!reset )
else
begin
if (loadseed_i )
else
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
else
begin
CASR_varCASR = CASR_reg ;
CASR_outCASR [36]= CASR_varCASR [35]^CASR_varCASR [0];
CASR_outCASR [35]= CASR_varCASR [34]^CASR_varCASR [36];
// ... some lines skipped
CASR_reg = CASR_outCASR;
end
end
end
68. Combine outputs
always @(posedge clk or negedge reset)
begin
if (!reset )
begin
number_o = (0);
end
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
else
begin
number_o = (LFSR_reg [31:0]^CASR_reg[31:0]);
end
end
70. Simulation (looking at the state registers)
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
72. Place and Route ..
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
73. Summary
Random number generators
Many useful applications
Linear Feedback Shift Registers: PRNG
Fibonacci and Galois
Maximal-length LFSR
Structural Verilog Model
Patrick Schaumont
Spring 2008
ECE 4514 Digital Design II
Lecture 6: A Random Number Generator in Verilog
Flaws of Random Number Generators
Bias
Predictability
Nonlinear Combination Generator
Design by Tkacik
Behavioral Verilog Model