Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.



Published on

Lec 22(1)

Published in: Education
  • Be the first to comment


  1. 1. Three FPLD Types• Simple Programmable Logic Device (SPLD) – LSI device – Less than 1000 logic gates• Complex Programmable Logic Device (CPLD) – VLSI device – Higher logic capacity than SPLDs• Field Programmable Gate Array (FPGA) – VLSI device – Higher logic capacity than CPLDs Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 1
  2. 2. Three FPLD Types• Simple Programmable Logic Device (SPLD) – PLA or PAL – Fixed internal routing, deterministic propagation delays• Complex Programmable Logic Device (CPLD) – Multiple SPLDs onto a single chip – Programmable interconnect• Field Programmable Gate Array (FPGA) – An array of logic blocks – Large number of gates, user selectable interconnection, delays depending on design and routing Programmable – A high ratio of flip-flops to logic resources Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 2
  3. 3. SPLDs• SPLDs = Simple PLDs• Popular SPLD Architecture Types – Programmable Logic Array, PLA – Programmable Array Logic, PAL (Vantis) – General Array Logic, GAL (Lattice) – others• Architecture Differences – AND versus OR implementation – Programmability (e.g., EE) – Fundamental logic block Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 3
  4. 4. SPLDs • We have already taken a close look at SPLDs • A PLA-like SPLD is illustrated at left – PAL and GAL devices offered a Logic Functions somewhat better solution • SPLDs are good alternative to Sums using SSI and MSI devices – Especially if re-programmable Programmable Logic Devices (FPLDs)Product Terms SPLDs CPLDs FPGAs (e.g., PALs) 4
  5. 5. SPLDs• Conventional programmable logic – PALs, PLAs, GALs – standard parts like GAL22V10 and PAL16R4 are available from multiple vendors• Includes programmable logic cells to a limited degree (programming options in I/O cells, may have fixed AND/OR gates for logic), limited routing network• Lowest density of all programmable devices, however, can offer very high performance• SPLDs have nearly replaced TTL logic which was the Programmable Logic Devices dominate approach to logic (FPLDs) implementation SPLDs CPLDs FPGAs (e.g., PALs) 5
  6. 6. How to Expand SPLD Architecture?• Increase number of inputs and outputs in a conventional PLD? – e.g., 16V8 → 20V8 → 22V10 – Why not → 32V16 → 128V64 ?• Problems: – n times the number of inputs and outputs requires n2 as much chip area – too costly – logic gets slower as number of inputs to AND array increases Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 6
  7. 7. How to Expand SPLD Architecture?• Solution: – Multiple SPLDs with a relatively small programmable interconnect – Less general than a single large PLD – Can use software “fitter” to partition into smaller PLD blocks Programmable Logic Devices (FPLDs) CPLD Architecture SPLDs CPLDs FPGAs (e.g., PALs) 7
  8. 8. CPLDs• PALs and GALs are available only in small sizes – equivalent to a few hundred logic gates• For bigger logic circuits, complex PLDs or CPLDs can be used.• CPLDs contain the equivalent of several PALs/GALs – linked by programmable interconnections – all in one integrated circuit (IC)• CPLDs can replace thousands, or even hundreds of thousands, of individual logic gates – increased integration density Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 8
  9. 9. Complex PLDs• Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins.• A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer.• The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function. Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 9
  10. 10. Complex PLDs versus FPGAs• Xilinx, for example:• Xilinx CPLD devices that are cheaper and have fewer gates than Xilinx FPGAs• Meant for interfacing rather than heavy computation• Built-in flash memory – Compare to FPGA which needs external configuration memory• Xess board has XC9572XL part – Approximately $2-$7 in quantities of one – vs. ~$15-20 for the Spartan2 FPGA on the board – Larger quantities much lower – 1600 gates, 72 registers Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 10
  11. 11. CPLD Architecture• Simplified CPLD architecture• Small number of largish PLDs (e.g., “36V18”) on a single chip• Programmable interconnect between PLDs• Large number of I/O blocks• Large number of pins 11
  12. 12. CPLDs• Composition of Complex PLDs – typically composed of 2-64 SPLDs – interconnected using sophisticated logic – includes macrocells (more about these later) – includes input/output blocks• Economical for designing large systems• Fast – switching speed Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 12
  13. 13. CPLDs• Complex PLDs have arrays of PLDs on one chip, with an interconnection matrix connecting them.• Timing performance can be more predictable than FPGAs because of simpler interconnect structure.• Density is normally less than most FPGAs (although high end CPLDs will have about the same density as low-end FPGAs).• Performance of CPLDs is usually better than FPGAs, but depends on vendor, number of cells in CPLD, and Programmable Logic Devices (FPLDs) compared FPGA. SPLDs CPLDs FPGAs (e.g., PALs) 13
  14. 14. CPLD Families• Identical individual PLD blocks (Xilinx “FBs”) replicated in different family members – Different number of PLD blocks – Different number of I/O pins Xilinx XC9500 CPLD Series 14
  15. 15. Typical CPLD Packages• CPLDs are made using 2 to 64 SPLDs• Packages use 44-pins to over 200-pins (or more) 15
  16. 16. Typical CPLD Packages• QFP = Quad Flat Package– A QFP is an IC package with leads extending from each of the four sides.– It is used primarily for surface mounting, no socketing• TQFP = Thin Quad Flat Package• PQFP = Plastic Quad Flat Package• VQFP = Very small Quad Flat Package• PLCC = Plastic Leaded Chip Carrier– A package related to QFP– Similar but has pins with larger distance, curved up underneath a thicker body to simplify socketing 16
  17. 17. CPLD Package Types• CSP = Chip Scale Package – IC package with an area no greater than 1.2 times that of the die• BGA = Ball Grid Array – A type of surface-mount packaging used for ICs – Pins are replaced by balls of solder stuck to the bottom of the package – The device is placed on a PCB that carries copper pads in a pattern that matches the solder balls – The assembly is then heated causing the solder balls to melt 17
  18. 18. CPLD Families• Many CPLDs have fewer I/O pins than macrocells – “Buried” Macrocells – provide needed logic terms internally but these outputs are not connected externally – IC package size dictates number of I/O pins but not the total number of macrocells – Typical CPLD families have devices with differing resources in the same IC package 18
  19. 19. Xilinx CPLDs• Notice overlap in resource availability in a particular package. 19
  20. 20. XC9572 CPLD Part Numbers• The part number for Xilinx CPLD devices includes information as follows: 20
  21. 21. XC9500 CPLD Block Diagram• The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration.• All devices are in- system programmable for a minimum of 10,000 program/erase cycles. 21
  22. 22. 9500-Family Function Blocks (FBs)• 18 macrocells per FB• 36 inputs per FB (partitioning challenge, but also reason for relatively compact size of FBs)• Macrocell outputs can go to I/O cells or back into switch matrix to be routed to this or other FBs 22
  23. 23. 9500-Series Macrocell • 18 macrocells per Function Block Set control Programmable inversion or XOR product term Up to 5 product termsGlobal clock or product-term clock Reset control OE control 23
  24. 24. 9500-Series Product-Term Allocator • Share terms from above and belowprogrammablesteeringelements 24
  25. 25. XC9500 Family• An I/O block is composed of input buffer, output buffer, multiplexer for the output control and grounding control• Slew rate control is used to smooth the rising and the falling edges of the output pulse.• Grounding control is used to make the input/output pin (I/O) an earth ground (noise suppression).• Each input/output pin can handle a 24-mA current. 25
  26. 26. 9500-Series I/O Block• OE Multiplexer (OE MUX) controls an output enable or stop.• It is controlled by the signal from the macrocell or the signal from the GTS (Global Three-State control) pin.• There are four GTS in XC95216 and XC95288 two in the others. 26
  27. 27. Switch Matrix for XC95108• Could be anything from a limited set of multiplexers to a full crossbar – Multiplexer -- small, fast, but difficult fitting – Crossbar -- easy fitting but large and slow 27
  28. 28. Problems with CPLDs• Pin locking – Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout – Locking too early may make the resulting circuit slower or not fit at all• Running out of resources – Design may “blow up” if it doesn’t all fit on a single device – On-chip interconnect resources are much richer than off- chip – Larger devices are exponentially more expensive 28