We propose an iterative (IR) and simulated-annealing (SA) based methodology for leakage power minimization by the means of gate sizing and threshold voltage assignment.
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
Fault Models
Physical Defect
Faults
Traditional Fault Models
Cell-aware User Defined Fault Models
Testing
Scan based control and observability (see my PhD talk slides)
Cell-aware fault coverage and testing
Test Compression
Diagnosis
Logic Diagnosis
Cell-aware diagnosis
Layout-aware diagnosis
Volume diagnosis
This document discusses power dissipation in CMOS circuits. It identifies the main sources of power dissipation as dynamic, static, and short circuit power. Dynamic power is caused by charging and discharging capacitors during switching and depends on activity factors, voltage, and frequency. Static power includes leakage currents that occur even when the device is inactive. Short circuit power arises when both NMOS and PMOS are on simultaneously during signal transitions. The document provides techniques for reducing each type of power dissipation such as lowering voltage, reducing switching activity, minimizing capacitance and transistor sizing.
Low Power VLSI Design Presentation_finalJITENDER -
This document discusses low power VLSI design techniques. It describes sources of power dissipation such as dynamic power from switching and static leakage power. It then discusses several approaches to reduce power consumption, including supply voltage scaling, minimizing switching capacitance through techniques like clock gating, and minimizing leakage through multi-threshold CMOS and power gating. The need for a power intent language to describe low power constructs is also discussed. Finally, it mentions low power EDA tools that can reduce power through techniques like clock gating and low power placement.
This document discusses various low power techniques for integrated circuits. It begins by describing the increasing challenges of power consumption as device densities and clock frequencies increase while supply voltages and threshold voltages decrease. It then discusses different types of power consumption, including dynamic power, static power, leakage power from different sources, and how they can be reduced. The document covers many low power design techniques like multi-threshold CMOS, clock gating, multi-voltage, DVFS, and more. It discusses the evolution of these techniques and challenges in their implementation like timing issues, level shifters, and floorplanning for multi-voltage designs.
This document discusses limitations of traditional serial scan design for testing integrated circuits and proposes an alternative called Random Access Scan (RAS). RAS addresses three key limitations of serial scan: 1) test data volume, 2) test application time, and 3) test power. In RAS, flip-flops act as addressable memory elements during test mode, reducing time to set and observe flip-flop states compared to serial scan. While RAS requires more gates and test pins than serial scan, it significantly reduces switching activity and power consumption during testing.
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
Fault Models
Physical Defect
Faults
Traditional Fault Models
Cell-aware User Defined Fault Models
Testing
Scan based control and observability (see my PhD talk slides)
Cell-aware fault coverage and testing
Test Compression
Diagnosis
Logic Diagnosis
Cell-aware diagnosis
Layout-aware diagnosis
Volume diagnosis
This document discusses power dissipation in CMOS circuits. It identifies the main sources of power dissipation as dynamic, static, and short circuit power. Dynamic power is caused by charging and discharging capacitors during switching and depends on activity factors, voltage, and frequency. Static power includes leakage currents that occur even when the device is inactive. Short circuit power arises when both NMOS and PMOS are on simultaneously during signal transitions. The document provides techniques for reducing each type of power dissipation such as lowering voltage, reducing switching activity, minimizing capacitance and transistor sizing.
Low Power VLSI Design Presentation_finalJITENDER -
This document discusses low power VLSI design techniques. It describes sources of power dissipation such as dynamic power from switching and static leakage power. It then discusses several approaches to reduce power consumption, including supply voltage scaling, minimizing switching capacitance through techniques like clock gating, and minimizing leakage through multi-threshold CMOS and power gating. The need for a power intent language to describe low power constructs is also discussed. Finally, it mentions low power EDA tools that can reduce power through techniques like clock gating and low power placement.
This document discusses various low power techniques for integrated circuits. It begins by describing the increasing challenges of power consumption as device densities and clock frequencies increase while supply voltages and threshold voltages decrease. It then discusses different types of power consumption, including dynamic power, static power, leakage power from different sources, and how they can be reduced. The document covers many low power design techniques like multi-threshold CMOS, clock gating, multi-voltage, DVFS, and more. It discusses the evolution of these techniques and challenges in their implementation like timing issues, level shifters, and floorplanning for multi-voltage designs.
This document discusses limitations of traditional serial scan design for testing integrated circuits and proposes an alternative called Random Access Scan (RAS). RAS addresses three key limitations of serial scan: 1) test data volume, 2) test application time, and 3) test power. In RAS, flip-flops act as addressable memory elements during test mode, reducing time to set and observe flip-flop states compared to serial scan. While RAS requires more gates and test pins than serial scan, it significantly reduces switching activity and power consumption during testing.
Expt1_Electronic Principles and Circuits Lab Manual_BEC303_18-11-2023.pptxDrAnanthKumarMS1
This document describes an experiment on bridge rectifier circuits. It contains:
1) An introduction to the BEC 303 electronics course and the objectives of experiment 1a on bridge rectifiers.
2) Details of the circuit design, components used, calculations for ripple factor, efficiency and regulation.
3) Procedures to set up the circuit in a simulator, make observations with and without a filter capacitor, and calculate performance metrics.
4) A second experiment on using a zener diode as a voltage regulator, covering the circuit, design considerations, procedure and observations.
Queuing theory and traffic analysis in depthIdcIdk1
This document provides a summary of concepts in queuing theory and network traffic analysis. It discusses queuing theory concepts like Little's Law, M/M/1 queues, and Kendall's notation. It then covers an empirical study of router delay that models delays using a fluid queue and reports on busy period metrics. Finally, it discusses the concept of network traffic self-similarity found in measurements of Ethernet LAN traffic.
This document discusses test generation for digital circuits. It covers fault detection and location in digital systems, as well as various test generation methods for combinational and sequential logic circuits. For combinational circuits, it describes path sensitization and Boolean difference methods. For sequential circuits, it discusses converting the circuit to combinational form and verifying the state table. The document also discusses design for testability, including testability measures and techniques like LSSD. Reed-Muller expansion is presented as a method to derive and implement logic functions.
This document provides an overview of a thesis that used OpenFOAM to simulate unsteady aerodynamic flow over a sphere. The study aimed to analyze flow instabilities and quantify uncertainty in simulations. It used an IDDES turbulence model on refined meshes. Frequency analysis revealed peaks from vortex shedding and shear layer instabilities. Mean flow parameters matched experimental data. Future work could include hybrid RANS-LES models and longer simulations for improved flow statistics.
The document discusses power estimation techniques at the circuit level. It describes SPICE simulation as the standard tool for circuit-level power analysis and mentions faster analytical models. It covers topics like power characterization of cell libraries through simulation and probability-based power estimation, which involves calculating signal probabilities and switching activity. Switching activity depends on factors like activity factor, abnormal switching due to glitches, and static and dynamic components of transition probability.
Measurements to Perform Voltage Reduction-MiuNicole Segal
This document discusses using measurements to support capacitor control on distribution systems. It proposes using measurements to define reactive power domains for capacitors and generators. A methodology is presented for partitioning a test system into these domains. Both centralized and distributed control approaches are formulated and compared through simulations on a test system and utility feeder. The distributed approach shows improvements over local control and approaches centralized solutions at higher loads, though centralized control performs better at low loads.
This document summarizes the setup and measurements of a cathodic protection network experiment using the Technotoy system. Key details include:
- Various meters and instruments are being used to measure corrosion reactions in real-time, including an oscilloscope, data logger, and micro-ammeter.
- Measurements are examining the "off potential" and ability to identify the "polarized potential". pH is also being measured at various stages.
- Data from the instruments is being logged directly to a spreadsheet where formulas calculate the effects on charges passing through the circuit.
- Initial measurements show voltages from the dry cell battery and small corrosion currents from an activated Alexander Cell. The data will be used to
The document summarizes a presentation on augmenting the velocity of supersonic molecular beams using a rotating source. Key points:
- A rotating nozzle source can increase the lab frame velocity of supersonic molecular beams, producing slower, colder beams for applications like precision spectroscopy and studies of cold molecular chemistry.
- Experimental results show the rotating source effectively shifts beam time-of-flight spectra and enhances beam density through centrifugal forces. Beam properties depend on parameters like gas type, source pressure and rotation speed.
- Improvements to the rotating source design aim to allow slowing of lighter molecules and higher operational frequencies. Future work may include secondary detection methods and dynamic rotor balancing for greater stability.
The document discusses delay modeling in digital VLSI circuits. It notes that circuit delay depends on many factors like charge, discharge, parasitics, transistor width-to-length ratio, fan-in, fan-out and topology. Existing delay models do not clearly indicate the contribution of each factor. This wastes circuit designers' time in simulation and tweaking. The document then presents a delay model based on logical effort that estimates delay based on the topology of the gate and relative sizes of its transistors. It shows how to compute logical effort values and parasitic delays for different gates. Applying this model helps optimize circuit design parameters like transistor sizes, number of stages in a path and topology for minimum delay.
This document provides an overview of various analysis tools available in EWB software for circuit simulation and analysis. It describes the following analysis types: DC operating point analysis, AC frequency analysis, transient analysis, Fourier analysis, noise analysis, distortion analysis, DC sweep analysis, sensitivity analysis, parameter sweep analysis, temperature sweep analysis, transfer function analysis, worst case analysis, pole zero analysis, and Monte Carlo analysis. For each analysis type, it provides a brief description of the analysis and an example circuit to demonstrate how to set up and interpret the results of that analysis.
Flexible Memory Allocation in Kinetic Monte Carlo SimulationsAaron Craig
The document describes different algorithms for performing kinetic Monte Carlo simulations of epitaxial crystal growth processes. It introduces linear search, standard inverted list, minimal allocation, and flexible allocation algorithms. The flexible allocation algorithm synthesizes aspects of the standard and minimal allocation approaches to provide memory efficient simulations while maintaining low computational cost per iteration. Performance comparisons on test systems show the flexible approach performs well even for large system sizes.
Part II also includes admittance and demag testing and uses more advanced equipment to test the meter. See live results from today’s newest test equipment.
lowpower consumption and details of dfferent power pdfManiBharathNuti1
This document discusses techniques for low power integrated circuit design. It begins with an introduction describing increasing power dissipation over time if left unconstrained. The main sources of power dissipation in CMOS circuits are then explained as dynamic switching power, short-circuit power, and leakage power. A variety of low power techniques are presented, ranging from basic approaches like voltage scaling to more advanced methods like power gating. Power gating is discussed in detail, including issues like rush current and verification challenges. The document concludes with sections on low power test strategies and power analysis.
This document presents preliminary results on developing an electro-thermal model for cylindrical double layer ultracapacitors operating at low temperatures and high power. An equivalent electric circuit model with nonlinear open circuit voltage mapping was able to accurately capture voltage behavior at sub-zero temperatures under different currents and states of charge. A linear two-state thermal model accounting for reversible and irreversible heat generation was also parameterized. The coupled electro-thermal model allows studying ultracapacitor and hybrid battery/ultracapacitor performance under cold starting conditions.
This document discusses analytically driven applications for power distribution systems. It provides examples of using analytical models and formulations to optimize switch placement for service restoration and capacitor placement for voltage control. Problem formulations are presented that consider objectives like reliability and efficiency along with electrical and operational constraints. Comments discuss challenges like limited distribution engineering education and the need for baselines to evaluate economically driven solutions.
This document describes an IA-32 processor core designed to operate over a wide voltage range from near-threshold voltages to maximum voltage. Key points:
- The "Claremont" prototype core can operate from 0.5V to 1.1V, achieving a 4.5x reduction in energy per cycle at its optimal voltage of 0.45V compared to maximum voltage. It demonstrates reliable near-threshold voltage operation down to 0.38V.
- Novel circuit techniques like variation-aware logic pruning, interruptible sequentials, and 10T register files enable robust near-threshold operation. Multi-corner timing convergence and programmable delay buffers manage skew across the wide voltage range.
- The core
This document discusses challenges in power system state estimation including measurement errors, leverage points, and topology errors. It proposes developing remote measurement calibration methods, robust parameter and topology estimators, and leverage point identification techniques. The goal is to provide accurate state estimation that can handle errors and outliers in measurements.
The document describes ongoing efforts to optimize a computational model of a CA1 pyramidal neuron. The model integrates synaptic and cellular interactions using the EONS/NEURON framework. The optimization aims to accurately reproduce various experimental data through tuning of channel conductances and other biophysical parameters. Several approaches are explored, including varying temperature effects, comparing different CA1 models, and deconvolving EPSCs to model presynaptic mechanisms. Future plans include using evolutionary optimization techniques and additional experimental objectives to further refine the model.
This document outlines a real-time phasor simulation test-bed for secondary voltage control of power grids using wide-area measurements. It presents a model predictive control (MPC) approach to coordinate reactive power compensators and regulate voltages at sensitive buses in real-time. Simulation results on the IEEE 39-bus system show the MPC controller can effectively handle voltage regulation and tracking in the presence of disturbances like generator trips and line outages. Future work includes real-time validation of the control approach on larger scale networks using decentralized MPC to address computational limitations.
Expt1_Electronic Principles and Circuits Lab Manual_BEC303_18-11-2023.pptxDrAnanthKumarMS1
This document describes an experiment on bridge rectifier circuits. It contains:
1) An introduction to the BEC 303 electronics course and the objectives of experiment 1a on bridge rectifiers.
2) Details of the circuit design, components used, calculations for ripple factor, efficiency and regulation.
3) Procedures to set up the circuit in a simulator, make observations with and without a filter capacitor, and calculate performance metrics.
4) A second experiment on using a zener diode as a voltage regulator, covering the circuit, design considerations, procedure and observations.
Queuing theory and traffic analysis in depthIdcIdk1
This document provides a summary of concepts in queuing theory and network traffic analysis. It discusses queuing theory concepts like Little's Law, M/M/1 queues, and Kendall's notation. It then covers an empirical study of router delay that models delays using a fluid queue and reports on busy period metrics. Finally, it discusses the concept of network traffic self-similarity found in measurements of Ethernet LAN traffic.
This document discusses test generation for digital circuits. It covers fault detection and location in digital systems, as well as various test generation methods for combinational and sequential logic circuits. For combinational circuits, it describes path sensitization and Boolean difference methods. For sequential circuits, it discusses converting the circuit to combinational form and verifying the state table. The document also discusses design for testability, including testability measures and techniques like LSSD. Reed-Muller expansion is presented as a method to derive and implement logic functions.
This document provides an overview of a thesis that used OpenFOAM to simulate unsteady aerodynamic flow over a sphere. The study aimed to analyze flow instabilities and quantify uncertainty in simulations. It used an IDDES turbulence model on refined meshes. Frequency analysis revealed peaks from vortex shedding and shear layer instabilities. Mean flow parameters matched experimental data. Future work could include hybrid RANS-LES models and longer simulations for improved flow statistics.
The document discusses power estimation techniques at the circuit level. It describes SPICE simulation as the standard tool for circuit-level power analysis and mentions faster analytical models. It covers topics like power characterization of cell libraries through simulation and probability-based power estimation, which involves calculating signal probabilities and switching activity. Switching activity depends on factors like activity factor, abnormal switching due to glitches, and static and dynamic components of transition probability.
Measurements to Perform Voltage Reduction-MiuNicole Segal
This document discusses using measurements to support capacitor control on distribution systems. It proposes using measurements to define reactive power domains for capacitors and generators. A methodology is presented for partitioning a test system into these domains. Both centralized and distributed control approaches are formulated and compared through simulations on a test system and utility feeder. The distributed approach shows improvements over local control and approaches centralized solutions at higher loads, though centralized control performs better at low loads.
This document summarizes the setup and measurements of a cathodic protection network experiment using the Technotoy system. Key details include:
- Various meters and instruments are being used to measure corrosion reactions in real-time, including an oscilloscope, data logger, and micro-ammeter.
- Measurements are examining the "off potential" and ability to identify the "polarized potential". pH is also being measured at various stages.
- Data from the instruments is being logged directly to a spreadsheet where formulas calculate the effects on charges passing through the circuit.
- Initial measurements show voltages from the dry cell battery and small corrosion currents from an activated Alexander Cell. The data will be used to
The document summarizes a presentation on augmenting the velocity of supersonic molecular beams using a rotating source. Key points:
- A rotating nozzle source can increase the lab frame velocity of supersonic molecular beams, producing slower, colder beams for applications like precision spectroscopy and studies of cold molecular chemistry.
- Experimental results show the rotating source effectively shifts beam time-of-flight spectra and enhances beam density through centrifugal forces. Beam properties depend on parameters like gas type, source pressure and rotation speed.
- Improvements to the rotating source design aim to allow slowing of lighter molecules and higher operational frequencies. Future work may include secondary detection methods and dynamic rotor balancing for greater stability.
The document discusses delay modeling in digital VLSI circuits. It notes that circuit delay depends on many factors like charge, discharge, parasitics, transistor width-to-length ratio, fan-in, fan-out and topology. Existing delay models do not clearly indicate the contribution of each factor. This wastes circuit designers' time in simulation and tweaking. The document then presents a delay model based on logical effort that estimates delay based on the topology of the gate and relative sizes of its transistors. It shows how to compute logical effort values and parasitic delays for different gates. Applying this model helps optimize circuit design parameters like transistor sizes, number of stages in a path and topology for minimum delay.
This document provides an overview of various analysis tools available in EWB software for circuit simulation and analysis. It describes the following analysis types: DC operating point analysis, AC frequency analysis, transient analysis, Fourier analysis, noise analysis, distortion analysis, DC sweep analysis, sensitivity analysis, parameter sweep analysis, temperature sweep analysis, transfer function analysis, worst case analysis, pole zero analysis, and Monte Carlo analysis. For each analysis type, it provides a brief description of the analysis and an example circuit to demonstrate how to set up and interpret the results of that analysis.
Flexible Memory Allocation in Kinetic Monte Carlo SimulationsAaron Craig
The document describes different algorithms for performing kinetic Monte Carlo simulations of epitaxial crystal growth processes. It introduces linear search, standard inverted list, minimal allocation, and flexible allocation algorithms. The flexible allocation algorithm synthesizes aspects of the standard and minimal allocation approaches to provide memory efficient simulations while maintaining low computational cost per iteration. Performance comparisons on test systems show the flexible approach performs well even for large system sizes.
Part II also includes admittance and demag testing and uses more advanced equipment to test the meter. See live results from today’s newest test equipment.
lowpower consumption and details of dfferent power pdfManiBharathNuti1
This document discusses techniques for low power integrated circuit design. It begins with an introduction describing increasing power dissipation over time if left unconstrained. The main sources of power dissipation in CMOS circuits are then explained as dynamic switching power, short-circuit power, and leakage power. A variety of low power techniques are presented, ranging from basic approaches like voltage scaling to more advanced methods like power gating. Power gating is discussed in detail, including issues like rush current and verification challenges. The document concludes with sections on low power test strategies and power analysis.
This document presents preliminary results on developing an electro-thermal model for cylindrical double layer ultracapacitors operating at low temperatures and high power. An equivalent electric circuit model with nonlinear open circuit voltage mapping was able to accurately capture voltage behavior at sub-zero temperatures under different currents and states of charge. A linear two-state thermal model accounting for reversible and irreversible heat generation was also parameterized. The coupled electro-thermal model allows studying ultracapacitor and hybrid battery/ultracapacitor performance under cold starting conditions.
This document discusses analytically driven applications for power distribution systems. It provides examples of using analytical models and formulations to optimize switch placement for service restoration and capacitor placement for voltage control. Problem formulations are presented that consider objectives like reliability and efficiency along with electrical and operational constraints. Comments discuss challenges like limited distribution engineering education and the need for baselines to evaluate economically driven solutions.
This document describes an IA-32 processor core designed to operate over a wide voltage range from near-threshold voltages to maximum voltage. Key points:
- The "Claremont" prototype core can operate from 0.5V to 1.1V, achieving a 4.5x reduction in energy per cycle at its optimal voltage of 0.45V compared to maximum voltage. It demonstrates reliable near-threshold voltage operation down to 0.38V.
- Novel circuit techniques like variation-aware logic pruning, interruptible sequentials, and 10T register files enable robust near-threshold operation. Multi-corner timing convergence and programmable delay buffers manage skew across the wide voltage range.
- The core
This document discusses challenges in power system state estimation including measurement errors, leverage points, and topology errors. It proposes developing remote measurement calibration methods, robust parameter and topology estimators, and leverage point identification techniques. The goal is to provide accurate state estimation that can handle errors and outliers in measurements.
The document describes ongoing efforts to optimize a computational model of a CA1 pyramidal neuron. The model integrates synaptic and cellular interactions using the EONS/NEURON framework. The optimization aims to accurately reproduce various experimental data through tuning of channel conductances and other biophysical parameters. Several approaches are explored, including varying temperature effects, comparing different CA1 models, and deconvolving EPSCs to model presynaptic mechanisms. Future plans include using evolutionary optimization techniques and additional experimental objectives to further refine the model.
This document outlines a real-time phasor simulation test-bed for secondary voltage control of power grids using wide-area measurements. It presents a model predictive control (MPC) approach to coordinate reactive power compensators and regulate voltages at sensitive buses in real-time. Simulation results on the IEEE 39-bus system show the MPC controller can effectively handle voltage regulation and tracking in the presence of disturbances like generator trips and line outages. Future work includes real-time validation of the control approach on larger scale networks using decentralized MPC to address computational limitations.
Similar to Leakage Power Minimization using SA-Based Gate Sizing and Threshold Voltage Assignment (20)
The cost of acquiring information by natural selectionCarl Bergstrom
This is a short talk that I gave at the Banff International Research Station workshop on Modeling and Theory in Population Biology. The idea is to try to understand how the burden of natural selection relates to the amount of information that selection puts into the genome.
It's based on the first part of this research paper:
The cost of information acquisition by natural selection
Ryan Seamus McGee, Olivia Kosterlitz, Artem Kaznatcheev, Benjamin Kerr, Carl T. Bergstrom
bioRxiv 2022.07.02.498577; doi: https://doi.org/10.1101/2022.07.02.498577
When I was asked to give a companion lecture in support of ‘The Philosophy of Science’ (https://shorturl.at/4pUXz) I decided not to walk through the detail of the many methodologies in order of use. Instead, I chose to employ a long standing, and ongoing, scientific development as an exemplar. And so, I chose the ever evolving story of Thermodynamics as a scientific investigation at its best.
Conducted over a period of >200 years, Thermodynamics R&D, and application, benefitted from the highest levels of professionalism, collaboration, and technical thoroughness. New layers of application, methodology, and practice were made possible by the progressive advance of technology. In turn, this has seen measurement and modelling accuracy continually improved at a micro and macro level.
Perhaps most importantly, Thermodynamics rapidly became a primary tool in the advance of applied science/engineering/technology, spanning micro-tech, to aerospace and cosmology. I can think of no better a story to illustrate the breadth of scientific methodologies and applications at their best.
The technology uses reclaimed CO₂ as the dyeing medium in a closed loop process. When pressurized, CO₂ becomes supercritical (SC-CO₂). In this state CO₂ has a very high solvent power, allowing the dye to dissolve easily.
Mending Clothing to Support Sustainable Fashion_CIMaR 2024.pdfSelcen Ozturkcan
Ozturkcan, S., Berndt, A., & Angelakis, A. (2024). Mending clothing to support sustainable fashion. Presented at the 31st Annual Conference by the Consortium for International Marketing Research (CIMaR), 10-13 Jun 2024, University of Gävle, Sweden.
PPT on Direct Seeded Rice presented at the three-day 'Training and Validation Workshop on Modules of Climate Smart Agriculture (CSA) Technologies in South Asia' workshop on April 22, 2024.
Immersive Learning That Works: Research Grounding and Paths ForwardLeonel Morgado
We will metaverse into the essence of immersive learning, into its three dimensions and conceptual models. This approach encompasses elements from teaching methodologies to social involvement, through organizational concerns and technologies. Challenging the perception of learning as knowledge transfer, we introduce a 'Uses, Practices & Strategies' model operationalized by the 'Immersive Learning Brain' and ‘Immersion Cube’ frameworks. This approach offers a comprehensive guide through the intricacies of immersive educational experiences and spotlighting research frontiers, along the immersion dimensions of system, narrative, and agency. Our discourse extends to stakeholders beyond the academic sphere, addressing the interests of technologists, instructional designers, and policymakers. We span various contexts, from formal education to organizational transformation to the new horizon of an AI-pervasive society. This keynote aims to unite the iLRN community in a collaborative journey towards a future where immersive learning research and practice coalesce, paving the way for innovative educational research and practice landscapes.
Authoring a personal GPT for your research and practice: How we created the Q...Leonel Morgado
Thematic analysis in qualitative research is a time-consuming and systematic task, typically done using teams. Team members must ground their activities on common understandings of the major concepts underlying the thematic analysis, and define criteria for its development. However, conceptual misunderstandings, equivocations, and lack of adherence to criteria are challenges to the quality and speed of this process. Given the distributed and uncertain nature of this process, we wondered if the tasks in thematic analysis could be supported by readily available artificial intelligence chatbots. Our early efforts point to potential benefits: not just saving time in the coding process but better adherence to criteria and grounding, by increasing triangulation between humans and artificial intelligence. This tutorial will provide a description and demonstration of the process we followed, as two academic researchers, to develop a custom ChatGPT to assist with qualitative coding in the thematic data analysis process of immersive learning accounts in a survey of the academic literature: QUAL-E Immersive Learning Thematic Analysis Helper. In the hands-on time, participants will try out QUAL-E and develop their ideas for their own qualitative coding ChatGPT. Participants that have the paid ChatGPT Plus subscription can create a draft of their assistants. The organizers will provide course materials and slide deck that participants will be able to utilize to continue development of their custom GPT. The paid subscription to ChatGPT Plus is not required to participate in this workshop, just for trying out personal GPTs during it.
The debris of the ‘last major merger’ is dynamically youngSérgio Sacani
The Milky Way’s (MW) inner stellar halo contains an [Fe/H]-rich component with highly eccentric orbits, often referred to as the
‘last major merger.’ Hypotheses for the origin of this component include Gaia-Sausage/Enceladus (GSE), where the progenitor
collided with the MW proto-disc 8–11 Gyr ago, and the Virgo Radial Merger (VRM), where the progenitor collided with the
MW disc within the last 3 Gyr. These two scenarios make different predictions about observable structure in local phase space,
because the morphology of debris depends on how long it has had to phase mix. The recently identified phase-space folds in Gaia
DR3 have positive caustic velocities, making them fundamentally different than the phase-mixed chevrons found in simulations
at late times. Roughly 20 per cent of the stars in the prograde local stellar halo are associated with the observed caustics. Based
on a simple phase-mixing model, the observed number of caustics are consistent with a merger that occurred 1–2 Gyr ago.
We also compare the observed phase-space distribution to FIRE-2 Latte simulations of GSE-like mergers, using a quantitative
measurement of phase mixing (2D causticality). The observed local phase-space distribution best matches the simulated data
1–2 Gyr after collision, and certainly not later than 3 Gyr. This is further evidence that the progenitor of the ‘last major merger’
did not collide with the MW proto-disc at early times, as is thought for the GSE, but instead collided with the MW disc within
the last few Gyr, consistent with the body of work surrounding the VRM.
Travis Hills of MN is Making Clean Water Accessible to All Through High Flux ...Travis Hills MN
By harnessing the power of High Flux Vacuum Membrane Distillation, Travis Hills from MN envisions a future where clean and safe drinking water is accessible to all, regardless of geographical location or economic status.
2. Outline
• Introduction
• Related Work
• Problem Formulation
• Proposed Methodology
• Experimental Results
• Conclusion and Future Work
2
3. Introduction
• Low Power and High Performance
• Mobile device
• Leakage Power Rise
• ITRS Roadmap 2009 [33]
• Technology scales down
3
4. Leakage Power Minimization Methods
• Gate Sizing
𝐺𝑎𝑡𝑒 𝑆𝑖𝑧𝑒 ∝
𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝑃𝑜𝑤𝑒𝑟 ∝
𝐷𝑟𝑖𝑣𝑖𝑛𝑔 𝑆𝑡𝑟𝑒𝑛𝑔𝑡ℎ
• Threshold Voltage Assignment
• 𝑉𝑡ℎ ∝ 1/𝐿𝑒𝑎𝑘𝑎𝑔𝑒 𝑃𝑜𝑤𝑒𝑟
• 𝑉𝑡ℎ ∝ 𝐷𝑒𝑙𝑎𝑦 𝑡𝑖𝑚𝑒
• Low Vth on critical path
• High Vth on non-critical path
4
5. Outline
• Introduction
• Related Work
• Problem Formulation
• Proposed Methodology
• Experimental Results
• Conclusion and Future Work
5
6. Related Work
6
Continuous methods Discrete methods
• Linear Programming (LP)
• Geometric programming
(GP)
• Sensitivity-based Approach
• Slack and delay Budgeting
• Dynamic Programming(DP)
• Lagrangian Relaxation (LR)
• Linear Programming (LP)
• Simulated Annealing (SA)
7. Continuous Methods
• Linear Programming (LP)
• Linear delay model
• The selection of gates is defined as linear function
• Geometric programming (GP)
• Polynomial delay model
7
8. Discrete Methods
• Sensitivity-based approach
• Score and Rank gates according to a defined sensitivity
• Iteratively select the best gate for optimization until no improvement can be
made
• Slack and delay budgeting
• Allocate a slack budget to each gate
• Use the slack budget to trade the power for each gate.
• Dynamic Programming (DP)
• Use decision stage and cost-to-go function.
8
9. Discrete Methods (cont.)
• Lagrangian Relaxation (LR)
• Covert constrained problem to unconstrained one.
• Lagrange multiplier
• Linear Programming (LP)
• The selection of gates is implemented by assigning value to a binary variable:
1 is chosen and 0 otherwise.
• Simulated Annealing (SA)
• Probabilistic method for finding a good approximation to the global optimum
9
10. Related Work Comparison
Methodology Pros Cons
Continuous
Sizing
LP
Fast
Modeling Error
Mapping IssueGP
Discrete
Sizing
Sensitivity Local optimal
Slack & Delay
Ignore delay interaction
LP
DP Solution space explosion
LR Large scale Solution Oscillate
SA
Global optimal
Approximation
Fast solution space
exploration
10
11. Outline
• Introduction
• Related Work
• Problem Formulation
• Proposed Methodology
• Experimental Results
• Conclusion and Future Work
11
12. Motivational Example
12
Solution u1 u2 u3
Timing
Violation
Total
Leakage
Power
Solution 1 s10 s06 s04 -2.32 26
Solution 2 s10 s06 f04 0 86
Solution 3 s10 s06 m04 0 38
n2n1
oa oa oa
n3 n4
50ps
u1 u2 u3
13. Problem Formulation
• Inputs:
• Standard Cell Library
• Gate-level Netlist
• Timing Constraints
• Interconnect Parasitics
• Outputs:
• The selection of each cell’s sizes and threshold voltage
• Objective:
• Satisfy all performance constraints
• Minimize total leakage power
13
14. Performance constraints
• Slack violation:
• At PO and DFF inputs, it exists negative slack.
• Slew(Transition time) violation:
• At PO and cell input pins, the transition time is larger than the max limit
transition time.
• Max-load violation:
• At cell output pins, the fan-out load summation is larger than the cell’s max
capacitance.
14
15. Problem Assumptions
• Interconnect parasitics are modeled as lumped capacitance.
• Sequential sizing is not allowed.
• Only one selection for sequential cells.
• Ideal clock network
• No clock buffer, zero skew, and clock net has zero lumped capacitance.
15
16. Outline
• Introduction
• Related Work
• Problem Formulation
• Proposed Methodology
• Experimental Results
• Conclusion and Future Work
16
17. Proposed Methodology
• Phase I: Iterative Algorithm for Initial Solution
• Initial solution that satisfies the timing requirement
• Phase II: Simulated-Annealing-Based Algorithm
• Leakage power minimization
17
18. Phase I: Pseudo Code
Iterative Algorithm: upsize cells for feasible solution
Inputs: netlist, cell library, timing constraints, and interconnect parasitics
Outputs: each cell’s size and threshold voltage assignment
Step 1: Count the visited times of the cells traced by negative-slack paths
Step 2: Sort by each cell counter
Step 3: Iterative upsizing in above-defined order
18
19. Phase I: Pseudo Code (Step 1)
Step 1: Count the visited times of the cells traced by negative-slack paths
Run timing engine to calculate each cell’s slack;
Initialize each cell’s counter to zero;
Initialize each cell’s to smallest type-size;
foreach (negative-slack paths)
foreach (cells in the selected path)
if (selected cell has negative slack)
Increase selected cell’s counter;
19
20. Phase I: Pseudo Code (Step 2 & 3)
Step 2: Sort by each cell counter
Sort cell order by each cell’s counter, from larger to small;
Step 3: Iterative upsizing in above-defined order
do
foreach (cell from above-defined order)
if (selected cell has negative slack)
while (selected cell has larger type-size)
if (new Pleakage < old Pleakage)
Update type-size;
until (no negative slack)
20
21. Phase II: Simulated-Annealing-Based
1. Solution representation:
• The set of size and type of each cell.
2. Solution perturbation:
• Randomly pick a cell and change its size and threshold voltage assignment.
3. Cost function:
• Total leakage power.
4. Annealing schedule: (next slide)
21
22. Phase II: SA — Temperature check
22
IF T > ε
THEN NEXT_ITER
ELSE
THEN FINISHED
FINISHED
START
initialization
T > ε
Find new solution
accept?
Update current solution
Update temperature(T)
update
T?
Yes
No
Yes
Yes
No
No
23. Phase II: SA — New solution
23
1. Randomly pick cell
2. Randomly pick new type
and size
3. Call timer and Recalculate
cost
FINISHED
START
initialization
T > ε
Find new solution
accept?
Update current solution
Update temperature(T)
update
T?
Yes
No
Yes
Yes
No
No
24. Phase II: SA — Solution acceptance
24
IF Cnew < Clast
IF Cnew < Cbest
THEN state = UPD
ELSE state = NEW
ELSE IF A.Prob. > Random
THEN state = ACP
ELSE state = REJ
0,1expProb.Accept. *TK
C
old
oldnew
C
CC
C
)(
1,0Random
FINISHED
START
initialization
T > ε
Find new solution
accept?
Update current solution
Update temperature(T)
update
T?
Yes
No
Yes
Yes
No
No
25. Phase II: SA — Solution update
25
FINISHED
START
initialization
T > ε
Find new solution
accept?
Update current solution
Update temperature(T)
update
T?
Yes
No
Yes
Yes
No
No
IF state = UPD or NEW or
ACP
THEN Slast = Snew
ELSE
THEN Slast = Slast
26. Phase II: SA — Temperature update
26
IF γ > φ
THEN DROP_TEMP
ELSE
THEN NEXT_ITER
γ is the counter of successive
state “Reject”
φ is a constant variable
FINISHED
START
initialization
T > ε
Find new solution
accept?
Update current solution
Update temperature(T)
update
T?
Yes
No
Yes
Yes
No
No
27. Outline
• Introduction
• Related Work
• Problem Formulation
• Proposed Methodology
• Experimental Results
• Conclusion and Future Work
27
28. Experimental Results
• Experimental Setting
• Standard Library
• Timing Engine
• Acceptance Probability
• Benchmark
• The Trend of Leakage Power Minimization
• Cost Comparison
28
29. Standard Library
• Cell Library in Synopsys Liberty format
• Combinational cells:
• 11 Footprints:
• in01, na02, na03, na04, no02, no03, no04, ao12, ao22, oa12 and oa22
• Each cell has 30 options
• 3 threshold voltage type and 10 gate size
• Sequential cells:
• 1 Footprints: ms08
29
30. Power, Capacitance, & Delay LUBs
30
Footprint:
in01
Leakage Power
(uW)
Capacitance
(fF)
Delay Time
(ps)
Vt Type
Gate Size
s m f s m f s m f
1 1 4 16 12.8 14.4 16 11.7 10.7 9.1
3 3 12 48 38.4 43.2 48 8.2 7.2 6.5
4 4 16 64 51.2 57.6 64 6.5 5.7 5.2
6 6 24 96 76.8 86.4 96 6.5 5.7 5.2
8 8 32 128 102.4 115.2 128 6.5 5.7 5.2
37. Cost Comparison
37
)
35
#
(*15
K
gates
RounduphhRuntime
3.71E+05
1.54E+06
2.05E+05
1.58E+05
1.47E+05
2.15E+05
4.51E+05
3.68E+05
0.E+00 5.E+05 1.E+06 2.E+06 2.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
DMA
3.51E+05
1.71E+06
2.03E+05
1.15E+05
1.16E+05
6.96E+05
2.26E+05
2.88E+05
0.E+00 5.E+05 1.E+06 2.E+06 2.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
pci_bridge32
1.54E+06
4.15E+06
6.74E+05
8.84E+05
6.97E+05
9.47E+05
2.28E+06
1.13E+06
0.E+00 2.E+06 4.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
des_perf
4.00E+05
1.47E+06
4.15E+05
3.78E+05
3.91E+05
4.63E+05
6.44E+05
7.53E+05
0.E+00 5.E+05 1.E+06 2.E+06 2.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
vga_lcd
↓ 73%
38. Cost Comparison (cont.)
38
7.32E+05
1.34E+06
6.27E+05
6.14E+05
7.36E+05
7.58E+05
8.62E+05
5.02E+06
0.E+00 2.E+06 4.E+06 6.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
b19
3.90E+06
4.78E+06
1.77E+06
1.97E+06
1.94E+06
1.81E+06
2.10E+06
2.00E+06
0.E+00 2.E+06 4.E+06 6.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
netcard
2.28E+06
5.40E+06
1.42E+06
1.79E+06
2.96E+06
1.47E+06
1.88E+06
1.92E+06
0.E+00 2.E+06 4.E+06 6.E+06
IR+SA
IR
NTUgs
UFRGS-BRAZIL
PowerValve
Goldilocks
eOPT
CUsizer
Total Leakage Power (μWatt)
leon3mp
39. Outline
• Introduction
• Related Work
• Problem Formulation
• Proposed Methodology
• Experimental Results
• Conclusion and Future Work
39
40. Conclusion
• An iterative algorithm is the necessary to initialization. Without using
it, the SA approach may not converge in fixed runtime.
• Our approach can reach a feasible solution in the same magnitude of
related works in all benchmarks.
• In some cases, our approach is resulted in a better solution than
previous work and reduce more than 70 % leakage power from initial
solution in sharp time.
40
41. Future Work
• Much realistic RC network model
• The leakage power minimization of the sequential circuit
41
而在這篇論文中,我們採用 gate sizing 和 threshold voltage assignment 作為我們降低 leakage power 的方法。
Gate 的尺寸影響驅動的能力,又和漏電流成正比,因此選用適當的尺寸能夠減少漏電流值。
另外,Threshold Voltage Assignment則是利用閥值電壓的特性,高Vth delay較長,但是漏電流較小,可以用於non-critical path。 而低 Vth可用於critical path,以符合timing requirement.
接下來是相關研究的部分
Gate sizing and threshold voltage assignmnet 相關的研究從90年代開始已經逐漸受到重視,因此針對在不同的實驗目標而所提出的各種方法,而主要可分為兩大類,分別為左邊的continuous methods和右邊的 discrete methods。
Continuous method 主要有 linear programming 和 geometric programming 兩種方法。
Discrete methods 則有 sensitivity-based approach, slack and delay budgeting 等六種方法。
以下我會簡短介紹各種方法,並且在此部分的最後做一個小結。
在continuous method 中, linear programming 將 power model和 gate selection定義呈線性函數。
而 geometric programming 進一步將 power model 定義成 多項式函數。
Modeling Error: misleads optimization due to the inaccuracy of delay and power models.
Mapping Issue: makes no guarantee on mapping a continuous solution to a discrete one.
LR 是將 constrained problem 轉換成 unconstrained problem 去求larangian multiplier的解
LP 有別於continuous method 將size and threshold voltage的選用,改成一個binary variable,來避免rounding問題
SA 則是 在退火的過程中,有條件地接受較差的解,以求接近最佳解的解,而且適用在離散的解空間(discrete larger search space)
第二階段SA,我分四個部分解釋,
首先 SA 的 solution 是指各個cell所用的type size
第二 solution的擾動是 隨機選取一個cell 並改變他的 type size
第三 cost function 是 total leakage power
最後的annealing schedule 會在flow chart 來說明