A memory stack on logic 3D IC stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.

1. A Comparative Simulation
Study of 3D Through Silicon
Stack Assembly Processes
Kamal Karimanal
Cielution LLC

2. Motivation

3. Traditional Flip Chip Process Steps
Step I: Silicon, solder bump and substrate
bond at reflow temperature (~230 C)
Step III: Underfilling, cure at above 160 C, Cool to
room temperature
Step IV: Lid attach/encapsulation at ~120 /180 C,
cool down to room temp
Step V: Board level attach & reflow at ~ 230C,
Step II: Cool down from 230 C
to room temperature
400 to 800 um die
(c) Cielution LLC

4. Classification of Through Silicon Stacking
From Process Flow Perspective
• W2W - D2W - D2D
• Chip Stacking First Vs. Chip 2 Substrate First
From an Underfilling Perspective…
• Capillary Underfilling (CUF)
• No Flow Underfilling (NUF)
• Molded Underfilling (MUF)
Interconnect Attach Perspective
• Reflow at ~ 230 C
• Thermo-compression Bonding @ 300-400 C
© Cielution LLC

5. Drivers for Thermo-Mechanical Simulation of
Assembly Processes
Assembly Process Technology Development
• Warpage assessment & feasibility of assembly
• New process evaluation
o CUF? NUF? MUF? Thermo Compression?
• Material choices & related process temperature implications
Package Design
• Warpage implication of the following:
o Encapsulation, substrate and stiffener dimensions
o Material Choice
Yield
• Low K Dielectric failure assessment
• Delamination Risk During Processing
Long term Reliability
• Solder Joint Reliability
• Underfill delamination mitigation
• Board level reliability of interconnects (shock/drop)
TSV/Device level Mobility impact study
(c) Cielution LLC

6. Scope of This Work

7. Stack up Description
Logic Die
(23mmX16mm)
Substrate
4X4 Memory
Stacks (10X6.5)
(c) Cielution LLC
FSRDL Films
BSRDL Films
Memory Chips
Underfill Regions
Logic Die

8. Scope
Two competing 3-D process flows were
considered
• Flow I - Memory stack to logic die first followed by
attach to substrate
o Pillar array with solder cap used for memory stack to logic
interconnection
o C4 bump array was used for logic to Substrate
• Flow II - Substrate to logic die attach first followed by
attach to memory stack
o Interconnect types were same as above
Both flows were followed by MC encapsulation
Thermo-Mechanical modeling approach was
used for investigation
• Substrate/logic die warpage at attach temperature
• Substrate/logic die warpage at room temperature

9. 3D Assembly Flow I: Chip Stack First
(c) Cielution LLC
Step 1: Mem Stack to Logic
(@ reflow Temperature 230 C)
Step 2: Capillary Underfill
Step 3: Chip Stack to Substrate
(@ reflow Temperature 230 C)
Step 4: Capillary Underfill Step 5: Overmolding or Lid Attach

10. Assembly Flow II: Substrate to Die First
(c) Cielution LLC
Step 1: Mem Stack to Logic
(@ reflow Temperature 230 C)
Step 3: Memory Stack Attach
Step 2: Capillary Underfill
Step 4: Capillary Underfill Step 5: Overmolding

11. Modeling Approach Used

12. Tools Used
3D Stack and Monolithic IC assembly process model
automation software, CielMech
Thermo-Mechanical and step by step process modeling
capabilities of ANSYS Mechanical FEA software.

13. Warpage Estimation Approaches
Thinned Wafer/chip
Warpage Estimation
Techniques
• Stoney Equation
o Applicable only to a single
substrate with film layers with
known stress free temperature.
o 50 um thick silicon is not much
thicker than the Front and Back Side
RDL Films (~5 to 10 um each).
Validity of Stoney equation is
questionable.
o Errors ~ 30 to 50% have been
observed for 50 micron thick wafers
with 5 micron thick films (Stoney
compared to FEA)
• Step by step Process modeling
using FEA Simulation
1 2
f Si '
(c) Cielution LLC
Film Stress, s
Stoney s Formula
t
si
t R
E
f
s  
R, radius of curvature
tSi
tf

14. Steps 3.2 & 3.2.1:
• Repeat Steps 3.1 & 3.1.1 for other chips on Chip 1 (use respective T3 & T4)
(c) Cielution LLC
Step By Step Process Modeling
Step 2:
• Ealive Second Film at T2
• Ramp to T3
• (T3 is the reference temperature of
the first film on Chip 2)
Step 3.1:
• Ealive Second chip & one film at T3
• Ramp to T4
• (T4 is the reference temperature of the
second film on Chip 2)
Step 3.1.1:
• Ealive Second film of second chip at T4
• Ramp to T5
•(T5 is the bump reflow temperature for attach between Chip 1 &
Chip 2)
Step 4:
• Ealive Lumped Bumps* of all Chip1–Chip_x interfaces at T5
• Ramp to T6
•(T6 is the underfill Cure temperature for the interface)
Step 1:
• Kill all elements other than first chip & Film
•Initial temperature is the deposition T of Film 1

15. Model Flow Chip 2 Chip
(c) Cielution LLC
Continue Similar Steps…
• Ealive Mold Compound at T8
• Set Ref Temp of Mold Compound to T8
• Cool Down to Room Temperature

16. Material Properties

17. Materials Properties
Part Material
Thickness
(mm)
Properties
E (Gpa)
CTE
(PPM/C)
n
Memory and Logic Dies Silicon 50 160 3 0.3
FSRDL (All chips) TEOS Oxide 5 71.487 0.51 0.3
BSRDL (All chips) Polyimide (PBO) 5 2 55 0.3
D2D Inter connections
25 mm dia Copper
Micropillars
25 121 17.3 0.3
Solder Cap(Sn 95.5, Ag 3.5) 10 50 20 0.3
Underfill epoxy 35 8 30.06 0.28
Substrate to Logic die
interconnection
100 mm dia C4 Bumps(Sn
95.5, Ag 3.5)
70 50 20 0.3
Underfill epoxy 70 15 30.06 0.28
Encapsulation Typical Mold Compound (MC) 700 26 15 0.3
Substrate Hitachi MCL_E_700G 400 33
Planar:
8
Normal:
20
0.25

18. Lumped Effective Properties of Interconnect
Region
Detailed Strip Model Lumped model Properties
Copper Pillar
25 mm dia, 25
mm tall, 50 mm
pitch
E=120GPA, CTE=17e-6,
n=0.3
E=2.4E10 , n=0.3 prior to
underfilling
E=2.9E10,n=0.3, CTE=25.6E-6
after underfill cure
Solder Cap 10 mm tall
Underfill
Viscoleastic model
from Park and Feger
[11]
Solder Bump
100 mm, dia, 70
mm tall, 200 mm
pitch
Viscoplastic Model
From Wang et al [12] E=9.5E9 , n=0.3 prior to
underfilling
E=1.5E10,n=0.3, CTE=26.6E-6
Viscoleastic model
from Park & Feger[11]
Underfill after underfill cure

19. Results and Discussion

20. Flow I Chip Stack warpage on attach+underfill &
Cool down
(c) Cielution LLC
Qualitative Warpage at T=20 Deg C

21. Flow I substrate warpage on attach to Chip Stack &
Cool down
(c) Cielution LLC
Qualitative Warpage at T=20 Deg C

22. Flow II Substrate Warpage on Attach & Underfill to
Thinned Logic Die & Cool Down
(c) Cielution LLC
Qualitative Warpage at T=20 Deg C
Substrate 1st: Thinned Die on
Substrate

23. Quantitative Warpage Evolution

24. Warpage Evolution for D2D Flow

25. Warpage Evolution for P2D Flow

26. Design Implications
CTE mismatch of silicon stack with MC and the
substrate cause counteracting warping
tendencies
This has always been an important design
parameter using which finally assembled
package warpage at room temperature as well
as board attach temperature may be tuned.
Following are some design parameter knobs:
• MC and substrate thickness
• Material properties (E & CTE) of MC and Substrate
• Die Thickness and size
• Need for Stiffener ring and it’s dimensions
• Need for external force during assembly its
minimization

27. Important Inferences
Path Dependence:
• Assembly of the same package stack can go through
significantly different warpage evolution depending on
process flow choice
Even though warping effect due to substrate was
dominant in both cases…
• D2D first flow resulted in
o C4 attach stage warpage being positive (~ +20 mm)
o Final warpage also being positive (~ +20 mm)
o This is also a function of MC properties and design
parameters
• P2D first flow resulted in
o C4 Attach stage warpage being negative (~ -25 mm )
o Final warpage also being positive (~ +20 mm)
o This is also a function of MC properties and design
parameters

28. Assembly Temperature Warpage
Due to the Stress free temperatures of
various package components being at
elevated temperature warpage at reflow
temperature was lower that that at room
temperature
But from the standpoint of assembling
without open and shorts attach temperature
warpage is a more important metric
This metric has smaller margin due to the
reduced micro pillar height