Thermo-compression bonding is a key technology for 3D integrated circuit packaging but has traditionally been costly due to low throughput. Recent developments have improved throughput and reduced costs. A dual bond head architecture on a fast machine can achieve 1000 units per hour per bonder. However, high volume production presents new challenges around tool repeatability, process portability, and usability. The document describes enhancements to bonding equipment that simplify processes and improve yields for applications like TSV memory stacks.
Hybrid bonding methods for lower temperature 3 d integration 1SUSS MicroTec
* Overview of primary 3D bonding processes
* Mechanics of metal bonding options
* Mechanics for hybrid bond materials
* Process requirement comparisons
* Equipment requirements for hybrid bond processes
A memory stack on logic 3D IC stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.
A memory stack on logic 3D IC stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.
Hybrid bonding methods for lower temperature 3 d integration 1SUSS MicroTec
* Overview of primary 3D bonding processes
* Mechanics of metal bonding options
* Mechanics for hybrid bond materials
* Process requirement comparisons
* Equipment requirements for hybrid bond processes
A memory stack on logic 3D IC stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.
A memory stack on logic 3D IC stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.
Wally s3 e cold_rolling_mills_strip_processing_linesWally Heydendael
Using liquid nitrogen as a coolant in final or skin pass cold rolling can dramatically increase
productivity by raising throughput, improving product quality and reducing rejects. G. Plicht and H.
Schillak of Air Products, and H. Höfinghoff and T. Demski of C.D. Wälzholz, describe the new Air
Products cool rolling technology.
The Innovative Laser Technologies in Cooperation with Ukrainian UniversitiesLvivPolytechnic
Presentation: The Innovative Laser Technologies in Cooperation with Ukrainian Universities
Presented by: Bogdan Antoszewski,
Kielce University of Technology
For: Ukrainian-Polish Forum «Technical Education for the Future of Europe»
Lviv, Ukraine, November, 6-9, 2014
This product is a type of Ceramic Encased Resistor, which is a type of Wire Wound Resistors. Features of this product are: Fibre glass & ceramic core available, Ceramic encased for high power dissipation, Radial terminations for Amp 187 & Amp 250 connectors available, Available with mounting bracket which also serves as heat sink. This products is consumable for Commercial and Industrial Electronics.
For more information of this product, please copy & paste the url given below:
http://htr-india.com/product/hcl/
3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update -...Yole Developpement
3D TSV technology is becoming a key solution platform for heterogeneous interconnection, high end memory and performance applications.
TSVs have been adopted for MEMS, Sensors, and Memory devices. What will the next technology driver be?
Through-silicon vias (TSVs) have now become the preferred interconnect choice for high-end memory. They are also an enabling technology for heterogeneous integration of logic circuits with CMOS image sensors (CIS), MEMS, sensors, and radio frequency (RF) filters. In the near future they will also enable photonics and LED function integration. The market for 3D TSV and 2.5D interconnect is expected to reach around two million wafers in 2020, expanding at a 22% compound annual growth rate (CAGR). The growth is driven by increased adoption of 3D memory devices in high-end graphics, high-performance computing, networking and data centers, and penetration into new areas, including fingerprint and ambient light sensors, RF filters and LEDs.
CIS still commanded more than 70% % share of TSV market wafer volume in 2015, although this will decrease to around 60% by 2020. This is primarily due to the growth of the other TSV applications, led by 3D memories, RF filters and fingerprint sensors (FPS). However, hybrid stacked technology, which uses direct copper-copper bonding, not TSVs, will penetrate around 30% of CIS production by 2020. The TSV markets for RF filters and FPS are expected to reach around $1.6B and $0.5B by 2020 respectively. The report will explain the market’s dynamics and give an overview of all segments and key markets. It will also provide market data in terms of revenues, units and wafer starts for all the different segments, including market share.
Wally s3 e cold_rolling_mills_strip_processing_linesWally Heydendael
Using liquid nitrogen as a coolant in final or skin pass cold rolling can dramatically increase
productivity by raising throughput, improving product quality and reducing rejects. G. Plicht and H.
Schillak of Air Products, and H. Höfinghoff and T. Demski of C.D. Wälzholz, describe the new Air
Products cool rolling technology.
The Innovative Laser Technologies in Cooperation with Ukrainian UniversitiesLvivPolytechnic
Presentation: The Innovative Laser Technologies in Cooperation with Ukrainian Universities
Presented by: Bogdan Antoszewski,
Kielce University of Technology
For: Ukrainian-Polish Forum «Technical Education for the Future of Europe»
Lviv, Ukraine, November, 6-9, 2014
This product is a type of Ceramic Encased Resistor, which is a type of Wire Wound Resistors. Features of this product are: Fibre glass & ceramic core available, Ceramic encased for high power dissipation, Radial terminations for Amp 187 & Amp 250 connectors available, Available with mounting bracket which also serves as heat sink. This products is consumable for Commercial and Industrial Electronics.
For more information of this product, please copy & paste the url given below:
http://htr-india.com/product/hcl/
3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update -...Yole Developpement
3D TSV technology is becoming a key solution platform for heterogeneous interconnection, high end memory and performance applications.
TSVs have been adopted for MEMS, Sensors, and Memory devices. What will the next technology driver be?
Through-silicon vias (TSVs) have now become the preferred interconnect choice for high-end memory. They are also an enabling technology for heterogeneous integration of logic circuits with CMOS image sensors (CIS), MEMS, sensors, and radio frequency (RF) filters. In the near future they will also enable photonics and LED function integration. The market for 3D TSV and 2.5D interconnect is expected to reach around two million wafers in 2020, expanding at a 22% compound annual growth rate (CAGR). The growth is driven by increased adoption of 3D memory devices in high-end graphics, high-performance computing, networking and data centers, and penetration into new areas, including fingerprint and ambient light sensors, RF filters and LEDs.
CIS still commanded more than 70% % share of TSV market wafer volume in 2015, although this will decrease to around 60% by 2020. This is primarily due to the growth of the other TSV applications, led by 3D memories, RF filters and fingerprint sensors (FPS). However, hybrid stacked technology, which uses direct copper-copper bonding, not TSVs, will penetrate around 30% of CIS production by 2020. The TSV markets for RF filters and FPS are expected to reach around $1.6B and $0.5B by 2020 respectively. The report will explain the market’s dynamics and give an overview of all segments and key markets. It will also provide market data in terms of revenues, units and wafer starts for all the different segments, including market share.
T HERMAL C ONTROL I N 3D L IQUID C OOLED P ROCESSORS V IA H OTSPOT S ...ijcsit
Microchannel liquid cooling is a promising techniqu
e to handling the high temperature problem of
three-dimensional (3D) processors. There have been
a few works which made initial attempts to optimize
liquid cooling by utilizing non-uniformly distribut
ed channels, variable flow rate, wider channels, an
d
Dynamic Voltage and Frequency Scaling (DVFS) combin
ed with thread migration mechanisms. Although
these optimizations could be better than a straight
forward microchannel liquid cooling design, the coo
ling
of 3D processors is limited due to design-time and
run-time challenges. Moreover, in new technologies,
the
processor power density is continually increasing a
nd this will bring more serious challenges to liqui
d
cooling.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
The merits and advantages of Ingeteam's third generation MV converters for +1...Ingeteam Wind Energy
As turbine sizes cross the threshold of 10MW, the wind turbine industry’s key supply chain partners must meet the challenge of developing components that enable turbine OEMs to provide machines that reduce LCoE.
Ingeteam’s latest expert report, written in partnership with Windpower Monthly, covers three areas of technological innovation for converters designed specifically for +10MW turbines:
- Voltage level - low voltage (LV) to medium voltage (MV) reduces power losses
- Number of conversion lines (CL)
- Semiconductor chip architectures.
Design and Implementation of Multiplier using Advanced Booth Multiplier and R...
Tackling High Volume Production of 3DI
1. 22nd Korean Conference on Semiconductors (KCS2015) Page 1
Tackling High Volume Production of 3DI/TSV Packages
Dr. Hugo Pristauz, VP TCB & Die Sorting,
Alastair Attard, Manager Process Development,
Besi Austria GmbH
The omni-presence of 3DI/TSV packages has been proposed since almost a decade, but the tremendous
package costs inhibited for a long time a general break-through of this technology. But, driven by super-
computing applications [4], the need for low-power consuming, high-speed memory stacks [5] has
evolved fast and since two years we see such kind of packages in volume production. Since thermo-
compression bonding is typically a slow process, the cost of ownership of thermo-compression equipment
is always under focus. Based on a dual bond head approach implemented on a fast machine architecture
an attractive cost-of-ownership can be offered on a minimum of floor-space, and 1000 UPH per TC
bonder is now a benchmark performance.
Beyond the high level of capabilities that thermo-compression bonders must provide for 3DI/TSV
applications there are special challenges like tool-to-tool repeatability, recipe portability, and enhanced
machine capability tests for thermo-compression equipment which must be tackled in a high volume
production environment. Finally a major challenge is addressing the graphical user interface (GUI)
which has to offer an easy access to the equipment whilst keeping the complexity of the machine behind
the scenes.
1. Introduction
Thermo-compression bonding (TCB) is a flip
chip assembly process where heat and pressure
is involved during the bonding phase of a pick
and place process. In the current volume
production major focus is on flip-chips with
copper pillar bumps that have a solder cap. Since
TCB is currently 4 to 8 times slower than mass
reflow flip chip bonding, the process is an
expensive one and will be only used for
applications where there is no other alternative.
This is the case for TSV based 3D integration,
especially for the production of TSV memory
stacks, where dies are usually 50µm thick with
roadmaps going down to 20µm. As such a thin
die would warp and lose touch with the substrate
after releasing it from the bond head, a
subsequent mass reflow would not work for high
yield requirements. With TC bonding the
subsequent mass reflow is replaced by a local
reflow in the bonder [3]. There are three TCB
main stream processes in place (fig. 1).
Fig 1: Types of TCB processes
The classical TC-NCP process (fig. 1a) com-
bines local reflow with a pre-applied underfill
paste, which is usually called NCP (non
conductive paste). The pre-application of the
NCP (in most cases dispensed) is an effective
approach to prevent voids in case of huge
numbers of low profile bump arrays [3]. In
addition the NCP is a helpful absorber of stress
caused by CTE mismatches in the cooling phase
of the TCB process [2]. This property has in
particular benefits for C2S applications, where
CTE mismatch is always a significant challenge.
2. 22nd Korean Conference on Semiconductors (KCS2015) Page 2
TC-NCP has several drawbacks: Especially for
memory applications where dies are very thin
the NCP-application process (dispensing) must
be very accurate, otherwise the NCP climbs up
the die, contaminates the bond tool and causes
down time. Another issue with NCP is the pre-
curing before bonding, which would happen for
pre-dispensed substrates or bottom wafers on a
heated bonding stage.
Because of these drawbacks the industry focuses
on pre-applied underfill on the die, which is
called NCF (non-conductive film) or WLUF
(wafer level underfill). TC-NCF process is
expected to become the main stream process for
memory stacking, although maturity of the
material seems still to be in improvement -
nevertheless the industry is optimistic to see
NCF in next mass production products.
Besides of these two processes there is a third
kind, TC-CUF (capillary underfill) with signifi-
cant potential. First of all it yields reliable mass
production products, proven by different indus-
try players. Secondly CUF can better target
major properties like package reliability and
thermal properties [1], as it does not have to
compromise with the additional NCP/NCF
properties of fast curing and wetting support.
The additional challenge of underfill voiding can
be mastered with molded underfill techniques.
2. High Volume TCB Production
When it goes to high volume production of TC
stacking several aspects play a key role:
high throughput
high yield
easy-to-use
tool-to-tool repeatability
process monitoring & alarming
High throughput is one of the key requirements,
as it directly influences the cost-of-ownership.
To go to high throughput Besi built its TCB
work horse 8800 TC on base of the fast 8800
dual head machine platform (fig. 2) which can
achieve pick & place dry-cycles of 7000 UPH.
With a target cycle time of 7 seconds the
machine will then have 1000 UPH in
production. This assumes 4 seconds for the TC
bond phase which can be achieved by means of
a rapid heater & cooler with +200°C/s, -100°C/s
temperature ramping rates. The remaining 3
seconds of the bond cycle are for pick and place
and accurate alignment, and there is still some
improvement potential for reduction of these 3
seconds, depending on the application.
Fig 2: Besi dual head TC bonder (8800 TC)
For a TC-CUF process we could see a through-
put of 1200 UPH in a project study which we
did together with an OSAT.
3. Achieving High Yield
The next key property to achieve is high yield,
which is always based on high machine
capability. In the language of TC bonding one
talks about the TC-engine of a TC bonder which
is responsible for the core capabilities:
placement accuracy
co-planarity
bond control
3. 22nd Korean Conference on Semiconductors (KCS2015) Page 3
Keeping the core-capabilities of the TC engine
under control is the basis for high yield. The
current standards for placement accuracy are
2µm@3sigma and 2µm co-planarity over the die
size under transient thermal conditions.
The bond control is heavily dependent on the
process type. For TC-NCP in general only a
precise force control combined with repeatable
temperature ramping is required, and TC-NCF
runs in a similar way. But for some NCF
materials a TC-NCF bonding process could look
more similar to a TC-CUF type, where the bond
control is much more sophisticated. Fig. 3 gives
an impression of the complexity of the TC-CUF
bond control, which has to make sure that after
liquification the solder height will be controlled
within a +/- 1.5µm tolerance band, in spite of the
thermal expansion of chip, substrate and
machine parts.
Fig. 3: Bond control for a TC-CUF process
The TC bond phase starts with a force controlled
mode (compression phase) to make sure that all
bumps have thermal contact with the substrate).
During solder liquification the bond force
collapses and due to relaxation of elastic
deformations of machine and substrate the bond
head z-position must be properly controlled with
fast reaction time in order to prevent a solder
collapse (kinematic compensation). In the
following step the solder height must be reduced
to an empirical target value which gives the
optimum reliability of the solder joints - in
parallel the z-position of the bond head will
continuously being adapted in order to compen-
sate the thermal expansion movements which
can range from 10 to 25µm.
4. Easy to Use – More than Nice-to-Have
If we consider the weird shape of the z-position
profile in fig. 3 one might ask how the teaching
of this profile can be done in a straight forward
way. On the 8800 TC bonder we solved this
issue by introduction of a new bond head
generation with 2 servo axes in z-direction (fig.
5). One axis (main z-axis) performs the touch-
down sequence and thermal expansion compen-
sation, the other (w-axis) is used for kinematic
compensation and solder height control. Fig. 4
shows how the bond control will be simplified,
if the z-position profile of fig.3 is distributed on
these two axes. After touch-down (not
displayed) the z-axis is only responsible for the
thermal expansion movement, which can be
automatically identified by proper procedures.
Fig. 4: Enhanced bond control for TC-CUF
The w-axis is initially (before and including the
force collapse) busy with the kinematic
compensation movements, which are correlated
with the force shape and can be automated by
4. 22nd Korean Conference on Semiconductors (KCS2015) Page 4
the machine. The only part which is left to the
responsibility of the process engineer is the
small piece of the w-profile which is highlighted
with the gray triangle labeled “-7µ@2s”. This
refers to the particular decision of the process
engineer to lower the initial height of the
(coined) solder cap by 7µm in a linear ramp that
lasts two seconds.
Fig 5: 7-axis TC bond head
Latest at this point the reader should have
realized that the complexity of a highly
sophisticated bond profile (z-position profile in
fig. 3) has been drastically reduced to a single
piece of ramp which can be described by the two
numbers -7µm and 2 seconds.
Easy-to-use is not a simple nice-to-have feature
in high volume production. It is a top-down
philosophy which must be coded in the DNA of
a production process and must show up again
and again as a philosophy in material sets,
procedures and tools, especially in a TC bonder,
the heart of the TCB process. An approach to
achieve easy-to-use functionality is breaking up
the complexity into parts which can be easily
understood by the people who utilize a tool or
process. This makes sure that these people are
able to come-up with creative ideas for process
improvement.
The hardware basis for the previously described
concept is the new-generation 7-axis bond head
of the 8800 TC bonder (fig.5). Besides of the
usual 3 axes for alignment (x,y and theta) the
bond head has the mentioned two bond control
axes (z and w). Additionally there are two micro
actors in x/y direction which are used for an
automatic tilt setup achieving sub-micron tilt
mismatch over the die size. Thus a second kind
of easy-to-use concept will be utilized by means
of this bond head.
5. Tool-to-Tool Repeatability
Proving a high throughput production process
that runs with high yield on one single machine
is the basis for high volume production. But
even such a process would suffer if there would
not be a fast and straight forward way to
replicate the process to another tool. We speak
of tool-to-tool repeatability when this scenario
can be accomplished and fast time-to-yield can
be achieved.
The basis for tool-to-tool repeatability is recipe
portability, which requires a strict separation of
machine parameters, which would be calibrated
with easy-to-use calibration procedures, and the
portable recipe which contains only product
specific parameters.
To measure tool-to-tool repeatability we use
several metric numbers represented by Cmk
values (machine capability numbers). For the
process temperature it is obvious that the
temperature levels must be highly repeatable, as
in particular for a multi-stack the dwell
temperature levels have to be tolerated tightly.
However, beyond the accurate temperature
levels, the whole dynamic temperature profile
needs to be repeatable, as we learn from the TC-
5. 22nd Korean Conference on Semiconductors (KCS2015) Page 5
CUF example, otherwise the open loop
controlled thermal compensation movement
would not be appropriate and would thus impact
the yield.
In fig.6 we can see, how such a metric can be
defined to measure the thermal repeatability
aspect of tool-to-tool repeatability. The two-
level reference temperature profile of fig.6 is in
fact an overlay of 15 traces.
Fig. 6 – Thermal Repeatability
By building the difference of each trace with the
average of all traces we get residual curves
which we can benchmark against a +/- 1°C
specification in order to get a Cmk number.
Following this idea we can define other Cmk
numbers, e.g. as to measure the repeatability of
the thermal compensation, or whatever we
consider as a crucial capability of the tool.
Process Monitoring and Alarming
To secure high yield in TCB mass production
the process traces need to be monitored in real
time against tolerance checking windows which
are defined in the recipe. Such an approach can
only be managed efficiently if the different tools
behave in a repeated way. Thus tool-to-tool
repeatability is a mandatory requirement for an
effective process monitoring and alarming
functionality.
Summary
Thermo-compression bonding is a key technolo-
gy for 3DI/TSV packaging, and there are now 3
different processes established. For high volume
production the throughput of a TC bonder is key,
and high capabilities are necessary for achieving
proper yield. As a TC bonding process can be
quite complex a new machine concept based on
a 7-axes bond head has been introduced, which
allows to simplify a complex bond profile by
distributing bond control over two independent
vertical position axes, where major parts of the
bond profiles can be automatically identified.
Another important property is tool-to-tool
repeatability which is key for optimized time-to-
yield. It is also the basis for an efficient real time
process monitoring and alarming system.
References
[1] Bhavani P. Dewan-Sandur et all: Thermal
Management of Die Stacking Architecture That
Includes Memory and Logic Processor; 2006
Electronic Components and Technology
Conference
[2] Deborah S. Patterson (Amkor Technology):
2.5/3D Packaging Enablement through Copper
Pillar Technology; Chip Scale Review May/June
2012
[3] Minjae Lee et all (Amkor Technology): Study
of Interconnection Process for Fine Pitch Flip
Chip; 2009 Electronic Components and
Technology Conference
[4] “Hybrid Memory Cube, Micron
Technologies,” http://www.micron.com/
innovations/hmc.html.
[5] Brian Black (AMD): Die Stacking is happe-
ning; European 3D TSV Summit, Grenoble
2015